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diff --git a/cad/nvc/Makefile b/cad/nvc/Makefile
--- a/cad/nvc/Makefile
+++ b/cad/nvc/Makefile
@@ -1,5 +1,5 @@
PORTNAME= nvc
-DISTVERSION= 1.18.1
+DISTVERSION= 1.18.2
CATEGORIES= cad
MASTER_SITES= https://www.nickg.me.uk/files/
@@ -8,7 +8,7 @@
WWW= https://www.nickg.me.uk/nvc/ \
https://github.com/nickg/nvc
-LICENSE= GPLv3
+LICENSE= GPLv3+
LICENSE_FILE= ${WRKSRC}/COPYING
ONLY_FOR_ARCHS= aarch64 amd64
diff --git a/cad/nvc/distinfo b/cad/nvc/distinfo
--- a/cad/nvc/distinfo
+++ b/cad/nvc/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1760851919
-SHA256 (nvc-1.18.1.tar.gz) = dcb2cb651ee13df384a47c55a596842106f6cca9492f192729e566648817e321
-SIZE (nvc-1.18.1.tar.gz) = 2599248
+TIMESTAMP = 1766493577
+SHA256 (nvc-1.18.2.tar.gz) = ee34522a04c49f2a73ff4367088ded9674d726b44fd480995df8ac90e84271d8
+SIZE (nvc-1.18.2.tar.gz) = 2601236
diff --git a/cad/nvc/pkg-descr b/cad/nvc/pkg-descr
--- a/cad/nvc/pkg-descr
+++ b/cad/nvc/pkg-descr
@@ -1,3 +1,15 @@
NVC is a GPLv3 VHDL compiler and simulator aiming for IEEE 1076-2002 compliance.
-See these blog posts for background information. NVC has been successfully used
-to simulate several real-world designs.
+
+- NVC supports almost all of VHDL-2008 with the exception of PSL, and it has
+been successfully used to simulate several real-world designs. Experimental
+support for Verilog and VHDL-2019 is under development.
+
+- NVC has a particular emphasis on simulation performance and uses LLVM to
+compile VHDL to native machine code.
+
+- NVC is not a synthesizer. That is, it does not output something that could be
+used to program an FPGA or ASIC. It implements only the simulation behaviour of
+the language as described by the IEEE 1076 standard.
+
+- NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and
+cocotb.

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