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Index: sys/dev/nvme/nvme.h
===================================================================
--- sys/dev/nvme/nvme.h
+++ sys/dev/nvme/nvme.h
@@ -632,7 +632,7 @@
/* dword 3 */
uint16_t cid; /* command identifier */
uint16_t status;
-} __packed;
+};
_Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
Index: usr.sbin/bhyve/pci_emul.h
===================================================================
--- usr.sbin/bhyve/pci_emul.h
+++ usr.sbin/bhyve/pci_emul.h
@@ -102,7 +102,7 @@
uint32_t vector_control;
} __packed;
-/*
+/*
* In case the structure is modified to hold extra information, use a define
* for the size that should be emulated.
*/
@@ -148,7 +148,7 @@
int table_count;
uint32_t pba_offset;
int pba_size;
- int function_mask;
+ int function_mask;
struct msix_table_entry *table; /* allocated at runtime */
void *pba_page;
int pba_page_offset;
@@ -176,7 +176,7 @@
uint16_t msgctrl;
uint32_t table_info; /* bar index and offset within it */
uint32_t pba_info; /* bar index and offset within it */
-} __packed;
+};
static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
struct pciecap {
@@ -254,21 +254,21 @@
int pci_resume(struct vmctx *ctx, const char *dev_name);
#endif
-static __inline void
+static __inline void
pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
{
assert(offset <= PCI_REGMAX);
*(uint8_t *)(pi->pi_cfgdata + offset) = val;
}
-static __inline void
+static __inline void
pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
{
assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
*(uint16_t *)(pi->pi_cfgdata + offset) = val;
}
-static __inline void
+static __inline void
pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
{
assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
Index: usr.sbin/bhyve/pci_xhci.c
===================================================================
--- usr.sbin/bhyve/pci_xhci.c
+++ usr.sbin/bhyve/pci_xhci.c
@@ -191,7 +191,7 @@
uint32_t portpmsc; /* port pwr mgmt status & control */
uint32_t portli; /* port link info */
uint32_t porthlpmc; /* port hardware LPM control */
-} __packed;
+};
#define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10)
/* xHC operational registers */
@@ -489,7 +489,7 @@
p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK |
XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
-
+
if (XHCI_DEVINST_PTR(sc, port))
p->portsc |= XHCI_PS_CCS;
@@ -545,7 +545,7 @@
break;
}
break;
- case 4:
+ case 4:
/* Port power management status and control register */
p->portpmsc = value;
break;
@@ -598,7 +598,7 @@
if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {
if (guestaddr)
*guestaddr = curtrb->qwTrb0 & ~0xFUL;
-
+
next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);
} else {
if (guestaddr)
@@ -1262,7 +1262,7 @@
cmderr = pci_xhci_find_stream(sc, ep_ctx, streamid, &sctx);
if (sctx != NULL) {
assert(devep->ep_sctx != NULL);
-
+
devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;
devep->ep_sctx_trbs[streamid].ringaddr =
trb->qwTrb0 & ~0xF;
@@ -1381,7 +1381,7 @@
while (1) {
sc->opregs.cr_p = trb;
-
+
type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=
@@ -1476,7 +1476,7 @@
}
if (type != XHCI_TRB_TYPE_LINK) {
- /*
+ /*
* insert command completion event and assert intr
*/
evtrb.qwTrb0 = crcr;
@@ -1604,7 +1604,7 @@
if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) {
DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla));
evtrb.qwTrb0 = trb->qwTrb0;
- evtrb.dwTrb2 = (edtla & 0xFFFFF) |
+ evtrb.dwTrb2 = (edtla & 0xFFFFF) |
XHCI_TRB_2_ERROR_SET(err);
evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;
edtla = 0;
@@ -2554,7 +2554,7 @@
if (dev) {
port->portsc = XHCI_PS_CCS | /* connected */
XHCI_PS_PP; /* port power */
-
+
if (dev->dev_ue->ue_usbver == 2) {
port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) |
XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
@@ -2563,7 +2563,7 @@
XHCI_PS_PED | /* enabled */
XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
}
-
+
DPRINTF(("Init port %d 0x%x", portn, port->portsc));
} else {
port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP;

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