Page MenuHomeFreeBSD
Files F142406439

D8557.diff
No OneTemporary
Actions

D8557.diff
View Options

Index: head/sys/mips/atheros/ar531x/files.ar5315
===================================================================
--- head/sys/mips/atheros/ar531x/files.ar5315
+++ head/sys/mips/atheros/ar531x/files.ar5315
@@ -14,17 +14,18 @@
mips/atheros/ar531x/ar5312_chip.c standard
mips/atheros/ar71xx_bus_space_reversed.c standard
-#mips/mips/intr_machdep.c standard
mips/mips/tick.c standard
dev/etherswitch/e6000sw/e6060sw.c optional etherswitch
-dev/etherswitch/realtek/rtl830x.c optional etherswitch
# Hack to reuse ARM intrng code
-kern/subr_intr.c standard
-kern/msi_if.m standard
-kern/pic_if.m standard
+kern/subr_intr.c optional intrng
+kern/msi_if.m optional intrng
+kern/pic_if.m optional intrng
# Intrng compatible MIPS32 interrupt controller
-mips/mips/mips_pic.c standard
+mips/mips/mips_pic.c optional intrng
+
+# Non Intrng
+mips/mips/intr_machdep.c optional !intrng
Index: head/sys/mips/atheros/ar531x/if_are.c
===================================================================
--- head/sys/mips/atheros/ar531x/if_are.c
+++ head/sys/mips/atheros/ar531x/if_are.c
@@ -35,7 +35,7 @@
__FBSDID("$FreeBSD$");
/*
- * AR231x Ethernet interface driver
+ * AR531x Ethernet interface driver
* copy from mips/idt/if_kr.c and netbsd code
*/
#include <sys/param.h>
@@ -90,8 +90,6 @@
#include <mips/atheros/ar531x/ar5315_setup.h>
#include <mips/atheros/ar531x/if_arereg.h>
-//#define ARE_DEBUG
-
#ifdef ARE_DEBUG
void dump_txdesc(struct are_softc *, int);
void dump_status_reg(struct are_softc *);
@@ -226,7 +224,7 @@
unit = device_get_unit(dev);
sc->are_dev = dev;
- // hardcode macaddress
+ /* hardcode macaddress */
sc->are_eaddr[0] = 0x00;
sc->are_eaddr[1] = 0x0C;
sc->are_eaddr[2] = 0x42;
@@ -234,7 +232,7 @@
sc->are_eaddr[4] = 0x5E;
sc->are_eaddr[5] = 0x6B;
- // try to get from hints
+ /* try to get from hints */
if (!resource_string_value(device_get_name(dev),
device_get_unit(dev), "macaddr", (const char **)&local_macstr)) {
uint32_t tmpmac[ETHER_ADDR_LEN];
@@ -302,12 +300,16 @@
ifp->if_ioctl = are_ioctl;
ifp->if_start = are_start;
ifp->if_init = are_init;
+ sc->are_if_flags = ifp->if_flags;
/* XXX: add real size */
IFQ_SET_MAXLEN(&ifp->if_snd, 9);
ifp->if_snd.ifq_maxlen = 9;
IFQ_SET_READY(&ifp->if_snd);
+ /* Tell the upper layer(s) we support long frames. */
+ ifp->if_capabilities |= IFCAP_VLAN_MTU;
+
ifp->if_capenable = ifp->if_capabilities;
if (are_dma_alloc(sc) != 0) {
@@ -315,14 +317,6 @@
goto fail;
}
- /* TODO: calculate prescale */
-/*
- CSR_WRITE_4(sc, ARE_ETHMCP, (165000000 / (1250000 + 1)) & ~1);
-
- CSR_WRITE_4(sc, ARE_MIIMCFG, ARE_MIIMCFG_R);
- DELAY(1000);
- CSR_WRITE_4(sc, ARE_MIIMCFG, 0);
-*/
CSR_WRITE_4(sc, CSR_BUSMODE, BUSMODE_SWR);
DELAY(1000);
@@ -350,11 +344,11 @@
#ifdef INTRNG
char *name;
- if(ar531x_soc >= AR531X_SOC_AR5315) {
+ if (ar531x_soc >= AR531X_SOC_AR5315) {
enetirq = AR5315_CPU_IRQ_ENET;
name = "enet";
} else {
- if(device_get_unit(dev) == 0) {
+ if (device_get_unit(dev) == 0) {
enetirq = AR5312_IRQ_ENET0;
name = "enet0";
} else {
@@ -465,7 +459,6 @@
addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT);
CSR_WRITE_4(sc, CSR_MIIADDR, addr);
-// AE_BARRIER(sc);
for (i = 0; i < 100000000; i++) {
if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0)
break;
@@ -488,7 +481,6 @@
addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) |
MIIADDR_WRITE;
CSR_WRITE_4(sc, CSR_MIIADDR, addr);
-// AE_BARRIER(sc);
for (i = 0; i < 100000000; i++) {
if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0)
@@ -610,7 +602,6 @@
*/
CSR_WRITE_4(sc, CSR_BUSMODE,
/* XXX: not sure if this is a good thing or not... */
- //BUSMODE_ALIGN_16B |
BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW);
/*
@@ -648,15 +639,16 @@
/*
* Start the mac.
*/
- CSR_WRITE_4(sc, CSR_MACCTL, CSR_READ_4(sc, CSR_MACCTL) |
- (MACCTL_RE | MACCTL_TE));
+ CSR_WRITE_4(sc, CSR_FLOWC, FLOWC_FCE);
+ CSR_WRITE_4(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE |
+ MACCTL_PM | MACCTL_FDX | MACCTL_HBD | MACCTL_RA);
/*
* Write out the opmode.
*/
- CSR_WRITE_4(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST |
-// ae_txthresh[sc->sc_txthresh].txth_opmode);
+ CSR_WRITE_4(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | OPMODE_SF |
OPMODE_TR_64);
+
/*
* Start the receive process.
*/
@@ -741,7 +733,6 @@
if (i == 0)
desc->are_devcs |= ADCTL_Tx_FS;
desc->are_addr = txsegs[i].ds_addr;
-// desc->are_link = 0;
/* link with previous descriptor */
if (prev_desc)
prev_desc->are_link = ARE_TX_RING_ADDR(sc, prod);
@@ -850,6 +841,36 @@
}
+static int
+are_set_filter(struct are_softc *sc)
+{
+ struct ifnet *ifp;
+ int mchash[2];
+ int macctl;
+
+ ifp = sc->are_ifp;
+
+ macctl = CSR_READ_4(sc, CSR_MACCTL);
+ macctl &= ~(MACCTL_PR | MACCTL_PM);
+ macctl |= MACCTL_HBD;
+
+ if (ifp->if_flags & IFF_PROMISC)
+ macctl |= MACCTL_PR;
+
+ /* Todo: hash table set.
+ * But I don't know how to use multicast hash table at this soc.
+ */
+
+ /* this is allmulti */
+ mchash[0] = mchash[1] = 0xffffffff;
+ macctl |= MACCTL_PM;
+
+ CSR_WRITE_4(sc, CSR_HTLO, mchash[0]);
+ CSR_WRITE_4(sc, CSR_HTHI, mchash[1]);
+ CSR_WRITE_4(sc, CSR_MACCTL, macctl);
+
+ return 0;
+}
static int
are_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
@@ -863,7 +884,6 @@
switch (command) {
case SIOCSIFFLAGS:
-#if 0
ARE_LOCK(sc);
if (ifp->if_flags & IFF_UP) {
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
@@ -880,16 +900,13 @@
}
sc->are_if_flags = ifp->if_flags;
ARE_UNLOCK(sc);
-#endif
error = 0;
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
-#if 0
ARE_LOCK(sc);
are_set_filter(sc);
ARE_UNLOCK(sc);
-#endif
error = 0;
break;
case SIOCGIFMEDIA:
@@ -903,28 +920,6 @@
break;
case SIOCSIFCAP:
error = 0;
-#if 0
- mask = ifr->ifr_reqcap ^ ifp->if_capenable;
- if ((mask & IFCAP_HWCSUM) != 0) {
- ifp->if_capenable ^= IFCAP_HWCSUM;
- if ((IFCAP_HWCSUM & ifp->if_capenable) &&
- (IFCAP_HWCSUM & ifp->if_capabilities))
- ifp->if_hwassist = ARE_CSUM_FEATURES;
- else
- ifp->if_hwassist = 0;
- }
- if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
- ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
- if (IFCAP_VLAN_HWTAGGING & ifp->if_capenable &&
- IFCAP_VLAN_HWTAGGING & ifp->if_capabilities &&
- ifp->if_drv_flags & IFF_DRV_RUNNING) {
- ARE_LOCK(sc);
- are_vlan_setup(sc);
- ARE_UNLOCK(sc);
- }
- }
- VLAN_CAPABILITIES(ifp);
-#endif
break;
default:
error = ether_ioctl(ifp, command, data);
@@ -1343,7 +1338,7 @@
return (ENOBUFS);
m->m_len = m->m_pkthdr.len = MCLBYTES;
- // tcp header boundary margin
+ /* tcp header boundary margin */
m_adj(m, 4);
if (bus_dmamap_load_mbuf_sg(sc->are_cdata.are_rx_tag,
@@ -1355,9 +1350,11 @@
rxd = &sc->are_cdata.are_rxdesc[idx];
if (rxd->rx_m != NULL) {
-// This code make bug. Make scranble on buffer data.
-// bus_dmamap_sync(sc->are_cdata.are_rx_tag, rxd->rx_dmamap,
-// BUS_DMASYNC_POSTREAD);
+ /*
+ * THis is if_kr.c original code but make bug. Make scranble on buffer data.
+ * bus_dmamap_sync(sc->are_cdata.are_rx_tag, rxd->rx_dmamap,
+ * BUS_DMASYNC_POSTREAD);
+ */
bus_dmamap_unload(sc->are_cdata.are_rx_tag, rxd->rx_dmamap);
}
map = rxd->rx_dmamap;
@@ -1551,7 +1548,6 @@
struct are_softc *sc = arg;
uint32_t status;
struct ifnet *ifp = sc->are_ifp;
-//kdb_break();
ARE_LOCK(sc);
Index: head/sys/mips/atheros/ar531x/if_arereg.h
===================================================================
--- head/sys/mips/atheros/ar531x/if_arereg.h
+++ head/sys/mips/atheros/ar531x/if_arereg.h
@@ -37,17 +37,17 @@
uint32_t are_link;
};
-#define ARE_DMASIZE(len) ((len) & ((1 << 11)-1))
-#define ARE_PKTSIZE(len) ((len & 0xffff0000) >> 16)
+#define ARE_DMASIZE(len) ((len) & ((1 << 11)-1))
+#define ARE_PKTSIZE(len) ((len & 0xffff0000) >> 16)
-#define ARE_RX_RING_CNT 128
-#define ARE_TX_RING_CNT 128
-#define ARE_TX_RING_SIZE sizeof(struct are_desc) * ARE_TX_RING_CNT
-#define ARE_RX_RING_SIZE sizeof(struct are_desc) * ARE_RX_RING_CNT
-#define ARE_RING_ALIGN sizeof(struct are_desc)
-#define ARE_RX_ALIGN sizeof(uint32_t)
-#define ARE_MAXFRAGS 8
-#define ARE_TX_INTR_THRESH 8
+#define ARE_RX_RING_CNT 128
+#define ARE_TX_RING_CNT 128
+#define ARE_TX_RING_SIZE sizeof(struct are_desc) * ARE_TX_RING_CNT
+#define ARE_RX_RING_SIZE sizeof(struct are_desc) * ARE_RX_RING_CNT
+#define ARE_RING_ALIGN sizeof(struct are_desc)
+#define ARE_RX_ALIGN sizeof(uint32_t)
+#define ARE_MAXFRAGS 8
+#define ARE_TX_INTR_THRESH 8
#define ARE_TX_RING_ADDR(sc, i) \
((sc)->are_rdata.are_tx_ring_paddr + sizeof(struct are_desc) * (i))
@@ -123,6 +123,7 @@
struct are_ring_data are_rdata;
int are_link_status;
int are_detach;
+ int are_if_flags; /* last if flags */
};
#define ARE_LOCK(_sc) mtx_lock(&(_sc)->are_mtx)
@@ -132,11 +133,11 @@
/*
* register space access macros
*/
-#define CSR_WRITE_4(sc, reg, val) \
- bus_space_write_4(sc->are_btag, sc->are_bhandle, reg, val)
+#define CSR_WRITE_4(sc, reg, val) \
+ bus_space_write_4(sc->are_btag, sc->are_bhandle, reg, val)
-#define CSR_READ_4(sc, reg) \
- bus_space_read_4(sc->are_btag, sc->are_bhandle, reg)
+#define CSR_READ_4(sc, reg) \
+ bus_space_read_4(sc->are_btag, sc->are_bhandle, reg)
/* $NetBSD: aereg.h,v 1.2 2008/04/28 20:23:28 martin Exp $ */

File Metadata

Mime Type
text/plain
Expires
Tue, Jan 20, 5:06 PM (12 h, 15 m)
Storage Engine
blob
Storage Format
Raw Data
Storage Handle
27766308
Default Alt Text
D8557.diff (9 KB)

Event Timeline