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Index: head/sys/dev/e1000/e1000_82571.c
===================================================================
--- head/sys/dev/e1000/e1000_82571.c
+++ head/sys/dev/e1000/e1000_82571.c
@@ -396,7 +396,7 @@
}
/* Ensure that the inter-port SWSM.SMBI lock bit is clear before
- * first NVM or PHY acess. This should be done for single-port
+ * first NVM or PHY access. This should be done for single-port
* devices, and for one port only on dual-port devices so that
* for those devices we can still use the SMBI lock to synchronize
* inter-port accesses to the PHY & NVM.
Index: head/sys/dev/e1000/e1000_mbx.c
===================================================================
--- head/sys/dev/e1000/e1000_mbx.c
+++ head/sys/dev/e1000/e1000_mbx.c
@@ -67,7 +67,7 @@
* @size: Length of buffer
* @mbx_id: id of mailbox to read
*
- * returns SUCCESS if it successfuly read message from buffer
+ * returns SUCCESS if it successfully read message from buffer
**/
s32 e1000_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)
{
@@ -493,7 +493,7 @@
* @size: Length of buffer
* @mbx_id: id of mailbox to read
*
- * returns SUCCESS if it successfuly read message from buffer
+ * returns SUCCESS if it successfully read message from buffer
**/
static s32 e1000_read_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size,
u16 E1000_UNUSEDARG mbx_id)
Index: head/sys/dev/e1000/if_em.c
===================================================================
--- head/sys/dev/e1000/if_em.c
+++ head/sys/dev/e1000/if_em.c
@@ -582,7 +582,7 @@
}
/*
** In the new SPT device flash is not a
- ** seperate BAR, rather it is also in BAR0,
+ ** separate BAR, rather it is also in BAR0,
** so use the same tag and an offset handle for the
** FLASH read/write macros in the shared code.
*/
@@ -1929,7 +1929,7 @@
* so we firstly get a writable mbuf chain then coalesce ethernet/
* IP/TCP header into a single buffer to meet the requirement of
* controller. This also simplifies IP/TCP/UDP checksum offloading
- * which also has similiar restrictions.
+ * which also has similar restrictions.
*/
if (do_tso || m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) {
if (do_tso || (m_head->m_next != NULL &&
@@ -2595,7 +2595,7 @@
*
* Setup the MSIX Interrupt handlers
* This is not really Multiqueue, rather
- * its just seperate interrupt vectors
+ * its just separate interrupt vectors
* for TX, RX, and Link.
*
**********************************************************************/
@@ -3083,7 +3083,7 @@
* received after sending an XOFF.
* - Low water mark works best when it is very near the high water mark.
* This allows the receiver to restart by sending XON when it has
- * drained a bit. Here we use an arbitary value of 1500 which will
+ * drained a bit. Here we use an arbitrary value of 1500 which will
* restart after one full frame is pulled from the buffer. There
* could be several smaller frames in the buffer and if so they will
* not trigger the XON until their total number reduces the buffer
Index: head/sys/dev/e1000/if_igb.c
===================================================================
--- head/sys/dev/e1000/if_igb.c
+++ head/sys/dev/e1000/if_igb.c
@@ -304,7 +304,7 @@
/*
** Header split causes the packet header to
-** be dma'd to a seperate mbuf from the payload.
+** be dma'd to a separate mbuf from the payload.
** this can have memory alignment benefits. But
** another plus is that small packets often fit
** into the header and thus use no cluster. Its
@@ -4483,7 +4483,7 @@
** Now set up the LRO interface, we
** also only do head split when LRO
** is enabled, since so often they
- ** are undesireable in similar setups.
+ ** are undesirable in similar setups.
*/
if (ifp->if_capenable & IFCAP_LRO) {
error = tcp_lro_init(lro);
Index: head/sys/dev/e1000/if_lem.c
===================================================================
--- head/sys/dev/e1000/if_lem.c
+++ head/sys/dev/e1000/if_lem.c
@@ -2412,7 +2412,7 @@
* received after sending an XOFF.
* - Low water mark works best when it is very near the high water mark.
* This allows the receiver to restart by sending XON when it has
- * drained a bit. Here we use an arbitary value of 1500 which will
+ * drained a bit. Here we use an arbitrary value of 1500 which will
* restart after one full frame is pulled from the buffer. There
* could be several smaller frames in the buffer and if so they will
* not trigger the XON until their total number reduces the buffer
@@ -3838,7 +3838,7 @@
* copy ethernet header to the new mbuf. The new mbuf is prepended into the
* existing mbuf chain.
*
- * Be aware, best performance of the 8254x is achived only when jumbo frame is
+ * Be aware, best performance of the 8254x is achieved only when jumbo frame is
* not used at all on architectures with strict alignment.
*/
static int
Index: head/sys/dev/ixgbe/if_ixv.c
===================================================================
--- head/sys/dev/ixgbe/if_ixv.c
+++ head/sys/dev/ixgbe/if_ixv.c
@@ -195,7 +195,7 @@
/*
* Header split: this causes the hardware to DMA
- * the header into a seperate mbuf from the payload,
+ * the header into a separate mbuf from the payload,
* it can be a performance win in some workloads, but
* in others it actually hurts, its off by default.
*/
@@ -1141,7 +1141,7 @@
}
- /* Only truely watchdog if all queues show hung */
+ /* Only truly watchdog if all queues show hung */
if (hung == adapter->num_queues)
goto watchdog;
else if (queues != 0) { /* Force an IRQ on queues with work */
@@ -1958,7 +1958,7 @@
}
/*
-** The VF stats registers never have a truely virgin
+** The VF stats registers never have a truly virgin
** starting point, so this routine tries to make an
** artificial one, marking ground zero on attach as
** it were.
Index: head/sys/dev/ixgbe/ixgbe_api.c
===================================================================
--- head/sys/dev/ixgbe/ixgbe_api.c
+++ head/sys/dev/ixgbe/ixgbe_api.c
@@ -879,7 +879,7 @@
* @vmdq: VMDq pool to assign
*
* Puts an ethernet address into a receive address register, or
- * finds the rar that it is aleady in; adds to the pool list
+ * finds the rar that it is already in; adds to the pool list
**/
s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
{
Index: head/sys/dev/ixgbe/ixgbe_common.c
===================================================================
--- head/sys/dev/ixgbe/ixgbe_common.c
+++ head/sys/dev/ixgbe/ixgbe_common.c
@@ -3610,7 +3610,7 @@
* @vmdq: VMDq pool to assign
*
* Puts an ethernet address into a receive address register, or
- * finds the rar that it is aleady in; adds to the pool list
+ * finds the rar that it is already in; adds to the pool list
**/
s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
{
Index: head/sys/dev/ixgbe/ixgbe_mbx.c
===================================================================
--- head/sys/dev/ixgbe/ixgbe_mbx.c
+++ head/sys/dev/ixgbe/ixgbe_mbx.c
@@ -42,7 +42,7 @@
* @size: Length of buffer
* @mbx_id: id of mailbox to read
*
- * returns SUCCESS if it successfuly read message from buffer
+ * returns SUCCESS if it successfully read message from buffer
**/
s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
{
@@ -462,7 +462,7 @@
* @size: Length of buffer
* @mbx_id: id of mailbox to read
*
- * returns SUCCESS if it successfuly read message from buffer
+ * returns SUCCESS if it successfully read message from buffer
**/
static s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,
u16 mbx_id)
Index: head/sys/dev/ixgbe/ixgbe_type.h
===================================================================
--- head/sys/dev/ixgbe/ixgbe_type.h
+++ head/sys/dev/ixgbe/ixgbe_type.h
@@ -47,7 +47,7 @@
*
* - IXGBE_ERROR_POLLING
* This category is for errors related to polling/timeout issues and should be
- * used in any case where the timeout occured, or a failure to obtain a lock, or
+ * used in any case where the timeout occurred, or a failure to obtain a lock, or
* failure to receive data within the time limit.
*
* - IXGBE_ERROR_CAUTION
@@ -2078,7 +2078,7 @@
#define IXGBE_MACC_FS 0x00040000
#define IXGBE_MAC_RX2TX_LPBK 0x00000002
-/* Veto Bit definiton */
+/* Veto Bit definition */
#define IXGBE_MMNGC_MNG_VETO 0x00000001
/* LINKS Bit Masks */

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