Page MenuHomeFreeBSD
Files F140079725

D2198.diff
No OneTemporary
Actions

D2198.diff
View Options

Index: sys/arm/arm/generic_timer.c
===================================================================
--- sys/arm/arm/generic_timer.c
+++ sys/arm/arm/generic_timer.c
@@ -105,12 +105,7 @@
static int
get_freq(void)
{
- uint32_t val;
-
- /* cntfrq */
- __asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
-
- return (val);
+ return (cp15_cntfrq_get());
}
static long
@@ -120,11 +115,9 @@
isb();
if (physical)
- /* cntpct */
- __asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
+ val = cp15_cntpct_get();
else
- /* cntvct */
- __asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (val));
+ val = cp15_cntvct_get();
return (val);
}
@@ -134,13 +127,9 @@
{
if (physical)
- /* cntp_ctl */
- __asm volatile("mcr p15, 0, %[val], c14, c2, 1" : :
- [val] "r" (val));
+ cp15_cntp_ctl_set(val);
else
- /* cntv_ctl */
- __asm volatile("mcr p15, 0, %[val], c14, c3, 1" : :
- [val] "r" (val));
+ cp15_cntv_ctl_set(val);
isb();
return (0);
@@ -151,13 +140,9 @@
{
if (physical)
- /* cntp_tval */
- __asm volatile("mcr p15, 0, %[val], c14, c2, 0" : :
- [val] "r" (val));
+ cp15_cntp_tval_set(val);
else
- /* cntv_tval */
- __asm volatile("mcr p15, 0, %[val], c14, c3, 0" : :
- [val] "r" (val));
+ cp15_cntv_tval_set(val);
isb();
return (0);
@@ -169,11 +154,9 @@
uint32_t val;
if (physical)
- /* cntp_ctl */
- __asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+ val = cp15_cntp_ctl_get();
else
- /* cntv_ctl */
- __asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+ val = cp15_cntv_ctl_get();
return (val);
}
@@ -183,10 +166,10 @@
{
uint32_t cntkctl;
- __asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
+ cntkctl = cp15_cntkctl_get();
cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
- __asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
+ cp15_cntkctl_set(cntkctl);
isb();
}
Index: sys/arm/include/cpu-v6.h
===================================================================
--- sys/arm/include/cpu-v6.h
+++ sys/arm/include/cpu-v6.h
@@ -54,6 +54,15 @@
return(reg); \
}
+#define _R64F0(fname, aname) \
+static __inline uint64_t \
+fname(void) \
+{ \
+ uint64_t reg; \
+ __asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
+ return(reg); \
+}
+
#define _WF0(fname, aname...) \
static __inline void \
fname(void) \
@@ -68,6 +77,13 @@
__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
}
+#define _W64F1(fname, aname...) \
+static __inline void \
+fname(uint64_t reg) \
+{ \
+ __asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \
+}
+
/*
* Raw CP15 maintenance operations
* !!! not for external use !!!
@@ -189,6 +205,37 @@
_RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
_WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
+/* Generic Timer registers - only use when you know the hardware is available */
+_RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
+_WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
+_RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
+_WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
+_RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
+_WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
+_RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
+_WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
+_RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
+_WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
+_RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
+_WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
+_RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
+_WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
+_RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
+_WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
+_RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
+_WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
+
+_R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
+_R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
+_R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
+_W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
+_R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
+_W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
+_R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
+_W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
+_R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
+_W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
+
#undef _FX
#undef _RF0
#undef _WF0
Index: sys/arm/include/sysreg.h
===================================================================
--- sys/arm/include/sysreg.h
+++ sys/arm/include/sysreg.h
@@ -257,6 +257,28 @@
#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
/*
+ * CP15 C14 registers
+ * These are the Generic Timer registers and may be unallocated on some SoCs.
+ * Only use these when you know the Generic Timer is available.
+ */
+#define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */
+#define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */
+#define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */
+#define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */
+#define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */
+#define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */
+#define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */
+#define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */
+#define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */
+/* 64-bit registers for use with mcrr/mrrc */
+#define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */
+#define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */
+#define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */
+#define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */
+#define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */
+#define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */
+
+/*
* CP15 C15 registers
*/
#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */

File Metadata

Mime Type
text/plain
Expires
Sat, Dec 20, 11:26 PM (13 h, 4 m)
Storage Engine
blob
Storage Format
Raw Data
Storage Handle
27102557
Default Alt Text
D2198.diff (6 KB)

Event Timeline