Page MenuHomeFreeBSD
Files F137989431

D9836.id25797.diff
No OneTemporary
Actions

D9836.id25797.diff
View Options

Index: sys/arm/altera/socfpga/socfpga_machdep.c
===================================================================
--- sys/arm/altera/socfpga/socfpga_machdep.c
+++ sys/arm/altera/socfpga/socfpga_machdep.c
@@ -54,6 +54,7 @@
#include "platform_if.h"
+#if defined(SOC_ALTERA_CYCLONE5)
static int
socfpga_devmap_init(platform_t plat)
{
@@ -82,7 +83,9 @@
return (0);
}
+#endif
+#if defined(SOC_ALTERA_ARRIA10)
static int
socfpga_a10_devmap_init(platform_t plat)
{
@@ -101,9 +104,10 @@
return (0);
}
+#endif
static void
-_socfpga_cpu_reset(platform_t plat, uint32_t reg)
+_socfpga_cpu_reset(bus_size_t reg)
{
uint32_t paddr;
bus_addr_t vaddr;
@@ -127,20 +131,25 @@
while (1);
}
+#if defined(SOC_ALTERA_CYCLONE5)
static void
socfpga_cpu_reset(platform_t plat)
{
- _socfpga_cpu_reset(plat, RSTMGR_CTRL);
+ _socfpga_cpu_reset(RSTMGR_CTRL);
}
+#endif
+#if defined(SOC_ALTERA_ARRIA10)
static void
socfpga_a10_cpu_reset(platform_t plat)
{
- _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
+ _socfpga_cpu_reset(RSTMGR_A10_CTRL);
}
+#endif
+#if defined(SOC_ALTERA_CYCLONE5)
static platform_method_t socfpga_methods[] = {
PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init),
PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset),
@@ -151,7 +160,9 @@
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
+#endif
+#if defined(SOC_ALTERA_ARRIA10)
static platform_method_t socfpga_a10_methods[] = {
PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init),
PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset),
@@ -162,3 +173,4 @@
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);
+#endif
Index: sys/arm/altera/socfpga/socfpga_mp.c
===================================================================
--- sys/arm/altera/socfpga/socfpga_mp.c
+++ sys/arm/altera/socfpga/socfpga_mp.c
@@ -75,8 +75,8 @@
#define RAM_PHYSBASE 0x0
#define RAM_SIZE 0x1000
-#define SOCFPGA_SOCKIT 1
-#define SOCFPGA_SOCDK 2
+#define SOCFPGA_CYCLONE5 1
+#define SOCFPGA_ARRIA10 2
extern char *mpentry_addr;
static void socfpga_trampoline(void);
@@ -112,22 +112,31 @@
mp_maxid = ncpu - 1;
}
-
static void
-_socfpga_mp_start_ap(platform_t plat, uint32_t platid)
+_socfpga_mp_start_ap(uint32_t platid)
{
bus_space_handle_t scu, rst, ram;
int reg;
- if (platid == SOCFPGA_SOCDK) {
+ switch (platid) {
+#if defined(SOC_ALTERA_ARRIA10)
+ case SOCFPGA_ARRIA10:
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
SCU_SIZE, 0, &scu) != 0)
- panic("Couldn't map the SCU\n");
- } else {
+ panic("Couldn't map the SCU\n");
+ break;
+#endif
+#if defined(SOC_ALTERA_CYCLONE5)
+ case SOCFPGA_CYCLONE5:
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0)
- panic("Couldn't map the SCU\n");
+ panic("Couldn't map the SCU\n");
+ break;
+#endif
+ default:
+ panic("Unknown platform id %d\n", platid);
}
+
if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
RSTMGR_SIZE, 0, &rst) != 0)
panic("Couldn't map the reset manager (RSTMGR)\n");
@@ -149,12 +158,21 @@
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
/* Put CPU1 to reset state */
- if (platid == SOCFPGA_SOCDK) {
+ switch (platid) {
+#if defined(SOC_ALTERA_ARRIA10)
+ case SOCFPGA_ARRIA10:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
- } else {
+ break;
+#endif
+#if defined(SOC_ALTERA_CYCLONE5)
+ case SOCFPGA_CYCLONE5:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, MPUMODRST_CPU1);
+ break;
+#endif
+ default:
+ panic("Unknown platform id %d\n", platid);
}
/* Enable the SCU, then clean the cache on this core */
@@ -170,12 +188,21 @@
dcache_wbinv_poc_all();
/* Put CPU1 out from reset */
- if (platid == SOCFPGA_SOCDK) {
+ switch (platid) {
+#if defined(SOC_ALTERA_ARRIA10)
+ case SOCFPGA_ARRIA10:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, 0);
- } else {
+ break;
+#endif
+#if defined(SOC_ALTERA_CYCLONE5)
+ case SOCFPGA_CYCLONE5:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, 0);
+ break;
+#endif
+ default:
+ panic("Unknown platform id %d\n", platid);
}
dsb();
@@ -186,17 +213,20 @@
bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
}
+#if defined(SOC_ALTERA_ARRIA10)
void
socfpga_a10_mp_start_ap(platform_t plat)
{
- _socfpga_mp_start_ap(plat, SOCFPGA_SOCDK);
+ _socfpga_mp_start_ap(SOCFPGA_ARRIA10);
}
+#endif
+#if defined(SOC_ALTERA_CYCLONE5)
void
socfpga_mp_start_ap(platform_t plat)
{
- _socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT);
+ _socfpga_mp_start_ap(SOCFPGA_CYCLONE5);
}
-
+#endif
Index: sys/arm/conf/SOCFPGA
===================================================================
--- sys/arm/conf/SOCFPGA
+++ sys/arm/conf/SOCFPGA
@@ -31,6 +31,9 @@
options SMP # Enable multiple cores
options MULTIDELAY
+options SOC_ALTERA_CYCLONE5
+options SOC_ALTERA_ARRIA10
+
# NFS root from boopt/dhcp
#options BOOTP
#options BOOTP_NFSROOT
Index: sys/conf/options.arm
===================================================================
--- sys/conf/options.arm
+++ sys/conf/options.arm
@@ -50,6 +50,8 @@
SOC_ALLWINNER_A33 opt_global.h
SOC_ALLWINNER_A83T opt_global.h
SOC_ALLWINNER_H3 opt_global.h
+SOC_ALTERA_CYCLONE5 opt_global.h
+SOC_ALTERA_ARRIA10 opt_global.h
SOC_BCM2835 opt_global.h
SOC_BCM2836 opt_global.h
SOC_IMX51 opt_global.h

File Metadata

Mime Type
text/plain
Expires
Fri, Nov 28, 10:37 PM (12 h, 32 m)
Storage Engine
blob
Storage Format
Raw Data
Storage Handle
26306244
Default Alt Text
D9836.id25797.diff (5 KB)

Event Timeline