D44096.diff
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	diff --git a/sys/arm64/arm64/gic_v3_reg.h b/sys/arm64/arm64/gic_v3_reg.h
	--- a/sys/arm64/arm64/gic_v3_reg.h
	+++ b/sys/arm64/arm64/gic_v3_reg.h
	@@ -182,6 +182,15 @@
	#define GICR_PROPBASER_OUTER_CACHE_MASK \
	(0x7UL << GICR_PROPBASER_OUTER_CACHE_SHIFT)

	+/*
	+ * The PROPBASER LPI Configuration Table is 4k aligned, so bits 51:12 are
	+ * defined to be the PA, for 40 potentially significant bits.
	+ */
	+#define GICR_PROPBASER_PA_SHIFT 12
	+#define GICR_PROPBASER_PA_SIZE 40
	+#define GICR_PROPBASER_PA_MASK \
	+ (((1UL << GICR_PROPBASER_PA_SIZE) - 1) << GICR_PROPBASER_PA_SHIFT)
	+
	#define GICR_PENDBASER 0x0078
	/*
	* Cacheability
	@@ -225,6 +234,15 @@
	#define GICR_PENDBASER_OUTER_CACHE_MASK \
	(0x7UL << GICR_PENDBASER_OUTER_CACHE_SHIFT)

	+/*
	+ * The LPI Pending Table (PENDBASER) is 64k aligned. So bits 51:16 are defined to be the PA, for 36
	+ * potentially significant bits.
	+ */
	+#define GICR_PENDBASER_PA_SHIFT 16
	+#define GICR_PENDBASER_PA_SIZE 36
	+#define GICR_PENDBASER_PA_MASK \
	+ (((1UL << GICR_PENDBASER_PA_SIZE) - 1) << GICR_PENDBASER_PA_SHIFT)
	+
	#define GICR_INVLPIR 0x00a0
	#define GICR_INVALLR 0x00b0
	#define GICR_SYNCR 0x00c0