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Index: sys/arm/include/pte-v6.h
===================================================================
--- sys/arm/include/pte-v6.h
+++ sys/arm/include/pte-v6.h
@@ -198,6 +198,17 @@
#define PTE2_ATTR_SO TEX2_CLASS_3
#define PTE2_ATTR_WT TEX2_CLASS_4
/*
+ * Workaround for Marvell Armada38X family HW issue
+ * between Cortex-A9 CPUs and on-chip devices that may
+ * cause hang on heavy load.
+ * To avoid that, map all registers including PCIe IO
+ * as strongly ordered instead of device memory.
+ */
+#ifdef SOC_MV_ARMADA38X
+#undef PTE2_ATTR_DEVICE
+#define PTE2_ATTR_DEVICE PTE2_ATTR_SO
+#endif
+/*
* Software defined bits for L1 descriptors
* - L1_AP0 is used as page accessed bit
* - L1_AP2 (RO / not RW) is used as page not modified bit

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