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Index: sys/dev/drm2/i915/i915_dma.c
===================================================================
--- sys/dev/drm2/i915/i915_dma.c
+++ sys/dev/drm2/i915/i915_dma.c
@@ -1483,6 +1483,13 @@
dev_priv->dev = dev;
dev_priv->info = info;
+ mtx_init(&dev_priv->irq_lock, "userirq", NULL, MTX_DEF);
+ mtx_init(&dev_priv->error_lock, "915err", NULL, MTX_DEF);
+ mtx_init(&dev_priv->rps.lock, "915rps", NULL, MTX_DEF);
+ sx_init(&dev_priv->dpio_lock, "915dpi");
+
+ sx_init(&dev_priv->rps.hw_lock, "915rpshw");
+
i915_dump_device_info(dev_priv);
if (i915_get_bridge_dev(dev)) {
@@ -1580,6 +1587,7 @@
intel_detect_pch(dev);
intel_irq_init(dev);
+ intel_gt_sanitize(dev);
intel_gt_init(dev);
/* Try to make sure MCHBAR is enabled before poking at it */
@@ -1605,13 +1613,6 @@
if (!IS_I945G(dev) && !IS_I945GM(dev))
drm_pci_enable_msi(dev);
- mtx_init(&dev_priv->irq_lock, "userirq", NULL, MTX_DEF);
- mtx_init(&dev_priv->error_lock, "915err", NULL, MTX_DEF);
- mtx_init(&dev_priv->rps.lock, "915rps", NULL, MTX_DEF);
- sx_init(&dev_priv->dpio_lock, "915dpi");
-
- sx_init(&dev_priv->rps.hw_lock, "915rpshw");
-
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
dev_priv->num_pipe = 3;
else if (IS_MOBILE(dev) || !IS_GEN2(dev))
Index: sys/dev/drm2/i915/i915_drv.h
===================================================================
--- sys/dev/drm2/i915/i915_drv.h
+++ sys/dev/drm2/i915/i915_drv.h
@@ -1346,7 +1346,7 @@
extern void intel_irq_init(struct drm_device *dev);
extern void intel_gt_init(struct drm_device *dev);
-extern void intel_gt_reset(struct drm_device *dev);
+extern void intel_gt_sanitize(struct drm_device *dev);
void i915_error_state_free(struct drm_i915_error_state *error);
Index: sys/dev/drm2/i915/i915_drv.c
===================================================================
--- sys/dev/drm2/i915/i915_drv.c
+++ sys/dev/drm2/i915/i915_drv.c
@@ -623,7 +623,7 @@
{
int error = 0;
- intel_gt_reset(dev);
+ intel_gt_sanitize(dev);
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
DRM_LOCK(dev);
@@ -652,7 +652,7 @@
pci_set_master(dev->pdev);
#endif
- intel_gt_reset(dev);
+ intel_gt_sanitize(dev);
/*
* Platforms with opregion should have sane BIOS, older ones (gen3 and
Index: sys/dev/drm2/i915/intel_pm.c
===================================================================
--- sys/dev/drm2/i915/intel_pm.c
+++ sys/dev/drm2/i915/intel_pm.c
@@ -4396,7 +4396,7 @@
gen6_gt_check_fifodbg(dev_priv);
}
-void intel_gt_reset(struct drm_device *dev)
+void intel_gt_sanitize(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4407,6 +4407,10 @@
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
__gen6_gt_force_wake_mt_reset(dev_priv);
}
+
+ /* BIOS often leaves RC6 enabled, but disable it for hw init */
+ if (INTEL_INFO(dev)->gen >= 6)
+ intel_disable_gt_powersave(dev);
}
void intel_gt_init(struct drm_device *dev)
@@ -4415,8 +4419,6 @@
mtx_init(&dev_priv->gt_lock, "i915_gt_lock", NULL, MTX_DEF);
- intel_gt_reset(dev);
-
if (IS_VALLEYVIEW(dev)) {
dev_priv->gt.force_wake_get = vlv_force_wake_get;
dev_priv->gt.force_wake_put = vlv_force_wake_put;

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