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Index: sys/arm/allwinner/a10_ehci.c
===================================================================
--- sys/arm/allwinner/a10_ehci.c
+++ sys/arm/allwinner/a10_ehci.c
@@ -88,9 +88,6 @@
static device_attach_t a10_ehci_attach;
static device_detach_t a10_ehci_detach;
-bs_r_1_proto(reversed);
-bs_w_1_proto(reversed);
-
struct aw_ehci_softc {
ehci_softc_t sc;
clk_t clk;
Index: sys/arm/allwinner/a10_gpio.c
===================================================================
--- sys/arm/allwinner/a10_gpio.c
+++ sys/arm/allwinner/a10_gpio.c
@@ -57,6 +57,10 @@
#include <dev/extres/clk/clk.h>
#include <dev/extres/hwreset/hwreset.h>
+#if defined(__aarch64__)
+#include "opt_soc.h"
+#endif
+
#include "gpio_if.h"
#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
@@ -116,6 +120,12 @@
extern const struct allwinner_padconf a83t_r_padconf;
#endif
+/* Defined in a64_padconf.c */
+#ifdef SOC_ALLWINNER_A64
+extern const struct allwinner_padconf a64_padconf;
+extern const struct allwinner_padconf a64_r_padconf;
+#endif
+
static struct ofw_compat_data compat_data[] = {
#ifdef SOC_ALLWINNER_A10
{"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf},
@@ -143,6 +153,10 @@
{"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf},
{"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf},
#endif
+#ifdef SOC_ALLWINNER_A64
+ {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_padconf},
+ {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_padconf},
+#endif
{NULL, 0}
};
Index: sys/arm/allwinner/a10_mmc.h
===================================================================
--- sys/arm/allwinner/a10_mmc.h
+++ sys/arm/allwinner/a10_mmc.h
@@ -196,4 +196,7 @@
uint32_t next;
};
+/* DMA descriptors and data buffers must be aligned to 32-bits */
+#define A10_MMC_DMA_ALIGN 4
+
#endif /* _A10_MMC_H_ */
Index: sys/arm/allwinner/a10_mmc.c
===================================================================
--- sys/arm/allwinner/a10_mmc.c
+++ sys/arm/allwinner/a10_mmc.c
@@ -182,6 +182,7 @@
MTX_DEF);
callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0);
+#if defined(__arm__)
/*
* Later chips use a different FIFO offset. Unfortunately the FDT
* uses the same compatible string for old and new implementations.
@@ -196,6 +197,9 @@
sc->a10_fifo_reg = A31_MMC_FIFO;
break;
}
+#else
+ sc->a10_fifo_reg = A31_MMC_FIFO;
+#endif
/* De-assert reset */
if (hwreset_get_by_ofw_name(dev, "ahb", &sc->a10_rst_ahb) == 0) {
@@ -255,7 +259,7 @@
a10_mmc_pio_mode ? "disabled" : "enabled");
if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
- bus_width = 1;
+ bus_width = 4;
sc->a10_host.f_min = 400000;
sc->a10_host.f_max = 50000000;
@@ -316,7 +320,8 @@
/* Allocate the DMA descriptor memory. */
dma_desc_size = sizeof(struct a10_mmc_dma_desc) * A10_MMC_DMA_SEGS;
- error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev), 1, 0,
+ error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
+ A10_MMC_DMA_ALIGN, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->a10_dma_tag);
if (error)
@@ -334,7 +339,8 @@
return (sc->a10_dma_map_err);
/* Create the DMA map for data transfers. */
- error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev), 1, 0,
+ error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
+ A10_MMC_DMA_ALIGN, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS, A10_MMC_DMA_SEGS,
A10_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
@@ -358,6 +364,10 @@
sc = (struct a10_mmc_softc *)arg;
sc->a10_dma_map_err = err;
+
+ if (err)
+ return;
+
dma_desc = sc->a10_dma_desc;
/* Note nsegs is guaranteed to be zero if err is non-zero. */
for (i = 0; i < nsegs; i++) {
Index: sys/arm/allwinner/a64/a64_padconf.c
===================================================================
--- /dev/null
+++ sys/arm/allwinner/a64/a64_padconf.c
@@ -0,0 +1,160 @@
+/*-
+ * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/types.h>
+
+#include <arm/allwinner/allwinner_pinctrl.h>
+
+#include "opt_soc.h"
+
+#ifdef SOC_ALLWINNER_A64
+
+static const struct allwinner_pins a64_pins[] = {
+ { "PB0", 1, 0, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", NULL, "eint" } },
+ { "PB1", 1, 1, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", "sim", "eint" } },
+ { "PB2", 1, 2, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", "sim", "eint" } },
+ { "PB3", 1, 3, { "gpio_in", "gpio_out", "uart2", "i2s0", "jtag", "sim", "eint" } },
+ { "PB4", 1, 4, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "eint" } },
+ { "PB5", 1, 5, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "eint" } },
+ { "PB6", 1, 6, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "eint" } },
+ { "PB7", 1, 7, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "eint" } },
+ { "PB8", 1, 8, { "gpio_in", "gpio_out", NULL, NULL, "uart0", NULL, "eint" } },
+ { "PB9", 1, 9, { "gpio_in", "gpio_out", NULL, NULL, "uart0", NULL, "eint" } },
+
+ { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
+ { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
+ { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
+ { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
+ { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand" } },
+ { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand" } },
+ { "PC8", 2, 8, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC9", 2, 9, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC10", 2, 10, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC11", 2, 11, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC12", 2, 12, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC13", 2, 13, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC14", 2, 14, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC15", 2, 15, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC16", 2, 16, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+
+ { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd", "uart3", "spi1", "ccir" } },
+ { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd", "uart3", "spi1", "ccir" } },
+ { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } },
+ { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } },
+ { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } },
+ { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } },
+ { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd", NULL, NULL, "ccir" } },
+ { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd", NULL, NULL, "ccir" } },
+ { "PD8", 3, 8, { "gpio_in", "gpio_out", "lcd", NULL, "emac", "ccir" } },
+ { "PD9", 3, 9, { "gpio_in", "gpio_out", "lcd", NULL, "emac", "ccir" } },
+ { "PD10", 3, 10, { "gpio_in", "gpio_out", "lcd", NULL, "emac" } },
+ { "PD11", 3, 11, { "gpio_in", "gpio_out", "lcd", NULL, "emac" } },
+ { "PD12", 3, 12, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD13", 3, 13, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD14", 3, 14, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD15", 3, 15, { "gpio_in", "gpio_out", "lcd", "lvds", "emac", "ccir" } },
+ { "PD16", 3, 16, { "gpio_in", "gpio_out", "lcd", "lvds", "emac", "ccir" } },
+ { "PD17", 3, 17, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD18", 3, 18, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD19", 3, 19, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD20", 3, 20, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD21", 3, 21, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } },
+ { "PD22", 3, 22, { "gpio_in", "gpio_out", "pwm0", NULL, "emac" } },
+ { "PD23", 3, 23, { "gpio_in", "gpio_out", NULL, NULL, "emac" } },
+ { "PD24", 3, 24, { "gpio_in", "gpio_out" } },
+
+ { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE3", 4, 3, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE4", 4, 4, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE5", 4, 5, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE6", 4, 6, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE7", 4, 7, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE8", 4, 8, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE9", 4, 9, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE10", 4, 10, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE11", 4, 11, { "gpio_in", "gpio_out", "csi", NULL, "ts" } },
+ { "PE12", 4, 12, { "gpio_in", "gpio_out", "csi" } },
+ { "PE13", 4, 13, { "gpio_in", "gpio_out", "csi" } },
+ { "PE14", 4, 14, { "gpio_in", "gpio_out", "pll_lock", "twi2" } },
+ { "PE15", 4, 15, { "gpio_in", "gpio_out", NULL, "twi2" } },
+ { "PE16", 4, 16, { "gpio_in", "gpio_out" } },
+ { "PE17", 4, 17, { "gpio_in", "gpio_out" } },
+
+ { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
+ { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
+ { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF6", 5, 6, { "gpio_in", "gpio_out" } },
+
+ { "PG0", 6, 0, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" } },
+ { "PG1", 6, 1, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" } },
+ { "PG2", 6, 2, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" } },
+ { "PG3", 6, 3, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" } },
+ { "PG4", 6, 4, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" } },
+ { "PG5", 6, 5, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" } },
+ { "PG6", 6, 6, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "eint" } },
+ { "PG7", 6, 7, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "eint" } },
+ { "PG8", 6, 8, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "eint" } },
+ { "PG9", 6, 9, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "eint" } },
+ { "PG10", 6, 10, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "eint" } },
+ { "PG11", 6, 11, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "eint" } },
+ { "PG12", 6, 12, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "eint" } },
+ { "PG13", 6, 13, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "eint" } },
+
+ { "PH0", 7, 0, { "gpio_in", "gpio_out", "i2c0", NULL, NULL, NULL, "eint" } },
+ { "PH1", 7, 1, { "gpio_in", "gpio_out", "i2c0", NULL, NULL, NULL, "eint" } },
+ { "PH2", 7, 2, { "gpio_in", "gpio_out", "i2c1", NULL, NULL, NULL, "eint" } },
+ { "PH3", 7, 3, { "gpio_in", "gpio_out", "i2c1", NULL, NULL, NULL, "eint" } },
+ { "PH4", 7, 4, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "eint" } },
+ { "PH5", 7, 5, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "eint" } },
+ { "PH6", 7, 6, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "eint" } },
+ { "PH7", 7, 7, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "eint" } },
+ { "PH8", 7, 8, { "gpio_in", "gpio_out", "owa", NULL, NULL, NULL, "eint" } },
+ { "PH9", 7, 9, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" } },
+ { "PH10", 7, 10, { "gpio_in", "gpio_out", "mic", NULL, NULL, NULL, "eint" } },
+ { "PH11", 7, 11, { "gpio_in", "gpio_out", "mic", NULL, NULL, NULL, "eint" } },
+};
+
+const struct allwinner_padconf a64_padconf = {
+ .npins = nitems(a64_pins),
+ .pins = a64_pins,
+};
+
+#endif /* !SOC_ALLWINNER_A64 */
Index: sys/arm/allwinner/a64/a64_r_padconf.c
===================================================================
--- /dev/null
+++ sys/arm/allwinner/a64/a64_r_padconf.c
@@ -0,0 +1,64 @@
+/*-
+ * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/types.h>
+
+#include <arm/allwinner/allwinner_pinctrl.h>
+
+#include "opt_soc.h"
+
+#ifdef SOC_ALLWINNER_A64
+
+static const struct allwinner_pins a64_r_pins[] = {
+ { "PL0", 0, 0, { "gpio_in", "gpio_out", "s_rsb", "s_i2c", NULL, NULL, "eint" } },
+ { "PL1", 0, 1, { "gpio_in", "gpio_out", "s_rsb", "s_i2c", NULL, NULL, "eint" } },
+ { "PL2", 0, 2, { "gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "eint" } },
+ { "PL3", 0, 3, { "gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "eint" } },
+ { "PL4", 0, 4, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "eint" } },
+ { "PL5", 0, 5, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "eint" } },
+ { "PL6", 0, 6, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "eint" } },
+ { "PL7", 0, 7, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "eint" } },
+ { "PL8", 0, 8, { "gpio_in", "gpio_out", "s_i2c", NULL, NULL, NULL, "eint" } },
+ { "PL9", 0, 9, { "gpio_in", "gpio_out", "s_i2c", NULL, NULL, NULL, "eint" } },
+ { "PL10", 0, 10, { "gpio_in", "gpio_out", "s_pwm", NULL, NULL, NULL, "eint" } },
+ { "PL11", 0, 11, { "gpio_in", "gpio_out", "s_cir", NULL, NULL, NULL, "eint" } },
+ { "PL12", 0, 12, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" } },
+};
+
+const struct allwinner_padconf a64_r_padconf = {
+ .npins = nitems(a64_r_pins),
+ .pins = a64_r_pins,
+};
+
+#endif /* !SOC_ALLWINNER_A64 */
Index: sys/arm/allwinner/a64/files.a64
===================================================================
--- /dev/null
+++ sys/arm/allwinner/a64/files.a64
@@ -0,0 +1,4 @@
+# $FreeBSD$
+
+arm/allwinner/a64/a64_padconf.c standard
+arm/allwinner/a64/a64_r_padconf.c standard
Index: sys/arm/allwinner/aw_ccu.c
===================================================================
--- sys/arm/allwinner/aw_ccu.c
+++ sys/arm/allwinner/aw_ccu.c
@@ -80,6 +80,7 @@
{ "allwinner,sun7i-a20", CLOCK_CCU },
{ "allwinner,sun6i-a31", CLOCK_CCU },
{ "allwinner,sun6i-a31s", CLOCK_CCU },
+ { "allwinner,sun50i-a64", CLOCK_CCU },
{ "allwinner,sun8i-a83t", CLOCK_CCU|CLOCK_PRCM|CLOCK_SYSCTRL },
{ "allwinner,sun8i-h3", CLOCK_CCU },
{ NULL, 0 }
Index: sys/arm/allwinner/aw_nmi.c
===================================================================
--- sys/arm/allwinner/aw_nmi.c
+++ sys/arm/allwinner/aw_nmi.c
@@ -35,6 +35,7 @@
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/proc.h>
+#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/intr.h>
Index: sys/arm/allwinner/aw_rsb.c
===================================================================
--- sys/arm/allwinner/aw_rsb.c
+++ sys/arm/allwinner/aw_rsb.c
@@ -472,6 +472,8 @@
static devclass_t rsb_devclass;
-DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0);
-DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0);
+EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0,
+ BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
+EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0,
+ BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
MODULE_VERSION(rsb, 1);
Index: sys/arm/allwinner/aw_rtc.c
===================================================================
--- sys/arm/allwinner/aw_rtc.c
+++ sys/arm/allwinner/aw_rtc.c
@@ -62,7 +62,11 @@
#define LOSC_MAGIC 0x16aa0000
#define LOSC_BUSY_MASK 0x00000380
+#if defined(__aarch64__)
+#define IS_SUN7I 0
+#else
#define IS_SUN7I (allwinner_soc_family() == ALLWINNERSOC_SUN7I)
+#endif
#define YEAR_MIN (IS_SUN7I ? 1970 : 2010)
#define YEAR_MAX (IS_SUN7I ? 2100 : 2073)
Index: sys/arm/allwinner/aw_usbphy.c
===================================================================
--- sys/arm/allwinner/aw_usbphy.c
+++ sys/arm/allwinner/aw_usbphy.c
@@ -41,6 +41,8 @@
#include <sys/module.h>
#include <sys/gpio.h>
+#include <machine/_inttypes.h>
+
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/gpio/gpiobusvar.h>
@@ -148,7 +150,7 @@
}
static int
-awusbphy_phy_enable(device_t dev, int phy, bool enable)
+awusbphy_phy_enable(device_t dev, intptr_t phy, bool enable)
{
struct awusbphy_softc *sc;
regulator_t reg;
@@ -177,7 +179,8 @@
} else
error = regulator_disable(reg);
if (error != 0) {
- device_printf(dev, "couldn't %s regulator for phy %d\n",
+ device_printf(dev,
+ "couldn't %s regulator for phy %" PRIdPTR "\n",
enable ? "enable" : "disable", phy);
return (error);
}
Index: sys/arm/allwinner/axp81x.c
===================================================================
--- sys/arm/allwinner/axp81x.c
+++ sys/arm/allwinner/axp81x.c
@@ -52,10 +52,17 @@
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
-#include "iicbus_if.h"
+#include <dev/extres/regulator/regulator.h>
+
#include "gpio_if.h"
+#include "iicbus_if.h"
+#include "regdev_if.h"
+
+MALLOC_DEFINE(M_AXP81X_REG, "AXP81x regulator", "AXP81x power regulator");
#define AXP_ICTYPE 0x03
+#define AXP_POWERCTL2 0x12
+#define AXP_POWERCTL2_DC1SW (1 << 7)
#define AXP_POWERBAT 0x32
#define AXP_POWERBAT_SHUTDOWN (1 << 7)
#define AXP_IRQEN1 0x40
@@ -96,6 +103,37 @@
{ -1, 0 }
};
+struct axp81x_regdef {
+ intptr_t id;
+ char *name;
+ char *supply_name;
+ uint8_t enable_reg;
+ uint8_t enable_mask;
+};
+
+enum axp81x_reg_id {
+ AXP81X_REG_ID_DC1SW
+};
+
+static struct axp81x_regdef axp81x_regdefs[] = {
+ {
+ .id = AXP81X_REG_ID_DC1SW,
+ .name = "dc1sw",
+ .enable_reg = AXP_POWERCTL2,
+ .enable_mask = AXP_POWERCTL2_DC1SW,
+ },
+};
+
+struct axp81x_softc;
+
+struct axp81x_reg_sc {
+ struct regnode *regnode;
+ device_t base_dev;
+ struct axp81x_regdef *def;
+ phandle_t xref;
+ struct regnode_std_param *param;
+};
+
struct axp81x_softc {
struct resource *res;
uint16_t addr;
@@ -103,6 +141,10 @@
device_t gpiodev;
struct mtx mtx;
int busy;
+
+ /* Regulators */
+ struct axp81x_reg_sc **regs;
+ int nregs;
};
#define AXP_LOCK(sc) mtx_lock(&(sc)->mtx)
@@ -150,6 +192,56 @@
return (iicbus_transfer(dev, msg, 2));
}
+static int
+axp81x_regnode_init(struct regnode *regnode)
+{
+ return (0);
+}
+
+static int
+axp81x_regnode_enable(struct regnode *regnode, bool enable, int *udelay)
+{
+ struct axp81x_reg_sc *sc;
+ uint8_t val;
+
+ sc = regnode_get_softc(regnode);
+
+ axp81x_read(sc->base_dev, sc->def->enable_reg, &val, 1);
+ if (enable)
+ val |= sc->def->enable_mask;
+ else
+ val &= ~sc->def->enable_mask;
+ axp81x_write(sc->base_dev, sc->def->enable_reg, val);
+
+ *udelay = 0;
+
+ return (0);
+}
+
+static int
+axp81x_regnode_set_voltage(struct regnode *regnode, int min_uvolt,
+ int max_uvolt, int *udelay)
+{
+ return (ENXIO);
+}
+
+static int
+axp81x_regnode_get_voltage(struct regnode *regnode, int *uvolt)
+{
+ return (ENXIO);
+}
+
+static regnode_method_t axp81x_regnode_methods[] = {
+ /* Regulator interface */
+ REGNODEMETHOD(regnode_init, axp81x_regnode_init),
+ REGNODEMETHOD(regnode_enable, axp81x_regnode_enable),
+ REGNODEMETHOD(regnode_set_voltage, axp81x_regnode_set_voltage),
+ REGNODEMETHOD(regnode_get_voltage, axp81x_regnode_get_voltage),
+ REGNODEMETHOD_END
+};
+DEFINE_CLASS_1(axp81x_regnode, axp81x_regnode_class, axp81x_regnode_methods,
+ sizeof(struct axp81x_reg_sc), regnode_class);
+
static void
axp81x_shutdown(void *devp, int howto)
{
@@ -417,6 +509,56 @@
return (ofw_bus_get_node(dev));
}
+static struct axp81x_reg_sc *
+axp81x_reg_attach(device_t dev, phandle_t node,
+ struct axp81x_regdef *def)
+{
+ struct axp81x_reg_sc *reg_sc;
+ struct regnode_init_def initdef;
+ struct regnode *regnode;
+
+ memset(&initdef, 0, sizeof(initdef));
+ regulator_parse_ofw_stdparam(dev, node, &initdef);
+ initdef.id = def->id;
+ initdef.ofw_node = node;
+ regnode = regnode_create(dev, &axp81x_regnode_class, &initdef);
+ if (regnode == NULL) {
+ device_printf(dev, "cannot create regulator\n");
+ return (NULL);
+ }
+
+ reg_sc = regnode_get_softc(regnode);
+ reg_sc->regnode = regnode;
+ reg_sc->base_dev = dev;
+ reg_sc->def = def;
+ reg_sc->xref = OF_xref_from_node(node);
+ reg_sc->param = regnode_get_stdparam(regnode);
+
+ regnode_register(regnode);
+
+ return (reg_sc);
+}
+
+static int
+axp81x_regdev_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells,
+ intptr_t *num)
+{
+ struct axp81x_softc *sc;
+ int i;
+
+ sc = device_get_softc(dev);
+ for (i = 0; i < sc->nregs; i++) {
+ if (sc->regs[i] == NULL)
+ continue;
+ if (sc->regs[i]->xref == xref) {
+ *num = sc->regs[i]->def->id;
+ return (0);
+ }
+ }
+
+ return (ENXIO);
+}
+
static int
axp81x_probe(device_t dev)
{
@@ -435,8 +577,10 @@
axp81x_attach(device_t dev)
{
struct axp81x_softc *sc;
+ struct axp81x_reg_sc *reg;
uint8_t chip_id;
- int error;
+ phandle_t rnode, child;
+ int error, i;
sc = device_get_softc(dev);
@@ -454,6 +598,29 @@
device_printf(dev, "chip ID 0x%02x\n", chip_id);
}
+ sc->nregs = nitems(axp81x_regdefs);
+ sc->regs = malloc(sizeof(struct axp81x_reg_sc *) * sc->nregs,
+ M_AXP81X_REG, M_WAITOK | M_ZERO);
+
+ /* Attach known regulators that exist in the DT */
+ rnode = ofw_bus_find_child(ofw_bus_get_node(dev), "regulators");
+ if (rnode > 0) {
+ for (i = 0; i < sc->nregs; i++) {
+ child = ofw_bus_find_child(rnode,
+ axp81x_regdefs[i].name);
+ if (child == 0)
+ continue;
+ reg = axp81x_reg_attach(dev, child, &axp81x_regdefs[i]);
+ if (reg == NULL) {
+ device_printf(dev,
+ "cannot attach regulator %s\n",
+ axp81x_regdefs[i].name);
+ return (ENXIO);
+ }
+ sc->regs[i] = reg;
+ }
+ }
+
/* Enable IRQ on short power key press */
axp81x_write(dev, AXP_IRQEN1, 0);
axp81x_write(dev, AXP_IRQEN2, 0);
@@ -495,6 +662,9 @@
DEVMETHOD(gpio_pin_toggle, axp81x_gpio_pin_toggle),
DEVMETHOD(gpio_map_gpios, axp81x_gpio_map_gpios),
+ /* Regdev interface */
+ DEVMETHOD(regdev_map, axp81x_regdev_map),
+
/* OFW bus interface */
DEVMETHOD(ofw_bus_get_node, axp81x_get_node),
@@ -511,9 +681,11 @@
extern devclass_t ofwgpiobus_devclass, gpioc_devclass;
extern driver_t ofw_gpiobus_driver, gpioc_driver;
-DRIVER_MODULE(axp81x, iicbus, axp81x_driver, axp81x_devclass, 0, 0);
-DRIVER_MODULE(ofw_gpiobus, axp81x_pmu, ofw_gpiobus_driver,
- ofwgpiobus_devclass, 0, 0);
-DRIVER_MODULE(gpioc, axp81x_pmu, gpioc_driver, gpioc_devclass, 0, 0);
+EARLY_DRIVER_MODULE(axp81x, iicbus, axp81x_driver, axp81x_devclass, 0, 0,
+ BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
+EARLY_DRIVER_MODULE(ofw_gpiobus, axp81x_pmu, ofw_gpiobus_driver,
+ ofwgpiobus_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
+EARLY_DRIVER_MODULE(gpioc, axp81x_pmu, gpioc_driver, gpioc_devclass, 0, 0,
+ BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
MODULE_VERSION(axp81x, 1);
MODULE_DEPEND(axp81x, iicbus, 1, 1, 1);
Index: sys/arm/allwinner/clk/aw_gate.c
===================================================================
--- sys/arm/allwinner/clk/aw_gate.c
+++ sys/arm/allwinner/clk/aw_gate.c
@@ -44,6 +44,7 @@
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/ofw/ofw_subr.h>
+#include <dev/fdt/fdt_common.h>
#include <dev/extres/clk/clk_gate.h>
@@ -89,11 +90,14 @@
(uintptr_t)"Allwinner APB0 Clock Gates" },
{ "allwinner,sun8i-h3-bus-gates-clk",
- (uintptr_t)"Allwinner Bus Clock Gates"},
+ (uintptr_t)"Allwinner Bus Clock Gates" },
{ "allwinner,sun9i-a80-apbs-gates-clk",
(uintptr_t)"Allwinner APBS Clock Gates" },
+ { "allwinner,sunxi-multi-bus-gates-clk",
+ (uintptr_t)"Allwinner Multi Bus Clock Gates" },
+
{ NULL, 0 }
};
@@ -119,6 +123,48 @@
}
static int
+aw_gate_add(device_t dev, struct clkdom *clkdom, phandle_t node,
+ bus_addr_t paddr)
+{
+ const char **names;
+ uint32_t *indices;
+ clk_t clk_parent;
+ int index, nout, error;
+
+ indices = NULL;
+
+ nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
+ if (nout == 0) {
+ device_printf(dev, "no clock outputs found\n");
+ error = ENOENT;
+ goto fail;
+ }
+ if (indices == NULL) {
+ device_printf(dev, "no clock-indices property\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ error = clk_get_by_ofw_node_index(dev, node, 0, &clk_parent);
+ if (error != 0) {
+ device_printf(dev, "cannot parse clock parent\n");
+ return (ENXIO);
+ }
+
+ for (index = 0; index < nout; index++) {
+ error = aw_gate_create(dev, paddr, clkdom,
+ clk_get_name(clk_parent), names[index], indices[index]);
+ if (error)
+ goto fail;
+ }
+
+ return (0);
+
+fail:
+ return (error);
+}
+
+static int
aw_gate_probe(device_t dev)
{
const char *d;
@@ -138,16 +184,11 @@
aw_gate_attach(device_t dev)
{
struct clkdom *clkdom;
- const char **names;
- int index, nout, error;
- uint32_t *indices;
- clk_t clk_parent;
bus_addr_t paddr;
bus_size_t psize;
- phandle_t node;
+ phandle_t node, child;
node = ofw_bus_get_node(dev);
- indices = NULL;
if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
device_printf(dev, "cannot parse 'reg' property\n");
@@ -156,44 +197,21 @@
clkdom = clkdom_create(dev);
- nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
- if (nout == 0) {
- device_printf(dev, "no clock outputs found\n");
- error = ENOENT;
- goto fail;
- }
- if (indices == NULL) {
- device_printf(dev, "no clock-indices property\n");
- error = ENXIO;
- goto fail;
- }
-
- error = clk_get_by_ofw_index(dev, 0, &clk_parent);
- if (error != 0) {
- device_printf(dev, "cannot parse clock parent\n");
- return (ENXIO);
- }
-
- for (index = 0; index < nout; index++) {
- error = aw_gate_create(dev, paddr, clkdom,
- clk_get_name(clk_parent), names[index], indices[index]);
- if (error)
- goto fail;
- }
+ if (fdt_is_compatible(node, "allwinner,sunxi-multi-bus-gates-clk")) {
+ for (child = OF_child(node); child > 0; child = OF_peer(child))
+ aw_gate_add(dev, clkdom, child, paddr);
+ } else
+ aw_gate_add(dev, clkdom, node, paddr);
if (clkdom_finit(clkdom) != 0) {
device_printf(dev, "cannot finalize clkdom initialization\n");
- error = ENXIO;
- goto fail;
+ return (ENXIO);
}
if (bootverbose)
clkdom_dump(clkdom);
return (0);
-
-fail:
- return (error);
}
static device_method_t aw_gate_methods[] = {
Index: sys/arm/allwinner/clk/aw_modclk.c
===================================================================
--- sys/arm/allwinner/clk/aw_modclk.c
+++ sys/arm/allwinner/clk/aw_modclk.c
@@ -160,28 +160,47 @@
int flags, int *stop)
{
struct aw_modclk_sc *sc;
- uint32_t val, m, n, best_m, best_n;
+ uint32_t val, m, n, src, best_m, best_n, best_src;
uint64_t cur_freq;
int64_t best_diff, cur_diff;
+ int error;
sc = clknode_get_softc(clk);
best_n = best_m = 0;
best_diff = (int64_t)*fout;
-
- for (n = 0; n <= CLK_RATIO_N_MAX; n++)
- for (m = 0; m <= CLK_RATIO_M_MAX; m++) {
- cur_freq = fin / (1 << n) / (m + 1);
- cur_diff = (int64_t)*fout - cur_freq;
- if (cur_diff >= 0 && cur_diff < best_diff) {
- best_diff = cur_diff;
- best_m = m;
- best_n = n;
+ best_src = 0;
+
+ for (src = 0; src < CLK_SRC_SEL_MAX; src++) {
+ error = clknode_set_parent_by_idx(clk, src);
+ if (error != 0)
+ continue;
+ error = clknode_get_freq(clknode_get_parent(clk), &fin);
+ if (error != 0)
+ continue;
+
+ for (n = 0; n <= CLK_RATIO_N_MAX; n++)
+ for (m = 0; m <= CLK_RATIO_M_MAX; m++) {
+ cur_freq = fin / (1 << n) / (m + 1);
+ cur_diff = (int64_t)*fout - cur_freq;
+ if (cur_diff >= 0 && cur_diff < best_diff) {
+ best_src = src;
+ best_diff = cur_diff;
+ best_m = m;
+ best_n = n;
+ }
}
- }
+ }
if (best_diff == (int64_t)*fout)
return (ERANGE);
+ error = clknode_set_parent_by_idx(clk, best_src);
+ if (error != 0)
+ return (error);
+ error = clknode_get_freq(clknode_get_parent(clk), &fin);
+ if (error != 0)
+ return (error);
+
DEVICE_LOCK(sc);
MODCLK_READ(sc, &val);
val &= ~(CLK_RATIO_N | CLK_RATIO_M);
Index: sys/arm/allwinner/clk/aw_pll.c
===================================================================
--- sys/arm/allwinner/clk/aw_pll.c
+++ sys/arm/allwinner/clk/aw_pll.c
@@ -142,6 +142,15 @@
#define A31_PLL6_DEFAULT_K 0x1
#define A31_PLL6_TIMEOUT 10
+#define A64_PLLHSIC_LOCK (1 << 28)
+#define A64_PLLHSIC_FRAC_CLK_OUT (1 << 25)
+#define A64_PLLHSIC_PLL_MODE_SEL (1 << 24)
+#define A64_PLLHSIC_PLL_SDM_EN (1 << 20)
+#define A64_PLLHSIC_FACTOR_N (0x7f << 8)
+#define A64_PLLHSIC_FACTOR_N_SHIFT 8
+#define A64_PLLHSIC_PRE_DIV_M (0xf << 0)
+#define A64_PLLHSIC_PRE_DIV_M_SHIFT 0
+
#define A80_PLL4_CLK_OUT_EN (1 << 20)
#define A80_PLL4_PLL_DIV2 (1 << 18)
#define A80_PLL4_PLL_DIV1 (1 << 16)
@@ -172,6 +181,7 @@
AWPLL_A23_PLL1,
AWPLL_A31_PLL1,
AWPLL_A31_PLL6,
+ AWPLL_A64_PLLHSIC,
AWPLL_A80_PLL4,
};
@@ -601,6 +611,7 @@
val &= ~(A31_PLL6_FACTOR_N | A31_PLL6_FACTOR_K | A31_PLL6_BYPASS_EN);
val |= (A31_PLL6_DEFAULT_N << A31_PLL6_FACTOR_N_SHIFT);
val |= (A31_PLL6_DEFAULT_K << A31_PLL6_FACTOR_K_SHIFT);
+ val |= AW_PLL_ENABLE;
CLKDEV_WRITE_4(dev, reg, val);
/* Wait for PLL to become stable */
@@ -613,9 +624,6 @@
CLKDEV_DEVICE_UNLOCK(dev);
- if (retry == 0)
- return (ETIMEDOUT);
-
return (0);
}
@@ -663,6 +671,40 @@
return (0);
}
+static int
+a64_pllhsic_recalc(struct aw_pll_sc *sc, uint64_t *freq)
+{
+ uint32_t val, n, m;
+
+ DEVICE_LOCK(sc);
+ PLL_READ(sc, &val);
+ DEVICE_UNLOCK(sc);
+
+ n = ((val & A64_PLLHSIC_FACTOR_N) >> A64_PLLHSIC_FACTOR_N_SHIFT) + 1;
+ m = ((val & A64_PLLHSIC_PRE_DIV_M) >> A64_PLLHSIC_PRE_DIV_M_SHIFT) + 1;
+
+ *freq = (*freq * n) / m;
+
+ return (0);
+}
+
+static int
+a64_pllhsic_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
+{
+ uint32_t val;
+
+ /*
+ * PLL_HSIC default is 480MHz, just enable it.
+ */
+ CLKDEV_DEVICE_LOCK(dev);
+ CLKDEV_READ_4(dev, reg, &val);
+ val |= AW_PLL_ENABLE;
+ CLKDEV_WRITE_4(dev, reg, val);
+ CLKDEV_DEVICE_UNLOCK(dev);
+
+ return (0);
+}
+
#define PLL(_type, _recalc, _set_freq, _init) \
[(_type)] = { \
.recalc = (_recalc), \
@@ -681,6 +723,7 @@
PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
+ PLL(AWPLL_A64_PLLHSIC, a64_pllhsic_recalc, NULL, a64_pllhsic_init),
};
static struct ofw_compat_data compat_data[] = {
@@ -694,6 +737,7 @@
{ "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
{ "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
{ "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
+ { "allwinner,sun50i-a64-pllhsic-clk", AWPLL_A64_PLLHSIC },
{ NULL, 0 }
};
Index: sys/arm/allwinner/if_awg.c
===================================================================
--- sys/arm/allwinner/if_awg.c
+++ sys/arm/allwinner/if_awg.c
@@ -44,6 +44,7 @@
#include <sys/sockio.h>
#include <sys/module.h>
#include <sys/taskqueue.h>
+#include <sys/gpio.h>
#include <net/bpf.h>
#include <net/if.h>
@@ -67,16 +68,22 @@
#include <dev/extres/regulator/regulator.h>
#include "miibus_if.h"
+#include "gpio_if.h"
-#define RD4(sc, reg) bus_read_4((sc)->res[0], (reg))
-#define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
+#define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
+#define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
#define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
#define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
#define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
#define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
+#if defined(__aarch64__)
+/* XXXJDM align to cacheline to workaround busdma issue */
+#define DESC_ALIGN 64
+#else
#define DESC_ALIGN 4
+#endif
#define TX_DESC_COUNT 256
#define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT)
#define RX_DESC_COUNT 256
@@ -98,6 +105,20 @@
#define PAUSE_TIME_DEFAULT 0x400
#define TX_INTERVAL_DEFAULT 64
+/* syscon EMAC clock register */
+#define EMAC_CLK_RMII_EN (1 << 13)
+#define EMAC_CLK_ETXDC (0x7 << 10)
+#define EMAC_CLK_ETXDC_SHIFT 10
+#define EMAC_CLK_ERXDC (0x1f << 5)
+#define EMAC_CLK_ERXDC_SHIFT 5
+#define EMAC_CLK_PIT (0x1 << 2)
+#define EMAC_CLK_PIT_MII (0 << 2)
+#define EMAC_CLK_PIT_RGMII (1 << 2)
+#define EMAC_CLK_SRC (0x3 << 0)
+#define EMAC_CLK_SRC_MII (0 << 0)
+#define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
+#define EMAC_CLK_SRC_RGMII (2 << 0)
+
/* Burst length of RX and TX DMA transfers */
static int awg_burst_len = BURST_LEN_DEFAULT;
TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
@@ -116,6 +137,7 @@
static struct ofw_compat_data compat_data[] = {
{ "allwinner,sun8i-a83t-emac", 1 },
+ { "allwinner,sun8i-h3-emac", 1 },
{ NULL, 0 }
};
@@ -144,8 +166,15 @@
u_int cur;
};
+enum {
+ _RES_EMAC,
+ _RES_IRQ,
+ _RES_SYSCON,
+ _RES_NITEMS
+};
+
struct awg_softc {
- struct resource *res[2];
+ struct resource *res[_RES_NITEMS];
struct mtx mtx;
if_t ifp;
device_t miibus;
@@ -163,6 +192,7 @@
static struct resource_spec awg_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
+ { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
{ -1, 0 }
};
@@ -909,49 +939,54 @@
}
static int
-awg_setup_extres(device_t dev)
+awg_setup_phy(device_t dev)
{
struct awg_softc *sc;
- hwreset_t rst_ahb;
- clk_t clk_ahb, clk_tx, clk_tx_parent;
- regulator_t reg;
+ clk_t clk_tx, clk_tx_parent;
const char *tx_parent_name;
char *phy_type;
phandle_t node;
- uint64_t freq;
- int error, div;
+ uint32_t reg, tx_delay, rx_delay;
+ int error;
sc = device_get_softc(dev);
node = ofw_bus_get_node(dev);
- rst_ahb = NULL;
- clk_ahb = NULL;
- clk_tx = NULL;
- clk_tx_parent = NULL;
- reg = NULL;
- phy_type = NULL;
- /* Get AHB clock and reset resources */
- error = hwreset_get_by_ofw_name(dev, "ahb", &rst_ahb);
- if (error != 0) {
- device_printf(dev, "cannot get ahb reset\n");
- goto fail;
- }
- error = clk_get_by_ofw_name(dev, "ahb", &clk_ahb);
- if (error != 0) {
- device_printf(dev, "cannot get ahb clock\n");
- goto fail;
- }
-
- /* Configure PHY for MII or RGMII mode */
- if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type)) {
- if (bootverbose)
- device_printf(dev, "PHY type: %s\n", phy_type);
+ if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) == 0)
+ return (0);
+ if (bootverbose)
+ device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
+ sc->res[_RES_SYSCON] != NULL ? "reg" : "clk");
+
+ if (sc->res[_RES_SYSCON] != NULL) {
+ reg = bus_read_4(sc->res[_RES_SYSCON], 0);
+ reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
+ if (strcmp(phy_type, "rgmii") == 0)
+ reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
+ else if (strcmp(phy_type, "rmii") == 0)
+ reg |= EMAC_CLK_RMII_EN;
+ else
+ reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
+
+ if (OF_getencprop(node, "tx-delay", &tx_delay,
+ sizeof(tx_delay)) > 0) {
+ reg &= ~EMAC_CLK_ETXDC;
+ reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
+ }
+ if (OF_getencprop(node, "rx-delay", &rx_delay,
+ sizeof(rx_delay)) > 0) {
+ reg &= ~EMAC_CLK_ERXDC;
+ reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
+ }
+ if (bootverbose)
+ device_printf(dev, "EMAC clock: 0x%08x\n", reg);
+ bus_write_4(sc->res[_RES_SYSCON], 0, reg);
+ } else {
if (strcmp(phy_type, "rgmii") == 0)
tx_parent_name = "emac_int_tx";
else
tx_parent_name = "mii_phy_tx";
- OF_prop_free(phy_type);
/* Get the TX clock */
error = clk_get_by_ofw_name(dev, "tx", &clk_tx);
@@ -983,6 +1018,46 @@
}
}
+ error = 0;
+
+fail:
+ OF_prop_free(phy_type);
+ return (error);
+}
+
+static int
+awg_setup_extres(device_t dev)
+{
+ struct awg_softc *sc;
+ hwreset_t rst_ahb;
+ clk_t clk_ahb;
+ regulator_t reg;
+ phandle_t node;
+ uint64_t freq;
+ int error, div;
+
+ sc = device_get_softc(dev);
+ node = ofw_bus_get_node(dev);
+ rst_ahb = NULL;
+ clk_ahb = NULL;
+ reg = NULL;
+
+ /* Get AHB clock and reset resources */
+ error = hwreset_get_by_ofw_name(dev, "ahb", &rst_ahb);
+ if (error != 0) {
+ device_printf(dev, "cannot get ahb reset\n");
+ goto fail;
+ }
+ error = clk_get_by_ofw_name(dev, "ahb", &clk_ahb);
+ if (error != 0) {
+ device_printf(dev, "cannot get ahb clock\n");
+ goto fail;
+ }
+
+ /* Configure PHY for MII or RGMII mode */
+ if (awg_setup_phy(dev) != 0)
+ goto fail;
+
/* Enable AHB clock */
error = clk_enable(clk_ahb);
if (error != 0) {
@@ -1028,20 +1103,14 @@
}
if (bootverbose)
- device_printf(dev, "AHB frequency %llu Hz, MDC div: 0x%x\n",
- freq, sc->mdc_div_ratio_m);
+ device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
+ (uintmax_t)freq, sc->mdc_div_ratio_m);
return (0);
fail:
- OF_prop_free(phy_type);
-
if (reg != NULL)
regulator_release(reg);
- if (clk_tx_parent != NULL)
- clk_release(clk_tx_parent);
- if (clk_tx != NULL)
- clk_release(clk_tx);
if (clk_ahb != NULL)
clk_release(clk_ahb);
if (rst_ahb != NULL)
@@ -1119,6 +1188,52 @@
}
#endif
+#define GPIO_ACTIVE_LOW 1
+
+static int
+awg_phy_reset(device_t dev)
+{
+ pcell_t gpio_prop[4], delay_prop[3];
+ phandle_t node, gpio_node;
+ device_t gpio;
+ uint32_t pin, flags;
+ uint32_t pin_value;
+
+ node = ofw_bus_get_node(dev);
+ if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
+ sizeof(gpio_prop)) <= 0)
+ return (0);
+
+ if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
+ sizeof(delay_prop)) <= 0)
+ return (ENXIO);
+
+ gpio_node = OF_node_from_xref(gpio_prop[0]);
+ if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
+ return (ENXIO);
+
+ if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
+ gpio_prop + 1, &pin, &flags) != 0)
+ return (ENXIO);
+
+ pin_value = GPIO_PIN_LOW;
+ if (OF_hasprop(node, "allwinner,reset-active-low"))
+ pin_value = GPIO_PIN_HIGH;
+
+ if (flags & GPIO_ACTIVE_LOW)
+ pin_value = !pin_value;
+
+ GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
+ GPIO_PIN_SET(gpio, pin, pin_value);
+ DELAY(delay_prop[0]);
+ GPIO_PIN_SET(gpio, pin, !pin_value);
+ DELAY(delay_prop[1]);
+ GPIO_PIN_SET(gpio, pin, pin_value);
+ DELAY(delay_prop[2]);
+
+ return (0);
+}
+
static int
awg_reset(device_t dev)
{
@@ -1127,6 +1242,12 @@
sc = device_get_softc(dev);
+ /* Reset PHY if necessary */
+ if (awg_phy_reset(dev) != 0) {
+ device_printf(dev, "failed to reset PHY\n");
+ return (ENXIO);
+ }
+
/* Soft reset all registers and logic */
WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
@@ -1354,8 +1475,8 @@
return (error);
/* Install interrupt handler */
- error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
- NULL, awg_intr, sc, &sc->ih);
+ error = bus_setup_intr(dev, sc->res[_RES_IRQ],
+ INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
if (error != 0) {
device_printf(dev, "cannot setup interrupt handler\n");
return (error);
Index: sys/arm/allwinner/if_awgreg.h
===================================================================
--- sys/arm/allwinner/if_awgreg.h
+++ sys/arm/allwinner/if_awgreg.h
@@ -176,6 +176,10 @@
uint32_t addr;
uint32_t next;
+
+#if defined(__aarch64__)
+ uint8_t padding[48]; /* XXXJDM work around busdma issue */
+#endif
} __packed;
#endif /* !__IF_AWGREG_H__ */
Index: sys/arm64/conf/GENERIC
===================================================================
--- sys/arm64/conf/GENERIC
+++ sys/arm64/conf/GENERIC
@@ -86,6 +86,7 @@
options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones
# SoC support
+options SOC_ALLWINNER_A64
options SOC_CAVM_THUNDERX
options SOC_HISI_HI6220
@@ -103,6 +104,7 @@
# Ethernet NICs
device mii
device miibus # MII bus support
+device awg # Allwinner EMAC Gigabit Ethernet
device em # Intel PRO/1000 Gigabit Ethernet Family
device igb # Intel PRO/1000 PCIE Server Gigabit Family
device ix # Intel 10Gb Ethernet Family
@@ -125,16 +127,25 @@
# Serial (COM) ports
device uart # Generic UART driver
device uart_ns8250 # ns8250-type UART driver
+device uart_snps
device pl011
# USB support
options USB_DEBUG # enable debug msgs
device dwcotg # DWC OTG controller
+device ehci # EHCI USB interface (USB 2.0)
device xhci # XHCI PCI->USB interface (USB 3.0)
device usb # USB Bus (required)
device ukbd # Keyboard
device umass # Disks/Mass storage - Requires scbus and da
+# GPIO
+device gpio
+device fdt_pinctrl
+
+# I2C
+device iicbus
+
# Pseudo devices.
device loop # Network loopback
device random # Entropy device
@@ -146,6 +157,13 @@
device firmware # firmware assist module
device psci # Support for ARM PSCI
+# EXT_RESOURCES pseudo devices
+options EXT_RESOURCES
+device clk
+device phy
+device hwreset
+device regulator
+
# The `bpf' device enables the Berkeley Packet Filter.
# Be aware of the administrative consequences of enabling this!
# Note that 'bpf' is required for DHCP.
@@ -159,3 +177,6 @@
# The crypto framework is required by IPSEC
device crypto # Required by IPSEC
+
+#options BOOTVERBOSE=1
+options COMPAT_FREEBSD10
Index: sys/boot/fdt/dts/arm/a64.dtsi
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/a64.dtsi
@@ -0,0 +1,137 @@
+/*-
+ * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/ {
+ clocks {
+ pll_hsic: clk@01c20044 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun50i-a64-pllhsic-clk";
+ reg = <0x01c20044 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll_hsic";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun8i-a83t-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>, <&pll_hsic>;
+ clock-indices = <8>, <9>,
+ <10>, <11>,
+ <16>;
+ clock-output-names = "usb_phy0", "usb_phy1",
+ "usb_hsic_pll", "usb_hsic_12m",
+ "usb_ohci0";
+ };
+ };
+
+ soc {
+ watchdog: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ nmi_intc: interrupt-controller@01f00c0c {
+ compatible = "allwinner,sun6i-a31-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c0c 0x38>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ r_rsb: i2c@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <3000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun8i-a83t-usb-phy";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>,
+ <&usb_clk 11>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "hsic_pll",
+ "hsic_12m";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 24>;
+ resets = <&ahb_rst 24>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 25>;
+ resets = <&ahb_rst 25>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+ };
+};
+
+&mmc0_pins {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+ r_rsb_pins: r_rsb {
+ allwinner,pins = "PL0", "PL1";
+ allwinner,function = "s_rsb";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
Index: sys/boot/fdt/dts/arm/pine64_plus.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/pine64_plus.dts
@@ -0,0 +1,81 @@
+/*-
+ * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include "sun50i-a64-pine64-plus.dts"
+#include "a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+&pio {
+ emac_phy_reset_pin_pine64_plus: emac_phy_reset_pin@0 {
+ allwinner,pins = "PD14";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&emac_phy_reset_pin_pine64_plus>;
+ phy-supply = <&reg_dc1dc>;
+ allwinner,reset-gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>;
+ allwinner,reset-active-low;
+ allwinner,reset-delays-us = <0 10000 30000>;
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp81x: pmic@3a3 {
+ compatible = "x-powers,axp813";
+ reg = <0x3a3>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <1>;
+
+ regulators {
+ reg_dc1dc: dc1sw {
+ regulator-name = "dc1sw";
+ };
+ };
+ };
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
Index: sys/boot/fdt/dts/arm/sun50i-a64-pine64-common.dtsi
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/sun50i-a64-pine64-common.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun50i-a64.dtsi"
+
+/ {
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ cd-gpios = <&pio 5 6 0>;
+ cd-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
Index: sys/boot/fdt/dts/arm/sun50i-a64-pine64-plus.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/sun50i-a64-pine64-plus.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-pine64-common.dtsi"
+
+/ {
+ model = "Pine64+";
+ compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
Index: sys/boot/fdt/dts/arm/sun50i-a64-pine64.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/sun50i-a64-pine64.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-pine64-common.dtsi"
+
+/ {
+ model = "Pine64";
+ compatible = "pine64,pine64", "allwinner,sun50i-a64";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x20000000>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
Index: sys/boot/fdt/dts/arm/sun50i-a64.dtsi
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/sun50i-a64.dtsi
@@ -0,0 +1,659 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0>;
+ };
+
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ cpux: clk@1c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "cpux";
+ };
+
+ periph0: clk@1c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "periph0", "periph0x2";
+ };
+
+ periph0d2: periph0d2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&periph0 0>;
+ clock-output-names = "periph0d2";
+ };
+
+ periph1: clk@1c2002c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c2002c 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "periph1", "periph1x2";
+ };
+
+ cpu: cpu_clk@1c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&cpux>, <&cpux>;
+ clock-output-names = "cpu";
+ critical-clocks = <0>;
+ };
+
+ axi: axi_clk@1c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1_clk@1c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&periph0 0>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb2: ahb2_clk@1c2005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&ahb1>, <&periph0d2>;
+ clock-output-names = "ahb2";
+ };
+
+ apb1: apb1_clk@1c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb2: apb2_clk@1c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>,
+ <&periph0 1>, <&periph0 1>;
+ clock-output-names = "apb2";
+ };
+
+ bus_gates: bus_gates_clk@1c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun50i-a64-bus-gates-clk",
+ "allwinner,sunxi-multi-bus-gates-clk";
+ reg = <0x01c20060 0x14>;
+ ahb1_parent {
+ clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>,
+ <9>, <10>,
+ <13>, <14>,
+ <18>, <19>,
+ <20>, <21>,
+ <23>, <24>,
+ <25>, <28>,
+ <32>, <35>,
+ <36>, <37>,
+ <40>, <43>,
+ <44>, <52>,
+ <53>, <54>,
+ <135>;
+ clock-output-names = "bus_mipidsi", "bus_ce",
+ "bus_dma", "bus_mmc0",
+ "bus_mmc1", "bus_mmc2",
+ "bus_nand", "bus_sdram",
+ "bus_ts", "bus_hstimer",
+ "bus_spi0", "bus_spi1",
+ "bus_otg", "bus_otg_ehci0",
+ "bus_ehci0", "bus_otg_ohci0",
+ "bus_ve", "bus_lcd0",
+ "bus_lcd1", "bus_deint",
+ "bus_csi", "bus_hdmi",
+ "bus_de", "bus_gpu",
+ "bus_msgbox", "bus_spinlock",
+ "bus_dbg";
+ };
+ ahb2_parent {
+ clocks = <&ahb2>;
+ clock-indices = <17>, <29>;
+ clock-output-names = "bus_gmac", "bus_ohci0";
+ };
+ apb1_parent {
+ clocks = <&apb1>;
+ clock-indices = <64>, <65>,
+ <69>, <72>,
+ <76>, <77>,
+ <78>;
+ clock-output-names = "bus_codec", "bus_spdif",
+ "bus_pio", "bus_ths",
+ "bus_i2s0", "bus_i2s1",
+ "bus_i2s2";
+ };
+ abp2_parent {
+ clocks = <&apb2>;
+ clock-indices = <96>, <97>,
+ <98>, <101>,
+ <112>, <113>,
+ <114>, <115>,
+ <116>;
+ clock-output-names = "bus_i2c0", "bus_i2c1",
+ "bus_i2c2", "bus_scr",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_uart4";
+ };
+ };
+
+ mmc0_clk: mmc0_clk@1c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&periph0 1>, <&periph1 1>;
+ clock-output-names = "mmc0";
+ };
+
+ mmc1_clk: mmc1_clk@1c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&periph0 1>, <&periph1 1>;
+ clock-output-names = "mmc1";
+ };
+
+ mmc2_clk: mmc2_clk@1c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&periph0 1>, <&periph1 1>;
+ clock-output-names = "mmc2";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&bus_gates 8>, <&mmc0_clk>,
+ <&mmc0_clk>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc",
+ "output", "sample";
+ resets = <&ahb_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&bus_gates 9>, <&mmc1_clk>,
+ <&mmc1_clk>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc",
+ "output", "sample";
+ resets = <&ahb_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&bus_gates 10>, <&mmc2_clk>,
+ <&mmc2_clk>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc",
+ "output", "sample";
+ resets = <&ahb_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,sun50i-a64-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 69>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB8", "PB9";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_b: uart0@1 {
+ allwinner,pins = "PF2", "PF3";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_2pins: uart1_2@0 {
+ allwinner,pins = "PG6", "PG7";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_4pins: uart1_4@0 {
+ allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_2pins: uart2_2@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_4pins: uart2_4@0 {
+ allwinner,pins = "PB0", "PB1", "PB2", "PB3";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_a: uart3@0 {
+ allwinner,pins = "PD0", "PD1";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_2pins_b: uart3_2@1 {
+ allwinner,pins = "PH4", "PH5";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_4pins_b: uart3_4@1 {
+ allwinner,pins = "PH4", "PH5", "PH6", "PH7";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_2pins: uart4_2@0 {
+ allwinner,pins = "PD2", "PD3";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_4pins: uart4_4@0 {
+ allwinner,pins = "PD2", "PD3", "PD4", "PD5";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins: mmc0@0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_default_cd_pin: mmc0_cd_pin@0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_pins: mmc1@0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins: mmc2@0 {
+ allwinner,pins = "PC1", "PC5", "PC6", "PC8",
+ "PC9", "PC10";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c0_pins: i2c0_pins {
+ allwinner,pins = "PH0", "PH1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins: i2c1_pins {
+ allwinner,pins = "PH2", "PH3";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins: i2c2_pins {
+ allwinner,pins = "PE14", "PE15";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ rmii_pins: rmii_pins {
+ allwinner,pins = "PD10", "PD11", "PD13", "PD14",
+ "PD17", "PD18", "PD19", "PD20",
+ "PD22", "PD23";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ rgmii_pins: rgmii_pins {
+ allwinner,pins = "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ ahb_rst: reset@1c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@1c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@1c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ uart0: serial@1c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 112>;
+ resets = <&apb2_rst 16>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 113>;
+ resets = <&apb2_rst 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 114>;
+ resets = <&apb2_rst 18>;
+ status = "disabled";
+ };
+
+ uart3: serial@1c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 115>;
+ resets = <&apb2_rst 19>;
+ status = "disabled";
+ };
+
+ uart4: serial@1c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 116>;
+ resets = <&apb2_rst 20>;
+ status = "disabled";
+ };
+
+ rtc: rtc@1f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ i2c0: i2c@1c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 96>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@1c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 97>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@1c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 98>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun50i-a64-emac",
+ "allwinner,sun8i-h3-emac";
+ reg = <0x01c30000 0x100>, <0x01c00030 0x4>;
+ reg-names = "emac", "syscon";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ahb_rst 17>;
+ reset-names = "ahb";
+ clocks = <&bus_gates 17>;
+ clock-names = "ahb";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
Index: sys/conf/files.arm64
===================================================================
--- sys/conf/files.arm64
+++ sys/conf/files.arm64
@@ -1,4 +1,28 @@
# $FreeBSD$
+arm/allwinner/a10_ehci.c optional ehci soc_allwinner_a64
+arm/allwinner/a10_gpio.c optional gpio soc_allwinner_a64
+arm/allwinner/a10_mmc.c optional mmc soc_allwinner_a64
+arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64
+arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64
+arm/allwinner/aw_ccu.c optional soc_allwinner_a64
+arm/allwinner/aw_nmi.c optional soc_allwinner_a64 \
+ compile-with "${NORMAL_C} -I$S/gnu/dts/include"
+arm/allwinner/aw_reset.c optional soc_allwinner_a64
+arm/allwinner/aw_rsb.c optional soc_allwinner_a64
+arm/allwinner/aw_rtc.c optional soc_allwinner_a64
+arm/allwinner/aw_usbphy.c optional ehci soc_allwinner_a64
+arm/allwinner/aw_wdog.c optional soc_allwinner_a64
+arm/allwinner/axp81x.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_ahbclk.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_apbclk.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_axiclk.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_cpuclk.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_gate.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_modclk.c optional soc_allwinner_a64
+arm/allwinner/clk/aw_pll.c optional soc_allwinner_a64 \
+ compile-with "${NORMAL_C} -I$S/gnu/dts/include"
+arm/allwinner/clk/aw_usbclk.c optional soc_allwinner_a64
+arm/allwinner/if_awg.c optional awg
arm/arm/generic_timer.c standard
arm/arm/gic.c optional intrng
arm/arm/pmu.c standard
@@ -68,6 +92,7 @@
dev/psci/psci_arm64.S optional psci
dev/uart/uart_cpu_fdt.c optional uart fdt
dev/uart/uart_dev_pl011.c optional uart pl011
+dev/uart/uart_dev_snps.c optional uart uart_snps
dev/usb/controller/dwc_otg_hisi.c optional dwcotg soc_hisi_hi6220
dev/usb/controller/generic_ohci.c optional ohci fdt
dev/usb/controller/generic_usb_if.m optional ohci fdt
Index: sys/conf/options.arm64
===================================================================
--- sys/conf/options.arm64
+++ sys/conf/options.arm64
@@ -8,5 +8,6 @@
VFP opt_global.h
# SoC Support
+SOC_ALLWINNER_A64 opt_soc.h
SOC_CAVM_THUNDERX opt_soc.h
SOC_HISI_HI6220 opt_soc.h

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