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Index: sys/x86/include/specialreg.h
===================================================================
--- sys/x86/include/specialreg.h
+++ sys/x86/include/specialreg.h
@@ -307,6 +307,15 @@
#define CPUID_EXTSTATE_XINUSE 0x00000004
#define CPUID_EXTSTATE_XSAVES 0x00000008
+/*
+ * AMD extended function 8000_0007h ebx info
+ */
+#define AMDRAS_MCA_OF_RECOV 0x00000001
+#define AMDRAS_SUCCOR 0x00000002
+#define AMDRAS_HW_ASSERT 0x00000004
+#define AMDRAS_SCALABLE_MCA 0x00000008
+#define AMDRAS_PFEH_SUPPORT 0x00000010
+
/*
* AMD extended function 8000_0007h edx info
*/
@@ -709,6 +718,7 @@
#define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */
#define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */
#define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */
+#define MC_MISC_AMDNB_INTP 0x1000000000000000 /* Int. type can generate interrupts */
#define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
#define MC_MISC_AMDNB_LVT_SHIFT 52
#define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */
Index: sys/x86/include/x86_var.h
===================================================================
--- sys/x86/include/x86_var.h
+++ sys/x86/include/x86_var.h
@@ -44,6 +44,7 @@
extern u_int cpu_feature2;
extern u_int amd_feature;
extern u_int amd_feature2;
+extern u_int amd_rascap;
extern u_int amd_pminfo;
extern u_int via_feature_rng;
extern u_int via_feature_xcrypt;
Index: sys/x86/x86/identcpu.c
===================================================================
--- sys/x86/x86/identcpu.c
+++ sys/x86/x86/identcpu.c
@@ -91,6 +91,7 @@
u_int cpu_feature2; /* Feature flags */
u_int amd_feature; /* AMD feature flags */
u_int amd_feature2; /* AMD feature flags */
+u_int amd_rascap; /* AMD RAS capabilities */
u_int amd_pminfo; /* AMD advanced power management info */
u_int via_feature_rng; /* VIA RNG features */
u_int via_feature_xcrypt; /* VIA ACE features */
@@ -1461,6 +1462,7 @@
}
if (cpu_exthigh >= 0x80000007) {
do_cpuid(0x80000007, regs);
+ amd_rascap = regs[1];
amd_pminfo = regs[3];
}
if (cpu_exthigh >= 0x80000008) {
Index: sys/x86/x86/mca.c
===================================================================
--- sys/x86/x86/mca.c
+++ sys/x86/x86/mca.c
@@ -132,8 +132,20 @@
static inline bool
amd_thresholding_supported(void)
{
- return (cpu_vendor_id == CPU_VENDOR_AMD &&
- CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16);
+ if (cpu_vendor_id != CPU_VENDOR_AMD)
+ return (false);
+ /*
+ * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F).
+ *
+ * It begins to be documented in family 0x15 model 30 and family 0x16,
+ * but neither of these families documents the ScalableMca bit, which
+ * supposedly defines the presence of this feature on family 0x17.
+ */
+ if (CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16)
+ return (true);
+ if (CPUID_TO_FAMILY(cpu_id) >= 0x17)
+ return ((amd_rascap & AMDRAS_SCALABLE_MCA) != 0);
+ return (false);
}
#endif

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