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	Index: sys/dev/ixgbe/if_ix.c
	===================================================================
	--- sys/dev/ixgbe/if_ix.c
	+++ sys/dev/ixgbe/if_ix.c
	@@ -47,7 +47,7 @@
	/************************************************************************
	* Driver version
	************************************************************************/
	-char ixgbe_driver_version[] = "4.0.0-k";
	+char ixgbe_driver_version[] = "4.0.1-k";


	/************************************************************************
	@@ -92,6 +92,7 @@
	PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	+ PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
	Index: sys/dev/ixgbe/if_ixv.c
	===================================================================
	--- sys/dev/ixgbe/if_ixv.c
	+++ sys/dev/ixgbe/if_ixv.c
	@@ -45,7 +45,7 @@
	/************************************************************************
	* Driver version
	************************************************************************/
	-char ixv_driver_version[] = "2.0.0-k";
	+char ixv_driver_version[] = "2.0.1-k";

	/************************************************************************
	* PCI Device ID Table
	@@ -616,6 +616,7 @@

	/* Reset VF and renegotiate mailbox API version */
	hw->mac.ops.reset_hw(hw);
	+ hw->mac.ops.start_hw(hw);
	error = ixv_negotiate_api(adapter);
	if (error) {
	device_printf(dev,
	@@ -909,10 +910,18 @@
	{
	struct adapter *adapter = iflib_get_softc(ctx);
	device_t dev = iflib_get_dev(ctx);
	+ s32 status;

	adapter->hw.mac.get_link_status = TRUE;
	- ixgbe_check_link(&adapter->hw, &adapter->link_speed, &adapter->link_up,
	- FALSE);
	+
	+ status = ixgbe_check_link(&adapter->hw, &adapter->link_speed,
	+ &adapter->link_up, FALSE);
	+
	+ if (status != IXGBE_SUCCESS && adapter->hw.adapter_stopped == FALSE) {
	+ /* Mailbox's Clear To Send status is lost or timeout occurred.
	+ * We need reinitialization. */
	+ iflib_get_ifp(ctx)->if_init(ctx);
	+ }

	if (adapter->link_up) {
	if (adapter->link_active == FALSE) {
	Index: sys/dev/ixgbe/ixgbe_82598.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_82598.c
	+++ sys/dev/ixgbe/ixgbe_82598.c
	@@ -550,6 +550,7 @@
	/**
	* ixgbe_start_mac_link_82598 - Configures MAC link settings
	* @hw: pointer to hardware structure
	+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
	*
	* Configures link settings based on values in the ixgbe_hw struct.
	* Restarts the link. Performs autonegotiation if needed.
	@@ -1207,7 +1208,7 @@
	* ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset at address 0xA2
	- * @eeprom_data: value read
	+ * @sff8472_data: value read
	*
	* Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
	**/
	Index: sys/dev/ixgbe/ixgbe_82599.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_82599.c
	+++ sys/dev/ixgbe/ixgbe_82599.c
	@@ -270,7 +270,7 @@
	/**
	* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
	* @hw: pointer to hardware structure
	- * @reg_val: value to write to AUTOC
	+ * @autoc: value to write to AUTOC
	* @locked: bool to indicate whether the SW/FW lock was already taken by
	* previous proc_autoc_read_82599.
	*
	@@ -1373,6 +1373,7 @@
	s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
	bool cloud_mode)
	{
	+ UNREFERENCED_1PARAMETER(cloud_mode);
	DEBUGFUNC("ixgbe_init_fdir_perfect_82599");

	/*
	@@ -1461,7 +1462,8 @@

	/**
	* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
	- * @stream: input bitstream to compute the hash on
	+ * @input: input bitstream to compute the hash on
	+ * @common: compressed common input dword
	*
	* This function is almost identical to the function above but contains
	* several optimizations such as unwinding all of the loops, letting the
	@@ -1600,7 +1602,7 @@

	/**
	* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
	- * @atr_input: input bitstream to compute the hash on
	+ * @input: input bitstream to compute the hash on
	* @input_mask: mask for the input bitstream
	*
	* This function serves two main purposes. First it applies the input_mask
	@@ -1701,6 +1703,7 @@
	u32 fdirm = IXGBE_FDIRM_DIPv6;
	u32 fdirtcpm;
	u32 fdirip6m;
	+ UNREFERENCED_1PARAMETER(cloud_mode);
	DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");

	/*
	@@ -1877,6 +1880,7 @@
	u32 addr_low, addr_high;
	u32 cloud_type = 0;
	s32 err;
	+ UNREFERENCED_1PARAMETER(cloud_mode);

	DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
	if (!cloud_mode) {
	@@ -2001,6 +2005,7 @@
	* @input_mask: mask for the input bitstream
	* @soft_id: software index for the filters
	* @queue: queue index to direct traffic to
	+ * @cloud_mode: unused
	*
	* Note that the caller to this function must lock before calling, since the
	* hardware writes must be protected from one another.
	@@ -2011,6 +2016,7 @@
	u16 soft_id, u8 queue, bool cloud_mode)
	{
	s32 err = IXGBE_ERR_CONFIG;
	+ UNREFERENCED_1PARAMETER(cloud_mode);

	DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");

	@@ -2520,6 +2526,7 @@
	* ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to read
	+ * @dev_addr: address to read from
	* @data: value read
	*
	* Performs byte read operation to SFP module's EEPROM over I2C interface at
	@@ -2577,6 +2584,7 @@
	* ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to write
	+ * @dev_addr: address to read from
	* @data: value to write
	*
	* Performs byte write operation to SFP module's EEPROM over I2C interface at
	Index: sys/dev/ixgbe/ixgbe_api.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_api.c
	+++ sys/dev/ixgbe/ixgbe_api.c
	@@ -521,6 +521,7 @@
	* ixgbe_read_phy_reg - Read PHY register
	* @hw: pointer to hardware structure
	* @reg_addr: 32 bit address of PHY register to read
	+ * @device_type: type of device you want to communicate with
	* @phy_data: Pointer to read data from PHY register
	*
	* Reads a value from a specified PHY register
	@@ -539,6 +540,7 @@
	* ixgbe_write_phy_reg - Write PHY register
	* @hw: pointer to hardware structure
	* @reg_addr: 32 bit PHY register to write
	+ * @device_type: type of device you want to communicate with
	* @phy_data: Data to write to the PHY register
	*
	* Writes a value to specified PHY register
	@@ -582,6 +584,8 @@
	/**
	* ixgbe_check_phy_link - Determine link and speed status
	* @hw: pointer to hardware structure
	+ * @speed: link speed
	+ * @link_up: TRUE when link is up
	*
	* Reads a PHY register to determine if link is up and the current speed for
	* the PHY.
	@@ -597,6 +601,7 @@
	* ixgbe_setup_phy_link_speed - Set auto advertise
	* @hw: pointer to hardware structure
	* @speed: new link speed
	+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
	*
	* Sets the auto advertised capabilities
	**/
	@@ -622,6 +627,9 @@
	/**
	* ixgbe_check_link - Get link and speed status
	* @hw: pointer to hardware structure
	+ * @speed: pointer to link speed
	+ * @link_up: TRUE when link is up
	+ * @link_up_wait_to_complete: bool used to wait for link up or not
	*
	* Reads the links register to determine if link is up and the current speed
	**/
	@@ -675,6 +683,7 @@
	* ixgbe_setup_link - Set link speed
	* @hw: pointer to hardware structure
	* @speed: new link speed
	+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
	*
	* Configures link settings. Restarts the link.
	* Performs autonegotiation if needed.
	@@ -691,6 +700,7 @@
	* ixgbe_setup_mac_link - Set link speed
	* @hw: pointer to hardware structure
	* @speed: new link speed
	+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
	*
	* Configures link settings. Restarts the link.
	* Performs autonegotiation if needed.
	@@ -706,6 +716,8 @@
	/**
	* ixgbe_get_link_capabilities - Returns link capabilities
	* @hw: pointer to hardware structure
	+ * @speed: link speed capabilities
	+ * @autoneg: TRUE when autoneg or autotry is enabled
	*
	* Determines the link capabilities of the current configuration.
	**/
	@@ -758,6 +770,7 @@
	/**
	* ixgbe_blink_led_stop - Stop blinking LEDs
	* @hw: pointer to hardware structure
	+ * @index: led number to stop
	*
	* Stop blinking LED based on index.
	**/
	@@ -1000,6 +1013,7 @@
	* @mc_addr_list: the list of new multicast addresses
	* @mc_addr_count: number of addresses
	* @func: iterator function to walk the multicast address list
	+ * @clear: flag, when set clears the table beforehand
	*
	* The given list replaces any existing list. Clears the MC addrs from receive
	* address registers and the multicast table. Uses unused receive address
	@@ -1190,7 +1204,7 @@
	/**
	* ixgbe_set_source_address_pruning - Enable/Disable source address pruning
	* @hw: pointer to hardware structure
	- * @enbale: enable or disable source address pruning
	+ * @enable: enable or disable source address pruning
	* @pool: Rx pool - Rx pool to toggle source address pruning
	**/
	void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
	Index: sys/dev/ixgbe/ixgbe_common.h
	===================================================================
	--- sys/dev/ixgbe/ixgbe_common.h
	+++ sys/dev/ixgbe/ixgbe_common.h
	@@ -180,6 +180,12 @@
	bool ixgbe_mng_present(struct ixgbe_hw *hw);
	bool ixgbe_mng_enabled(struct ixgbe_hw *hw);

	+
	+void ixgbe_get_etk_id(struct ixgbe_hw hw, struct ixgbe_nvm_version nvm_ver);
	+void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
	+ struct ixgbe_nvm_version *nvm_ver);
	+void ixgbe_get_orom_version(struct ixgbe_hw *hw,
	+ struct ixgbe_nvm_version *nvm_ver);
	void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
	void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
	s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
	Index: sys/dev/ixgbe/ixgbe_common.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_common.c
	+++ sys/dev/ixgbe/ixgbe_common.c
	@@ -2099,6 +2099,7 @@
	/**
	* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
	* @hw: pointer to hardware structure
	+ * @count: number of bits to shift
	**/
	static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
	{
	@@ -2157,7 +2158,7 @@
	/**
	* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
	* @hw: pointer to hardware structure
	- * @eecd: EECD's current value
	+ * @eec: EEC's current value
	**/
	static void ixgbe_lower_eeprom_clk(struct ixgbe_hw hw, u32 eec)
	{
	@@ -2537,6 +2538,7 @@
	* ixgbe_add_uc_addr - Adds a secondary unicast address.
	* @hw: pointer to hardware structure
	* @addr: new address
	+ * @vmdq: VMDq "set" or "pool" index
	*
	* Adds it to unused receive address register or goes into promiscuous mode.
	**/
	@@ -2681,7 +2683,7 @@
	/**
	* ixgbe_set_mta - Set bit-vector in multicast table
	* @hw: pointer to hardware structure
	- * @hash_value: Multicast address hash value
	+ * @mc_addr: Multicast address
	*
	* Sets the bit-vector in the multicast table.
	**/
	@@ -3385,6 +3387,7 @@
	/**
	* prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
	* @hw: pointer to hardware structure
	+ * @locked: bool to indicate whether the SW/FW lock was taken
	* @reg_val: Value we read from AUTOC
	*
	* The default case requires no protection so just to the register read.
	@@ -3911,6 +3914,9 @@
	* ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
	* @hw: pointer to hardware structure
	* @vlan: VLAN id to write to VLAN filter
	+ * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if
	+ * vlanid not found
	+ *
	*
	* return the VLVF index where this VLAN id should be placed
	*
	@@ -4253,9 +4259,8 @@
	case IXGBE_LINKS_SPEED_10_X550EM_A:
	*speed = IXGBE_LINK_SPEED_UNKNOWN;
	if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T \|\|
	- hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
	+ hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
	*speed = IXGBE_LINK_SPEED_10_FULL;
	- }
	break;
	default:
	*speed = IXGBE_LINK_SPEED_UNKNOWN;
	@@ -4583,10 +4588,11 @@
	u32 length, u32 timeout, bool return_data)
	{
	u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
	- u16 dword_len;
	+ struct ixgbe_hic_hdr resp = (struct ixgbe_hic_hdr )buffer;
	u16 buf_len;
	s32 status;
	u32 bi;
	+ u32 dword_len;

	DEBUGFUNC("ixgbe_host_interface_command");

	@@ -4616,8 +4622,23 @@
	IXGBE_LE32_TO_CPUS(&buffer[bi]);
	}

	- /* If there is any thing in data position pull it in */
	- buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
	+ /*
	+ * If there is any thing in data position pull it in
	+ * Read Flash command requires reading buffer length from
	+ * two byes instead of one byte
	+ */
	+ if (resp->cmd == 0x30) {
	+ for (; bi < dword_len + 2; bi++) {
	+ buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
	+ bi);
	+ IXGBE_LE32_TO_CPUS(&buffer[bi]);
	+ }
	+ buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
	+ & 0xF00) \| resp->buf_len;
	+ hdr_size += (2 << 2);
	+ } else {
	+ buf_len = resp->buf_len;
	+ }
	if (!buf_len)
	goto rel_out;

	@@ -4649,6 +4670,8 @@
	* @min: driver version minor number
	* @build: driver version build number
	* @sub: driver version sub build number
	+ * @len: unused
	+ * @driver_ver: unused
	*
	* Sends driver version number to firmware through the manageability
	* block. On success return IXGBE_SUCCESS
	@@ -4675,10 +4698,10 @@
	fw_cmd.ver_build = build;
	fw_cmd.ver_sub = sub;
	fw_cmd.hdr.checksum = 0;
	- fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
	- (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
	fw_cmd.pad = 0;
	fw_cmd.pad2 = 0;
	+ fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
	+ (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));

	for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
	ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
	@@ -5067,6 +5090,117 @@
	return IXGBE_SUCCESS;
	}

	+/**
	+ * ixgbe_get_orom_version - Return option ROM from EEPROM
	+ *
	+ * @hw: pointer to hardware structure
	+ * @nvm_ver: pointer to output structure
	+ *
	+ * if valid option ROM version, nvm_ver->or_valid set to TRUE
	+ * else nvm_ver->or_valid is FALSE.
	+ **/
	+void ixgbe_get_orom_version(struct ixgbe_hw *hw,
	+ struct ixgbe_nvm_version *nvm_ver)
	+{
	+ u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
	+
	+ nvm_ver->or_valid = FALSE;
	+ /* Option Rom may or may not be present. Start with pointer */
	+ hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
	+
	+ /* make sure offset is valid */
	+ if ((offset == 0x0) \|\| (offset == NVM_INVALID_PTR))
	+ return;
	+
	+ hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
	+ hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
	+
	+ /* option rom exists and is valid */
	+ if ((eeprom_cfg_blkl \| eeprom_cfg_blkh) == 0x0 \|\|
	+ eeprom_cfg_blkl == NVM_VER_INVALID \|\|
	+ eeprom_cfg_blkh == NVM_VER_INVALID)
	+ return;
	+
	+ nvm_ver->or_valid = TRUE;
	+ nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
	+ nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) \|
	+ (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
	+ nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
	+}
	+
	+/**
	+ * ixgbe_get_oem_prod_version - Return OEM Product version
	+ *
	+ * @hw: pointer to hardware structure
	+ * @nvm_ver: pointer to output structure
	+ *
	+ * if valid OEM product version, nvm_ver->oem_valid set to TRUE
	+ * else nvm_ver->oem_valid is FALSE.
	+ **/
	+void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
	+ struct ixgbe_nvm_version *nvm_ver)
	+{
	+ u16 rel_num, prod_ver, mod_len, cap, offset;
	+
	+ nvm_ver->oem_valid = FALSE;
	+ hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
	+
	+ /* Return is offset to OEM Product Version block is invalid */
	+ if (offset == 0x0 && offset == NVM_INVALID_PTR)
	+ return;
	+
	+ /* Read product version block */
	+ hw->eeprom.ops.read(hw, offset, &mod_len);
	+ hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
	+
	+ /* Return if OEM product version block is invalid */
	+ if (mod_len != NVM_OEM_PROD_VER_MOD_LEN \|\|
	+ (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
	+ return;
	+
	+ hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
	+ hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
	+
	+ /* Return if version is invalid */
	+ if ((rel_num \| prod_ver) == 0x0 \|\|
	+ rel_num == NVM_VER_INVALID \|\| prod_ver == NVM_VER_INVALID)
	+ return;
	+
	+ nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
	+ nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
	+ nvm_ver->oem_release = rel_num;
	+ nvm_ver->oem_valid = TRUE;
	+}
	+
	+/**
	+ * ixgbe_get_etk_id - Return Etrack ID from EEPROM
	+ *
	+ * @hw: pointer to hardware structure
	+ * @nvm_ver: pointer to output structure
	+ *
	+ * word read errors will return 0xFFFF
	+ **/
	+void ixgbe_get_etk_id(struct ixgbe_hw hw, struct ixgbe_nvm_version nvm_ver)
	+{
	+ u16 etk_id_l, etk_id_h;
	+
	+ if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
	+ etk_id_l = NVM_VER_INVALID;
	+ if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
	+ etk_id_h = NVM_VER_INVALID;
	+
	+ /* The word order for the version format is determined by high order
	+ * word bit 15.
	+ */
	+ if ((etk_id_h & NVM_ETK_VALID) == 0) {
	+ nvm_ver->etk_id = etk_id_h;
	+ nvm_ver->etk_id \|= (etk_id_l << NVM_ETK_SHIFT);
	+ } else {
	+ nvm_ver->etk_id = etk_id_l;
	+ nvm_ver->etk_id \|= (etk_id_h << NVM_ETK_SHIFT);
	+ }
	+}
	+

	/**
	* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
	@@ -5138,8 +5272,8 @@
	return FALSE;

	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
	- fwsm &= IXGBE_FWSM_MODE_MASK;
	- return fwsm == IXGBE_FWSM_FW_MODE_PT;
	+
	+ return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
	}

	/**
	Index: sys/dev/ixgbe/ixgbe_dcb.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_dcb.c
	+++ sys/dev/ixgbe/ixgbe_dcb.c
	@@ -45,6 +45,10 @@
	* are the smallest unit programmable into the underlying
	* hardware. The IEEE 802.1Qaz specification do not use bandwidth
	* groups so this is much simplified from the CEE case.
	+ * @bw: bandwidth index by traffic class
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits by traffic class
	+ * @max_frame_size: maximum frame size
	*/
	s32 ixgbe_dcb_calculate_tc_credits(u8 bw, u16 refill, u16 *max,
	int max_frame_size)
	@@ -79,8 +83,10 @@

	/**
	* ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
	- * @ixgbe_dcb_config: Struct containing DCB settings.
	- * @direction: Configuring either Tx or Rx.
	+ * @hw: pointer to hardware structure
	+ * @dcb_config: Struct containing DCB settings
	+ * @max_frame_size: Maximum frame size
	+ * @direction: Configuring either Tx or Rx
	*
	* This function calculates the credits allocated to each traffic class.
	* It should be called only after the rules are checked by
	Index: sys/dev/ixgbe/ixgbe_dcb_82598.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_dcb_82598.c
	+++ sys/dev/ixgbe/ixgbe_dcb_82598.c
	@@ -112,7 +112,9 @@
	/**
	* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	*
	* Configure Rx Data Arbiter and credits for each traffic class.
	*/
	@@ -167,7 +169,10 @@
	/**
	* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	*
	* Configure Tx Descriptor Arbiter and credits for each traffic class.
	*/
	@@ -211,7 +216,10 @@
	/**
	* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	*
	* Configure Tx Data Arbiter and credits for each traffic class.
	*/
	@@ -256,7 +264,7 @@
	/**
	* ixgbe_dcb_config_pfc_82598 - Config priority flow control
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @pfc_en: enabled pfc bitmask
	*
	* Configure Priority Flow Control for each traffic class.
	*/
	@@ -340,7 +348,11 @@
	/**
	* ixgbe_dcb_hw_config_82598 - Config and enable DCB
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @link_speed: unused
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	*
	* Configure dcb settings and enable dcb mode.
	*/
	Index: sys/dev/ixgbe/ixgbe_dcb_82599.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_dcb_82599.c
	+++ sys/dev/ixgbe/ixgbe_dcb_82599.c
	@@ -111,7 +111,11 @@
	/**
	* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	+ * @map: priority to tc assignments indexed by priority
	*
	* Configure Rx Packet Arbiter and credits for each traffic class.
	*/
	@@ -170,7 +174,10 @@
	/**
	* ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	*
	* Configure Tx Descriptor Arbiter and credits for each traffic class.
	*/
	@@ -215,7 +222,11 @@
	/**
	* ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	+ * @map: priority to tc assignments indexed by priority
	*
	* Configure Tx Packet Arbiter and credits for each traffic class.
	*/
	@@ -363,6 +374,7 @@
	/**
	* ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
	* @hw: pointer to hardware structure
	+ * @dcb_config: pointer to ixgbe_dcb_config structure
	*
	* Configure queue statistics registers, all queues belonging to same traffic
	* class uses a single set of queue statistics counters.
	@@ -573,7 +585,12 @@
	/**
	* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
	* @hw: pointer to hardware structure
	- * @dcb_config: pointer to ixgbe_dcb_config structure
	+ * @link_speed: unused
	+ * @refill: refill credits index by traffic class
	+ * @max: max credits index by traffic class
	+ * @bwg_id: bandwidth grouping indexed by traffic class
	+ * @tsa: transmission selection algorithm indexed by traffic class
	+ * @map: priority to tc assignments indexed by priority
	*
	* Configure dcb settings and enable dcb mode.
	*/
	Index: sys/dev/ixgbe/ixgbe_phy.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_phy.c
	+++ sys/dev/ixgbe/ixgbe_phy.c
	@@ -88,8 +88,8 @@

	/**
	* ixgbe_ones_comp_byte_add - Perform one's complement addition
	- * @add1 - addend 1
	- * @add2 - addend 2
	+ * @add1: addend 1
	+ * @add2: addend 2
	*
	* Returns one's complement 8-bit sum.
	*/
	@@ -400,6 +400,7 @@
	/**
	* ixgbe_validate_phy_addr - Determines phy address is valid
	* @hw: pointer to hardware structure
	+ * @phy_addr: PHY address
	*
	**/
	bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
	@@ -577,6 +578,7 @@
	* the SWFW lock
	* @hw: pointer to hardware structure
	* @reg_addr: 32 bit address of PHY register to read
	+ * @device_type: 5 bit device type
	* @phy_data: Pointer to read data from PHY register
	**/
	s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
	@@ -658,6 +660,7 @@
	* using the SWFW lock - this function is needed in most cases
	* @hw: pointer to hardware structure
	* @reg_addr: 32 bit address of PHY register to read
	+ * @device_type: 5 bit device type
	* @phy_data: Pointer to read data from PHY register
	**/
	s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
	@@ -874,6 +877,7 @@
	* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
	* @hw: pointer to hardware structure
	* @speed: new link speed
	+ * @autoneg_wait_to_complete: unused
	**/
	s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
	ixgbe_link_speed speed,
	@@ -979,6 +983,8 @@
	/**
	* ixgbe_check_phy_link_tnx - Determine link and speed status
	* @hw: pointer to hardware structure
	+ * @speed: current link speed
	+ * @link_up: TRUE is link is up, FALSE otherwise
	*
	* Reads the VS1 register to determine if link is up and the current speed for
	* the PHY.
	@@ -1934,7 +1940,7 @@
	* ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset at address 0xA2
	- * @eeprom_data: value read
	+ * @sff8472_data: value read
	*
	* Performs byte read operation to SFP module's SFF-8472 data over I2C
	**/
	@@ -1983,6 +1989,7 @@
	* ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to read
	+ * @dev_addr: address to read from
	* @data: value read
	* @lock: TRUE if to take and release semaphore
	*
	@@ -2074,6 +2081,7 @@
	* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to read
	+ * @dev_addr: address to read from
	* @data: value read
	*
	* Performs byte read operation to SFP module's EEPROM over I2C interface at
	@@ -2090,6 +2098,7 @@
	* ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to read
	+ * @dev_addr: address to read from
	* @data: value read
	*
	* Performs byte read operation to SFP module's EEPROM over I2C interface at
	@@ -2106,6 +2115,7 @@
	* ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to write
	+ * @dev_addr: address to write to
	* @data: value to write
	* @lock: TRUE if to take and release semaphore
	*
	@@ -2177,6 +2187,7 @@
	* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to write
	+ * @dev_addr: address to write to
	* @data: value to write
	*
	* Performs byte write operation to SFP module's EEPROM over I2C interface at
	@@ -2193,6 +2204,7 @@
	* ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
	* @hw: pointer to hardware structure
	* @byte_offset: byte offset to write
	+ * @dev_addr: address to write to
	* @data: value to write
	*
	* Performs byte write operation to SFP module's EEPROM over I2C interface at
	@@ -2575,6 +2587,7 @@
	{
	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
	bool data;
	+ UNREFERENCED_1PARAMETER(hw);

	DEBUGFUNC("ixgbe_get_i2c_data");

	Index: sys/dev/ixgbe/ixgbe_type.h
	===================================================================
	--- sys/dev/ixgbe/ixgbe_type.h
	+++ sys/dev/ixgbe/ixgbe_type.h
	@@ -274,7 +274,6 @@
	#define IXGBE_I2C_BB_EN_X550 0x00000100
	#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
	#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
	-
	#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)

	#define IXGBE_I2C_CLK_OE_N_EN 0
	@@ -286,6 +285,47 @@
	#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500


	+
	+#define NVM_OROM_OFFSET 0x17
	+#define NVM_OROM_BLK_LOW 0x83
	+#define NVM_OROM_BLK_HI 0x84
	+#define NVM_OROM_PATCH_MASK 0xFF
	+#define NVM_OROM_SHIFT 8
	+
	+#define NVM_VER_MASK 0x00FF /* version mask */
	+#define NVM_VER_SHIFT 8 /* version bit shift */
	+#define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */
	+#define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */
	+#define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */
	+#define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */
	+#define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
	+#define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */
	+#define NVM_ETK_OFF_LOW 0x2D /* version low order word */
	+#define NVM_ETK_OFF_HI 0x2E /* version high order word */
	+#define NVM_ETK_SHIFT 16 /* high version word shift */
	+#define NVM_VER_INVALID 0xFFFF
	+#define NVM_ETK_VALID 0x8000
	+#define NVM_INVALID_PTR 0xFFFF
	+#define NVM_VER_SIZE 32 /* version sting size */
	+
	+struct ixgbe_nvm_version {
	+ u32 etk_id;
	+ u8 nvm_major;
	+ u16 nvm_minor;
	+ u8 nvm_id;
	+
	+ bool oem_valid;
	+ u8 oem_major;
	+ u8 oem_minor;
	+ u16 oem_release;
	+
	+ bool or_valid;
	+ u8 or_major;
	+ u16 or_build;
	+ u8 or_patch;
	+
	+};
	+
	/* Interrupt Registers */
	#define IXGBE_EICR 0x00800
	#define IXGBE_EICS 0x00808
	@@ -553,7 +593,6 @@
	#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */
	#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */
	#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */
	-
	#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16

	#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
	@@ -563,7 +602,6 @@

	/* Four Flexible Filters are supported */
	#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
	-
	/* Six Flexible Filters are supported */
	#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
	/* Eight Flexible Filters are supported */
	@@ -711,8 +749,6 @@
	#define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */
	#define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */

	-
	-
	/* Security Control Registers */
	#define IXGBE_SECTXCTRL 0x08800
	#define IXGBE_SECTXSTAT 0x08804
	@@ -850,7 +886,6 @@
	#define IXGBE_RTTBCNRTT 0x05150
	#define IXGBE_RTTBCNRD 0x0498C

	-
	/* FCoE DMA Context Registers */
	/* FCoE Direct DMA Context */
	#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
	@@ -4275,7 +4310,6 @@
	#define BYPASS_LOG_EVENT_SHIFT 28
	#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */

	-
	#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
	#define IXGBE_FUSES0_300MHZ (1 << 5)
	#define IXGBE_FUSES0_REV_MASK (3 << 6)
	Index: sys/dev/ixgbe/ixgbe_vf.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_vf.c
	+++ sys/dev/ixgbe/ixgbe_vf.c
	@@ -376,6 +376,7 @@
	* @mc_addr_list: array of multicast addresses to program
	* @mc_addr_count: number of multicast addresses to program
	* @next: caller supplied function to return next address in list
	+ * @clear: unused
	*
	* Updates the Multicast Table Array.
	**/
	@@ -509,8 +510,9 @@
	}

	/**
	- * ixgbe_get_mac_addr_vf - Read device MAC address
	- * @hw: pointer to the HW structure
	+ * ixgbe_get_mac_addr_vf - Read device MAC address
	+ * @hw: pointer to the HW structure
	+ * @mac_addr: the MAC address
	**/
	s32 ixgbe_get_mac_addr_vf(struct ixgbe_hw hw, u8 mac_addr)
	{
	@@ -556,7 +558,6 @@
	* ixgbe_setup_mac_link_vf - Setup MAC link settings
	* @hw: pointer to hardware structure
	* @speed: new link speed
	- * @autoneg: TRUE if autonegotiation enabled
	* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
	*
	* Set the link speed in the AUTOC register and restarts link.
	Index: sys/dev/ixgbe/ixgbe_x540.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_x540.c
	+++ sys/dev/ixgbe/ixgbe_x540.c
	@@ -785,6 +785,9 @@

	swmask \|= swi2c_mask;
	fwmask \|= swi2c_mask << 2;
	+ if (hw->mac.type >= ixgbe_mac_X550)
	+ timeout = 1000;
	+
	for (i = 0; i < timeout; i++) {
	/* SW NVM semaphore bit is used for access to all
	* SW_FW_SYNC bits (not just NVM)
	Index: sys/dev/ixgbe/ixgbe_x550.c
	===================================================================
	--- sys/dev/ixgbe/ixgbe_x550.c
	+++ sys/dev/ixgbe/ixgbe_x550.c
	@@ -336,98 +336,6 @@
	IXGBE_WRITE_FLUSH(hw);
	}

	-/**
	- * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
	- * @hw: pointer to hardware structure
	- * @reg_addr: 32 bit address of PHY register to read
	- * @dev_type: always unused
	- * @phy_data: Pointer to read data from PHY register
	- */
	-static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
	- u32 dev_type, u16 *phy_data)
	-{
	- u32 i, data, command;
	- UNREFERENCED_1PARAMETER(dev_type);
	-
	- /* Setup and write the read command */
	- command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	- IXGBE_MSCA_OLD_PROTOCOL \| IXGBE_MSCA_READ_AUTOINC \|
	- IXGBE_MSCA_MDI_COMMAND;
	-
	- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	-
	- /* Check every 10 usec to see if the access completed.
	- * The MDI Command bit will clear when the operation is
	- * complete
	- */
	- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
	- usec_delay(10);
	-
	- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	- if (!(command & IXGBE_MSCA_MDI_COMMAND))
	- break;
	- }
	-
	- if (command & IXGBE_MSCA_MDI_COMMAND) {
	- ERROR_REPORT1(IXGBE_ERROR_POLLING,
	- "PHY read command did not complete.\n");
	- return IXGBE_ERR_PHY;
	- }
	-
	- /* Read operation is complete. Get the data from MSRWD */
	- data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
	- data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
	- *phy_data = (u16)data;
	-
	- return IXGBE_SUCCESS;
	-}
	-
	-/**
	- * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
	- * @hw: pointer to hardware structure
	- * @reg_addr: 32 bit PHY register to write
	- * @dev_type: always unused
	- * @phy_data: Data to write to the PHY register
	- */
	-static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
	- u32 dev_type, u16 phy_data)
	-{
	- u32 i, command;
	- UNREFERENCED_1PARAMETER(dev_type);
	-
	- /* Put the data in the MDI single read and write data register*/
	- IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
	-
	- /* Setup and write the write command */
	- command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	- IXGBE_MSCA_OLD_PROTOCOL \| IXGBE_MSCA_WRITE \|
	- IXGBE_MSCA_MDI_COMMAND;
	-
	- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	-
	- /* Check every 10 usec to see if the access completed.
	- * The MDI Command bit will clear when the operation is
	- * complete
	- */
	- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
	- usec_delay(10);
	-
	- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	- if (!(command & IXGBE_MSCA_MDI_COMMAND))
	- break;
	- }
	-
	- if (command & IXGBE_MSCA_MDI_COMMAND) {
	- ERROR_REPORT1(IXGBE_ERROR_POLLING,
	- "PHY write cmd didn't complete\n");
	- return IXGBE_ERR_PHY;
	- }
	-
	- return IXGBE_SUCCESS;
	-}
	-
	/**
	* ixgbe_identify_phy_x550em - Get PHY type based on device id
	* @hw: pointer to hardware structure
	@@ -468,14 +376,10 @@
	return ixgbe_identify_phy_generic(hw);
	case IXGBE_DEV_ID_X550EM_X_1G_T:
	hw->phy.type = ixgbe_phy_ext_1g_t;
	- hw->phy.ops.read_reg = NULL;
	- hw->phy.ops.write_reg = NULL;
	break;
	case IXGBE_DEV_ID_X550EM_A_1G_T:
	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
	hw->phy.type = ixgbe_phy_fw;
	- hw->phy.ops.read_reg = NULL;
	- hw->phy.ops.write_reg = NULL;
	if (hw->bus.lan_id)
	hw->phy.phy_semaphore_mask \|= IXGBE_GSSR_PHY1_SM;
	else
	@@ -1770,6 +1674,8 @@
	/**
	* ixgbe_setup_sgmii - Set up link for sgmii
	* @hw: pointer to hardware structure
	+ * @speed: new link speed
	+ * @autoneg_wait: TRUE when waiting for completion is needed
	*/
	static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
	bool autoneg_wait)
	@@ -1835,8 +1741,10 @@
	}

	/**
	- * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
	+ * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
	* @hw: pointer to hardware structure
	+ * @speed: new link speed
	+ * @autoneg_wait: TRUE when waiting for completion is needed
	*/
	static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
	bool autoneg_wait)
	@@ -2379,10 +2287,10 @@
	switch (hw->device_id) {
	case IXGBE_DEV_ID_X550EM_A_1G_T:
	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
	- phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
	- phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
	- hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
	- hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
	+ phy->ops.read_reg_mdi = NULL;
	+ phy->ops.write_reg_mdi = NULL;
	+ hw->phy.ops.read_reg = NULL;
	+ hw->phy.ops.write_reg = NULL;
	phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
	if (hw->bus.lan_id)
	hw->phy.phy_semaphore_mask \|= IXGBE_GSSR_PHY1_SM;
	@@ -2403,6 +2311,9 @@
	/* set up for CS4227 usage */
	hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
	break;
	+ case IXGBE_DEV_ID_X550EM_X_1G_T:
	+ phy->ops.read_reg_mdi = NULL;
	+ phy->ops.write_reg_mdi = NULL;
	default:
	break;
	}
	@@ -2539,7 +2450,8 @@
	DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
	status);

	- if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) {
	+ if (status == IXGBE_ERR_SFP_NOT_SUPPORTED \|\|
	+ status == IXGBE_ERR_PHY_ADDR_INVALID) {
	DEBUGOUT("Returning from reset HW due to PHY init failure\n");
	return status;
	}
	@@ -2700,6 +2612,8 @@
	/**
	* ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
	* @hw: pointer to hardware structure
	+ * @speed: new link speed
	+ * @autoneg_wait_to_complete: unused
	*
	* Configure the external PHY and the integrated KR PHY for SFP support.
	**/
	@@ -2792,6 +2706,8 @@
	/**
	* ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
	* @hw: pointer to hardware structure
	+ * @speed: new link speed
	+ * @autoneg_wait_to_complete: unused
	*
	* Configure the the integrated PHY for SFP support.
	**/
	@@ -3214,6 +3130,8 @@
	buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
	/* one word */
	buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
	+ buffer.pad2 = 0;
	+ buffer.pad3 = 0;

	status = hw->mac.ops.acquire_swfw_sync(hw, mask);
	if (status)
	@@ -3272,6 +3190,8 @@
	/* convert offset from words to bytes */
	buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
	buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
	+ buffer.pad2 = 0;
	+ buffer.pad3 = 0;

	status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
	IXGBE_HI_COMMAND_TIMEOUT);
	@@ -3409,6 +3329,8 @@
	* @ptr: pointer offset in eeprom
	* @size: size of section pointed by ptr, if 0 first word will be used as size
	* @csum: address of checksum to update
	+ * @buffer: pointer to buffer containing calculated checksum
	+ * @buffer_size: size of buffer
	*
	* Returns error status for any failure
	*/
	@@ -3780,6 +3702,7 @@

	/**
	* ixgbe_disable_rx_x550 - Disable RX unit
	+ * @hw: pointer to hardware structure
	*
	* Enables the Rx DMA unit for x550
	**/
	@@ -4424,6 +4347,7 @@
	* ixgbe_read_phy_reg_x550a - Reads specified PHY register
	* @hw: pointer to hardware structure
	* @reg_addr: 32 bit address of PHY register to read
	+ * @device_type: 5 bit device type
	* @phy_data: Pointer to read data from PHY register
	*
	* Reads a value from a specified PHY register using the SWFW lock and PHY

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