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diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -319,14 +319,12 @@
* - Configure EL2 to support running the kernel at EL1 and exit to that
*/
LENTRY(enter_kernel_el)
-#define INIT_SCTLR_EL1 (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | \
- SCTLR_TSCXT | SCTLR_EOS)
mrs x23, CurrentEL
and x23, x23, #(CURRENTEL_EL_MASK)
cmp x23, #(CURRENTEL_EL_EL2)
b.eq 1f
- ldr x2, =INIT_SCTLR_EL1
+ ldr x2, =SCTLR_MMU_OFF
msr sctlr_el1, x2
/* SCTLR_EOS is set so eret is a context synchronizing event so we
* need an isb here to ensure it's observed by later instructions,
@@ -370,7 +368,7 @@
msr vmpidr_el2, x2
/* Set the initial sctlr_el1 */
- ldr x2, =INIT_SCTLR_EL1
+ ldr x2, =SCTLR_MMU_OFF
msr sctlr_el1, x2
/* Check if the E2H flag is set */
@@ -443,7 +441,6 @@
isb
eret
-#undef INIT_SCTLR_EL1
LEND(enter_kernel_el)
/*
@@ -1038,11 +1035,7 @@
/*
* Setup SCTLR.
*/
- ldr x2, sctlr_set
- ldr x3, sctlr_clear
- mrs x1, sctlr_el1
- bic x1, x1, x3 /* Clear the required bits */
- orr x1, x1, x2 /* Set the required bits */
+ ldr x1, =SCTLR_MMU_ON
msr sctlr_el1, x1
isb
@@ -1067,16 +1060,6 @@
.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \
TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA | \
TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA)
-sctlr_set:
- /* Bits to set */
- .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
- SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
- SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
- SCTLR_M | SCTLR_CP15BEN | SCTLR_BT1 | SCTLR_BT0)
-sctlr_clear:
- /* Bits to clear */
- .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
- SCTLR_ITD | SCTLR_A)
LEND(start_mmu)
ENTRY(abort)
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2608,6 +2608,26 @@
#define SCTLR_EnALS (UL(0x1) << 56)
#define SCTLR_EPAN (UL(0x1) << 57)
+#define SCTLR_MMU_OFF \
+ (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | SCTLR_TSCXT | SCTLR_EOS)
+#define SCTLR_MMU_ON \
+ (SCTLR_MMU_OFF | \
+ SCTLR_BT1 | \
+ SCTLR_BT0 | \
+ SCTLR_UCI | \
+ SCTLR_SPAN | \
+ SCTLR_nTWE | \
+ SCTLR_nTWI | \
+ SCTLR_UCT | \
+ SCTLR_DZE | \
+ SCTLR_I | \
+ SCTLR_SED | \
+ SCTLR_CP15BEN | \
+ SCTLR_SA0 | \
+ SCTLR_SA | \
+ SCTLR_C | \
+ SCTLR_M)
+
/* SCTLR_EL12 */
#define SCTLR_EL12_REG MRS_REG_ALT_NAME(SCTLR_EL12)
#define SCTLR_EL12_op0 3

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