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D28561.id83610.diff
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Index: sys/arm64/arm64/trap.c
===================================================================
--- sys/arm64/arm64/trap.c
+++ sys/arm64/arm64/trap.c
@@ -534,6 +534,11 @@
exception);
userret(td, frame);
break;
+ case EXCP_WATCHPT_EL0:
+ call_trapsignal(td, SIGTRAP, TRAP_TRACE, (void *)frame->tf_elr,
+ exception);
+ userret(td, frame);
+ break;
case EXCP_MSR:
/*
* The CPU can raise EXCP_MSR when userspace executes an mrs
Index: sys/arm64/include/armreg.h
===================================================================
--- sys/arm64/include/armreg.h
+++ sys/arm64/include/armreg.h
@@ -230,6 +230,7 @@
#define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */
#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */
#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
+#define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */
#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
#define EXCP_BRK 0x3c /* Breakpoint */
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D28561.id83610.diff (1015 B)
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D28561: arm64: handle watchpoint exceptions from EL0
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