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Index: emulators/Makefile
===================================================================
--- emulators/Makefile
+++ emulators/Makefile
@@ -129,6 +129,8 @@
SUBDIR += qtemu
SUBDIR += quasi88
SUBDIR += raine
+ SUBDIR += riscv-fesvr
+ SUBDIR += riscv-isa-sim
SUBDIR += rtc
SUBDIR += rubygem-fission
SUBDIR += simh
Index: emulators/riscv-fesvr/Makefile
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/Makefile
@@ -0,0 +1,35 @@
+# $FreeBSD$
+
+PORTNAME= riscv-fesvr
+PORTVERSION= 0.0.1
+PORTREVISION= 20170206
+CATEGORIES= emulators
+
+MAINTAINER= lwhsu@FreeBSD.org
+COMMENT= RISC-V Frontend Server
+
+LICENSE= BSD3CLAUSE
+LICENSE_FILE= ${WRKSRC}/LICENSE
+
+USE_GITHUB= yes
+GH_ACCOUNT= freebsd-riscv
+GH_TAGNAME= 10a0333
+
+USES= gmake
+HAS_CONFIGURE= yes
+USE_LDCONFIG= yes
+
+STRIP_FILES= bin/elf2hex \
+ lib/libfesvr.so
+
+post-patch:
+ ${REINPLACE_CMD} -e \
+ 's|[(]install_libs_dir[)]/pkgconfig|(INSTALLDIR)/libdata/pkgconfig|g' \
+ ${WRKSRC}/Makefile.in
+
+post-install:
+. for f in ${STRIP_FILES}
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f}
+. endfor
+
+.include <bsd.port.mk>
Index: emulators/riscv-fesvr/distinfo
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1486398914
+SHA256 (freebsd-riscv-riscv-fesvr-0.0.1-10a0333_GH0.tar.gz) = a1fc984b3ea49f77c11f876288853c2072ac449515e81e32983d179b9c79d52d
+SIZE (freebsd-riscv-riscv-fesvr-0.0.1-10a0333_GH0.tar.gz) = 104214
Index: emulators/riscv-fesvr/pkg-descr
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/pkg-descr
@@ -0,0 +1,7 @@
+RISC-V Frontend Server
+
+The RISC-V front-end server library, which facilitates communication between a
+host machine and a RISC-V target machine. It is usually not meant to be used as
+a standalone package.
+
+WWW: https://github.com/freebsd-riscv/riscv-fesvr
Index: emulators/riscv-fesvr/pkg-plist
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/pkg-plist
@@ -0,0 +1,18 @@
+bin/elf2hex
+include/fesvr/configstring.h
+include/fesvr/context.h
+include/fesvr/device.h
+include/fesvr/dtm.h
+include/fesvr/elf.h
+include/fesvr/elfloader.h
+include/fesvr/htif_hexwriter.h
+include/fesvr/htif_pthread.h
+include/fesvr/htif.h
+include/fesvr/memif.h
+include/fesvr/option_parser.h
+include/fesvr/rfb.h
+include/fesvr/syscall.h
+include/fesvr/term.h
+include/fesvr/tsi.h
+lib/libfesvr.so
+libdata/pkgconfig/riscv-fesvr.pc
Index: emulators/riscv-isa-sim/Makefile
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/Makefile
@@ -0,0 +1,50 @@
+# $FreeBSD$
+
+PORTNAME= riscv-isa-sim
+PORTVERSION= 0.0.1
+PORTREVISION= 20170206
+CATEGORIES= emulators
+
+MAINTAINER= lwhsu@FreeBSD.org
+COMMENT= Spike, a RISC-V ISA Simulator
+
+LICENSE= BSD3CLAUSE
+LICENSE_FILE= ${WRKSRC}/LICENSE
+
+LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr
+
+USE_GITHUB= yes
+GH_ACCOUNT= freebsd-riscv
+GH_TAGNAME= 11ec3a3
+
+USES= compiler:c++11-lang gmake pathfix shebangfix
+HAS_CONFIGURE= yes
+SHEBANG_FILES= scripts/vcs-version.sh
+USE_LDCONFIG= yes
+
+LDFLAGS+= -L${LOCALBASE}/lib
+CFLAGS+= -I${LOCALBASE}/include
+
+STRIP_FILES= bin/spike \
+ bin/spike-dasm \
+ bin/termios-xspike \
+ bin/xspike \
+ lib/libdummy_rocc.so \
+ lib/libriscv.so \
+ lib/libsoftfloat.so \
+ lib/libspike_main.so
+
+post-extract:
+ @${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp
+
+post-patch:
+ ${REINPLACE_CMD} -e \
+ 's|[(]install_libs_dir[)]/pkgconfig|(INSTALLDIR)/libdata/pkgconfig|g' \
+ ${WRKSRC}/Makefile.in
+
+post-install:
+. for f in ${STRIP_FILES}
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f}
+. endfor
+
+.include <bsd.port.mk>
Index: emulators/riscv-isa-sim/distinfo
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1486408487
+SHA256 (freebsd-riscv-riscv-isa-sim-0.0.1-11ec3a3_GH0.tar.gz) = fc2e48c69477c8b25994cf540f508d0beaec578d972d83c1683ec32eb49d1d85
+SIZE (freebsd-riscv-riscv-isa-sim-0.0.1-11ec3a3_GH0.tar.gz) = 187995
Index: emulators/riscv-isa-sim/files/patch-Makefile.in
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/files/patch-Makefile.in
@@ -0,0 +1,19 @@
+--- Makefile.in.orig 2016-08-01 15:40:47 UTC
++++ Makefile.in
+@@ -188,13 +188,13 @@ _$(1).cc :
+
+ # Build the object files for this subproject
+
+-$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs))
++$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs))
+ $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs))
+ $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs))
+ $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs))
+ $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs))
+-$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs))
+-$$($(2)_pch) : %.h.gch : %.h
++$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs))
++$$($(2)_pch) : %.h.gch : %.hpp
+ $(COMPILE) $$< -o $$@
+ # If using clang, don't depend (and thus don't build) precompiled headers
+ $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch))
Index: emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
@@ -0,0 +1,10 @@
+--- riscv/insn_template.cc.orig 2016-08-01 15:40:47 UTC
++++ riscv/insn_template.cc
+@@ -1,6 +1,6 @@
+ // See LICENSE for license details.
+
+-#include "insn_template.h"
++#include "insn_template.hpp"
+
+ reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
+ {
Index: emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
@@ -0,0 +1,18 @@
+--- riscv/riscv.mk.in.orig 2016-08-01 15:40:47 UTC
++++ riscv/riscv.mk.in
+@@ -21,13 +21,13 @@ riscv_hdrs = \
+ tracer.h \
+ extension.h \
+ rocc.h \
+- insn_template.h \
++ insn_template.hpp \
+ mulhi.h \
+ gdbserver.h \
+ debug_module.h \
+
+ riscv_precompiled_hdrs = \
+- insn_template.h \
++ insn_template.hpp \
+
+ riscv_srcs = \
+ processor.cc \
Index: emulators/riscv-isa-sim/pkg-descr
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/pkg-descr
@@ -0,0 +1,6 @@
+Spike, a RISC-V ISA Simulator
+
+The RISC-V ISA Simulator implements a functional model of one or more RISC-V
+processors.
+
+WWW: https://github.com/freebsd-riscv/riscv-isa-sim
Index: emulators/riscv-isa-sim/pkg-plist
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/pkg-plist
@@ -0,0 +1,39 @@
+bin/spike
+bin/spike-dasm
+bin/termios-xspike
+bin/xspike
+include/spike/cachesim.h
+include/spike/common.h
+include/spike/config.h
+include/spike/debug_module.h
+include/spike/decode.h
+include/spike/devices.h
+include/spike/disasm.h
+include/spike/encoding.h
+include/spike/extension.h
+include/spike/gdbserver.h
+include/spike/icache.h
+include/spike/insn_list.h
+include/spike/insn_template.hpp
+include/spike/internals.h
+include/spike/memtracer.h
+include/spike/mmu.h
+include/spike/mulhi.h
+include/spike/primitives.h
+include/spike/primitiveTypes.h
+include/spike/processor.h
+include/spike/rocc.h
+include/spike/sim.h
+include/spike/softfloat_types.h
+include/spike/softfloat.h
+include/spike/specialize.h
+include/spike/tracer.h
+include/spike/trap.h
+lib/libdummy_rocc.so
+lib/libriscv.so
+lib/libsoftfloat.so
+lib/libspike_main.so
+libdata/pkgconfig/riscv-dummy_rocc.pc
+libdata/pkgconfig/riscv-riscv.pc
+libdata/pkgconfig/riscv-softfloat.pc
+libdata/pkgconfig/riscv-spike_main.pc

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