D51893.id160325.diff
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	diff --git a/sys/dev/ufshci/ufshci.h b/sys/dev/ufshci/ufshci.h
	--- a/sys/dev/ufshci/ufshci.h
	+++ b/sys/dev/ufshci/ufshci.h
	@@ -638,6 +638,42 @@
	_Static_assert(sizeof(struct ufshci_device_descriptor) == 89,
	"bad size for ufshci_device_descriptor");

	+/* Defines the bit field of dExtendedUfsFeaturesSupport. */
	+enum ufshci_desc_wb_ext_ufs_feature {
	+ UFSHCI_DESC_EXT_UFS_FEATURE_FFU = (1 << 0),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_PSA = (1 << 1),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_DEV_LIFE_SPAN = (1 << 2),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_REFRESH_OP = (1 << 3),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_TOO_HIGH_TEMP = (1 << 4),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_TOO_LOW_TEMP = (1 << 5),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_EXT_TEMP = (1 << 6),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_HPB_SUPPORT = (1 << 7),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_WRITE_BOOSTER = (1 << 8),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_PERF_THROTTLING = (1 << 9),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_ADVANCED_RPMB = (1 << 10),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_ZONED_UFS_EXTENSION = (1 << 11),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_DEV_LEVEL_EXCEPTION = (1 << 12),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_HID = (1 << 13),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_BARRIER = (1 << 14),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_CLEAR_ERROR_HISTORY = (1 << 15),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_EXT_IID = (1 << 16),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_FBO = (1 << 17),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_FAST_RECOVERY_MODE = (1 << 18),
	+ UFSHCI_DESC_EXT_UFS_FEATURE_RPMB_VENDOR_CMD = (1 << 19),
	+};
	+
	+/* Defines the bit field of bWriteBoosterBufferType. */
	+enum ufshci_desc_wb_buffer_type {
	+ UFSHCI_DESC_WB_BUF_TYPE_LU_DEDICATED = 0x00,
	+ UFSHCI_DESC_WB_BUF_TYPE_SINGLE_SHARED = 0x01,
	+};
	+
	+/* Defines the bit field of bWriteBoosterBufferPreserveUserSpaceEn. */
	+enum ufshci_desc_user_space_config {
	+ UFSHCI_DESC_WB_BUF_USER_SPACE_REDUCTION = 0x00,
	+ UFSHCI_DESC_WB_BUF_PRESERVE_USER_SPACE = 0x01,
	+};
	+
	/*
	* UFS Spec 4.1, section 14.1.5.3 "Configuration Descriptor"
	* ConfigurationDescriptor use big-endian byte ordering.
	@@ -936,4 +972,37 @@
	UFSHCI_ATTR_B_REFRESH_METHOD = 0x2f,
	};

	+/* bAvailableWriteBoosterBufferSize codes (UFS WriteBooster abailable buffer
	+ * left %) */
	+enum ufshci_wb_available_buffer_Size {
	+ UFSHCI_ATTR_WB_AVAILABLE_0 = 0x00, /* 0% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_10 = 0x01, /* 10% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_20 = 0x02, /* 20% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_30 = 0x03, /* 30% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_40 = 0x04, /* 40% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_50 = 0x05, /* 50% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_60 = 0x06, /* 60% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_70 = 0x07, /* 70% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_80 = 0x08, /* 80% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_90 = 0x09, /* 90% buffer remains */
	+ UFSHCI_ATTR_WB_AVAILABLE_100 = 0x0A, /* 100% buffer remains */
	+};
	+
	+/* bWriteBoosterBufferLifeTimeEst codes (UFS WriteBooster buffer life %) */
	+enum ufshci_wb_lifetime {
	+ UFSHCI_ATTR_WB_LIFE_DISABLED = 0x00, /* Info not available */
	+ UFSHCI_ATTR_WB_LIFE_0_10 = 0x01, /* 0%–10% used */
	+ UFSHCI_ATTR_WB_LIFE_10_20 = 0x02, /* 10%–20% used */
	+ UFSHCI_ATTR_WB_LIFE_20_30 = 0x03, /* 20%–30% used */
	+ UFSHCI_ATTR_WB_LIFE_30_40 = 0x04, /* 30%–40% used */
	+ UFSHCI_ATTR_WB_LIFE_40_50 = 0x05, /* 40%–50% used */
	+ UFSHCI_ATTR_WB_LIFE_50_60 = 0x06, /* 50%–60% used */
	+ UFSHCI_ATTR_WB_LIFE_60_70 = 0x07, /* 60%–70% used */
	+ UFSHCI_ATTR_WB_LIFE_70_80 = 0x08, /* 70%–80% used */
	+ UFSHCI_ATTR_WB_LIFE_80_90 = 0x09, /* 80%–90% used */
	+ UFSHCI_ATTR_WB_LIFE_90_100 = 0x0A, /* 90%–100% used */
	+ UFSHCI_ATTR_WB_LIFE_EXCEEDED =
	+ 0x0B, /* Exceeded estimated life (treat as WB disabled) */
	+};
	+
	#endif /* __UFSHCI_H__ */
	diff --git a/sys/dev/ufshci/ufshci_ctrlr.c b/sys/dev/ufshci/ufshci_ctrlr.c
	--- a/sys/dev/ufshci/ufshci_ctrlr.c
	+++ b/sys/dev/ufshci/ufshci_ctrlr.c
	@@ -61,7 +61,7 @@
	int
	ufshci_ctrlr_construct(struct ufshci_controller *ctrlr, device_t dev)
	{
	- uint32_t ver, cap, hcs, ie;
	+ uint32_t ver, cap, hcs, ie, ahit;
	uint32_t timeout_period, retry_count;
	int error;

	@@ -127,6 +127,13 @@
	if (error)
	return (error);

	+ /* Read the UECPA register to clear */
	+ ufshci_mmio_read_4(ctrlr, uecpa);
	+
	+ /* Diable Auto-hibernate */
	+ ahit = 0;
	+ ufshci_mmio_write_4(ctrlr, ahit, ahit);
	+
	/*
	* The device_present(UFSHCI_HCS_REG_DP) bit becomes true if the host
	* controller has successfully received a Link Startup UIC command
	@@ -333,18 +340,19 @@
	return;
	}

	- /* Read Controller Descriptor (Device, Geometry)*/
	+ /* Read Controller Descriptor (Device, Geometry) */
	if (ufshci_dev_get_descriptor(ctrlr) != 0) {
	ufshci_ctrlr_fail(ctrlr, false);
	return;
	}

	- /* TODO: Configure Write Protect */
	+ if (ufshci_dev_config_write_booster(ctrlr)) {
	+ ufshci_ctrlr_fail(ctrlr, false);
	+ return;
	+ }

	/* TODO: Configure Background Operations */

	- /* TODO: Configure Write Booster */
	-
	if (ufshci_sim_attach(ctrlr) != 0) {
	ufshci_ctrlr_fail(ctrlr, false);
	return;
	diff --git a/sys/dev/ufshci/ufshci_dev.c b/sys/dev/ufshci/ufshci_dev.c
	--- a/sys/dev/ufshci/ufshci_dev.c
	+++ b/sys/dev/ufshci/ufshci_dev.c
	@@ -59,6 +59,14 @@
	0, desc, sizeof(struct ufshci_geometry_descriptor)));
	}

	+static int
	+ufshci_dev_read_unit_descriptor(struct ufshci_controller *ctrlr, uint8_t lun,
	+ struct ufshci_unit_descriptor *desc)
	+{
	+ return (ufshci_dev_read_descriptor(ctrlr, UFSHCI_DESC_TYPE_UNIT, lun, 0,
	+ desc, sizeof(struct ufshci_unit_descriptor)));
	+}
	+
	static int
	ufshci_dev_read_flag(struct ufshci_controller *ctrlr,
	enum ufshci_flags flag_type, uint8_t *flag)
	@@ -113,6 +121,61 @@
	return (0);
	}

	+static int
	+ufshci_dev_clear_flag(struct ufshci_controller *ctrlr,
	+ enum ufshci_flags flag_type)
	+{
	+ struct ufshci_completion_poll_status status;
	+ struct ufshci_query_param param;
	+
	+ param.function = UFSHCI_QUERY_FUNC_STANDARD_WRITE_REQUEST;
	+ param.opcode = UFSHCI_QUERY_OPCODE_CLEAR_FLAG;
	+ param.type = flag_type;
	+ param.index = 0;
	+ param.selector = 0;
	+ param.value = 0;
	+
	+ status.done = 0;
	+ ufshci_ctrlr_cmd_send_query_request(ctrlr, ufshci_completion_poll_cb,
	+ &status, param);
	+ ufshci_completion_poll(&status);
	+ if (status.error) {
	+ ufshci_printf(ctrlr, "ufshci_dev_clear_flag failed!\n");
	+ return (ENXIO);
	+ }
	+
	+ return (0);
	+}
	+
	+static int
	+ufshci_dev_read_attribute(struct ufshci_controller *ctrlr,
	+ enum ufshci_attributes attr_type, uint8_t index, uint8_t selector,
	+ uint64_t *value)
	+{
	+ struct ufshci_completion_poll_status status;
	+ struct ufshci_query_param param;
	+
	+ param.function = UFSHCI_QUERY_FUNC_STANDARD_READ_REQUEST;
	+ param.opcode = UFSHCI_QUERY_OPCODE_READ_ATTRIBUTE;
	+ param.type = attr_type;
	+ param.index = index;
	+ param.selector = selector;
	+ param.value = 0;
	+
	+ status.done = 0;
	+ ufshci_ctrlr_cmd_send_query_request(ctrlr, ufshci_completion_poll_cb,
	+ &status, param);
	+ ufshci_completion_poll(&status);
	+ if (status.error) {
	+ ufshci_printf(ctrlr, "ufshci_dev_read_attribute failed!\n");
	+ return (ENXIO);
	+ }
	+
	+ *value = status.cpl.response_upiu.query_response_upiu.value_64;
	+
	+ return (0);
	+}
	+
	static int
	ufshci_dev_write_attribute(struct ufshci_controller *ctrlr,
	enum ufshci_attributes attr_type, uint8_t index, uint8_t selector,
	@@ -270,7 +333,7 @@
	*/
	const uint32_t fast_mode = 1;
	const uint32_t rx_bit_shift = 4;
	- const uint32_t power_mode = (fast_mode << rx_bit_shift) \| fast_mode;
	+ uint32_t power_mode, peer_granularity;

	/* Update lanes with available TX/RX lanes */
	if (ufshci_uic_send_dme_get(ctrlr, PA_AvailTxDataLanes,
	@@ -295,6 +358,20 @@
	ctrlr->rx_lanes))
	return (ENXIO);

	+ if (ctrlr->quirks & UFSHCI_QUIRK_CHANGE_LANE_AND_GEAR_SEPARATELY) {
	+ /* Before changing gears, first change the number of lanes. */
	+ if (ufshci_uic_send_dme_get(ctrlr, PA_PWRMode, &power_mode))
	+ return (ENXIO);
	+ if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, power_mode))
	+ return (ENXIO);
	+
	+ /* Wait for power mode changed. */
	+ if (ufshci_uic_power_mode_ready(ctrlr)) {
	+ ufshci_reg_dump(ctrlr);
	+ return (ENXIO);
	+ }
	+ }
	+
	/* Set HS-GEAR to max gear */
	ctrlr->hs_gear = ctrlr->max_rx_hs_gear;
	if (ufshci_uic_send_dme_set(ctrlr, PA_TxGear, ctrlr->hs_gear))
	@@ -346,6 +423,7 @@
	return (ENXIO);

	/* Set TX/RX PWRMode */
	+ power_mode = (fast_mode << rx_bit_shift) \| fast_mode;
	if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, power_mode))
	return (ENXIO);

	@@ -366,7 +444,8 @@
	pause_sbt("ufshci", ustosbt(1250), 0, C_PREL(1));

	/* Test with dme_peer_get to make sure there are no errors. */
	- if (ufshci_uic_send_dme_peer_get(ctrlr, PA_Granularity, NULL))
	+ if (ufshci_uic_send_dme_peer_get(ctrlr, PA_Granularity,
	+ &peer_granularity))
	return (ENXIO);
	}

	@@ -398,7 +477,7 @@
	return (error);

	ver = be16toh(device->dev_desc.wSpecVersion);
	- ufshci_printf(ctrlr, "UFS device spec version %u.%u%u\n",
	+ ufshci_printf(ctrlr, "UFS device spec version %u.%u.%u\n",
	UFSHCIV(UFSHCI_VER_REG_MJR, ver), UFSHCIV(UFSHCI_VER_REG_MNR, ver),
	UFSHCIV(UFSHCI_VER_REG_VS, ver));
	ufshci_printf(ctrlr, "%u enabled LUNs found\n",
	@@ -426,3 +505,272 @@

	return (0);
	}
	+
	+static int
	+ufshci_dev_enable_write_booster(struct ufshci_controller *ctrlr)
	+{
	+ struct ufshci_device *dev = &ctrlr->ufs_dev;
	+ int error;
	+
	+ /* Enable WriteBooster */
	+ error = ufshci_dev_set_flag(ctrlr, UFSHCI_FLAG_F_WRITE_BOOSTER_EN);
	+ if (error) {
	+ ufshci_printf(ctrlr, "Failed to enable WriteBooster\n");
	+ return (error);
	+ }
	+ dev->is_wb_enabled = true;
	+
	+ /* Enable WriteBooster buffer flush during hibernate */
	+ error = ufshci_dev_set_flag(ctrlr,
	+ UFSHCI_FLAG_F_WB_BUFFER_FLUSH_DURING_HIBERNATE);
	+ if (error) {
	+ ufshci_printf(ctrlr,
	+ "Failed to enable WriteBooster buffer flush during hibernate\n");
	+ return (error);
	+ }
	+
	+ /* Enable WriteBooster buffer flush */
	+ error = ufshci_dev_set_flag(ctrlr, UFSHCI_FLAG_F_WB_BUFFER_FLUSH_EN);
	+ if (error) {
	+ ufshci_printf(ctrlr,
	+ "Failed to enable WriteBooster buffer flush\n");
	+ return (error);
	+ }
	+ dev->is_wb_flush_enabled = true;
	+
	+ return (0);
	+}
	+
	+static int
	+ufshci_dev_disable_write_booster(struct ufshci_controller *ctrlr)
	+{
	+ struct ufshci_device *dev = &ctrlr->ufs_dev;
	+ int error;
	+
	+ /* Disable WriteBooster buffer flush */
	+ error = ufshci_dev_clear_flag(ctrlr, UFSHCI_FLAG_F_WB_BUFFER_FLUSH_EN);
	+ if (error) {
	+ ufshci_printf(ctrlr,
	+ "Failed to disable WriteBooster buffer flush\n");
	+ return (error);
	+ }
	+ dev->is_wb_flush_enabled = false;
	+
	+ /* Disable WriteBooster buffer flush during hibernate */
	+ error = ufshci_dev_clear_flag(ctrlr,
	+ UFSHCI_FLAG_F_WB_BUFFER_FLUSH_DURING_HIBERNATE);
	+ if (error) {
	+ ufshci_printf(ctrlr,
	+ "Failed to disable WriteBooster buffer flush during hibernate\n");
	+ return (error);
	+ }
	+
	+ /* Disable WriteBooster */
	+ error = ufshci_dev_clear_flag(ctrlr, UFSHCI_FLAG_F_WRITE_BOOSTER_EN);
	+ if (error) {
	+ ufshci_printf(ctrlr, "Failed to disable WriteBooster\n");
	+ return (error);
	+ }
	+ dev->is_wb_enabled = false;
	+
	+ return (0);
	+}
	+
	+static int
	+ufshci_dev_is_write_booster_buffer_life_time_left(
	+ struct ufshci_controller ctrlr, bool is_life_time_left)
	+{
	+ struct ufshci_device *dev = &ctrlr->ufs_dev;
	+ uint8_t buffer_lun;
	+ uint64_t life_time;
	+ uint32_t error;
	+
	+ if (dev->wb_buffer_type == UFSHCI_DESC_WB_BUF_TYPE_LU_DEDICATED)
	+ buffer_lun = dev->wb_dedicated_lu;
	+ else
	+ buffer_lun = 0;
	+
	+ error = ufshci_dev_read_attribute(ctrlr,
	+ UFSHCI_ATTR_B_WB_BUFFER_LIFE_TIME_EST, buffer_lun, 0, &life_time);
	+ if (error)
	+ return (error);
	+
	+ *is_life_time_left = (life_time != UFSHCI_ATTR_WB_LIFE_EXCEEDED);
	+
	+ return (0);
	+}
	+
	+/*
	+ * This function is not yet in use. It will be used when suspend/resume is
	+ * implemented.
	+ */
	+static __unused int
	+ufshci_dev_need_write_booster_buffer_flush(struct ufshci_controller *ctrlr,
	+ bool *need_flush)
	+{
	+ struct ufshci_device *dev = &ctrlr->ufs_dev;
	+ bool is_life_time_left = false;
	+ uint64_t available_buffer_size, current_buffer_size;
	+ uint8_t buffer_lun;
	+ uint32_t error;
	+
	+ *need_flush = false;
	+
	+ if (!dev->is_wb_enabled)
	+ return (0);
	+
	+ error = ufshci_dev_is_write_booster_buffer_life_time_left(ctrlr,
	+ &is_life_time_left);
	+ if (error)
	+ return (error);
	+
	+ if (!is_life_time_left)
	+ return (ufshci_dev_disable_write_booster(ctrlr));
	+
	+ if (dev->wb_buffer_type == UFSHCI_DESC_WB_BUF_TYPE_LU_DEDICATED)
	+ buffer_lun = dev->wb_dedicated_lu;
	+ else
	+ buffer_lun = 0;
	+
	+ error = ufshci_dev_read_attribute(ctrlr,
	+ UFSHCI_ATTR_B_AVAILABLE_WB_BUFFER_SIZE, buffer_lun, 0,
	+ &available_buffer_size);
	+ if (error)
	+ return (error);
	+
	+ switch (dev->wb_user_space_config_option) {
	+ case UFSHCI_DESC_WB_BUF_USER_SPACE_REDUCTION:
	+ *need_flush = (available_buffer_size <=
	+ UFSHCI_ATTR_WB_AVAILABLE_10);
	+ break;
	+ case UFSHCI_DESC_WB_BUF_PRESERVE_USER_SPACE:
	+ /*
	+ * In PRESERVE USER SPACE mode, flush should be performed when
	+ * the current buffer is greater than 0 and the available buffer
	+ * below write_booster_flush_threshold is left.
	+ */
	+ error = ufshci_dev_read_attribute(ctrlr,
	+ UFSHCI_ATTR_D_CURRENT_WB_BUFFER_SIZE, buffer_lun, 0,
	+ &current_buffer_size);
	+ if (error)
	+ return (error);
	+
	+ if (current_buffer_size == 0)
	+ return (0);
	+
	+ *need_flush = (available_buffer_size <
	+ dev->write_booster_flush_threshold);
	+ break;
	+ default:
	+ ufshci_printf(ctrlr,
	+ "Invalid bWriteBoosterBufferPreserveUserSpaceEn value");
	+ return (EINVAL);
	+ }
	+
	+ /*
	+ * TODO: Need to handle WRITEBOOSTER_FLUSH_NEEDED exception case from
	+ * wExceptionEventStatus attribute.
	+ */
	+
	+ return (0);
	+}
	+
	+int
	+ufshci_dev_config_write_booster(struct ufshci_controller *ctrlr)
	+{
	+ struct ufshci_device *dev = &ctrlr->ufs_dev;
	+ uint32_t extended_ufs_feature_support;
	+ uint32_t alloc_units;
	+ struct ufshci_unit_descriptor unit_desc;
	+ uint8_t lun;
	+ bool is_life_time_left;
	+ uint32_t mega_byte = 1024 * 1024;
	+ uint32_t error = 0;
	+
	+ extended_ufs_feature_support = be32toh(
	+ dev->dev_desc.dExtendedUfsFeaturesSupport);
	+ if (!(extended_ufs_feature_support &
	+ UFSHCI_DESC_EXT_UFS_FEATURE_WRITE_BOOSTER)) {
	+ /* This device does not support Write Booster */
	+ return (0);
	+ }
	+
	+ if (ufshci_dev_enable_write_booster(ctrlr))
	+ return (0);
	+
	+ /* Get WriteBooster buffer parameters */
	+ dev->wb_buffer_type = dev->dev_desc.bWriteBoosterBufferType;
	+ dev->wb_user_space_config_option =
	+ dev->dev_desc.bWriteBoosterBufferPreserveUserSpaceEn;
	+
	+ /*
	+ * Find the size of the write buffer.
	+ * With LU-dedicated (00h), the WriteBooster buffer is assigned
	+ * exclusively to one chosen LU (not one-per-LU), whereas Shared (01h)
	+ * uses a single device-wide buffer shared by multiple LUs.
	+ */
	+ if (dev->wb_buffer_type == UFSHCI_DESC_WB_BUF_TYPE_SINGLE_SHARED) {
	+ alloc_units = be32toh(
	+ dev->dev_desc.dNumSharedWriteBoosterBufferAllocUnits);
	+ ufshci_printf(ctrlr,
	+ "WriteBooster buffer type = Shared, alloc_units=%d\n",
	+ alloc_units);
	+ } else if (dev->wb_buffer_type ==
	+ UFSHCI_DESC_WB_BUF_TYPE_LU_DEDICATED) {
	+ ufshci_printf(ctrlr, "WriteBooster buffer type = Dedicated\n");
	+ for (lun = 0; lun < ctrlr->max_lun_count; lun++) {
	+ /* Find a dedicated buffer using a unit descriptor */
	+ if (ufshci_dev_read_unit_descriptor(ctrlr, lun,
	+ &unit_desc))
	+ continue;
	+
	+ alloc_units = be32toh(
	+ unit_desc.dLUNumWriteBoosterBufferAllocUnits);
	+ if (alloc_units) {
	+ dev->wb_dedicated_lu = lun;
	+ break;
	+ }
	+ }
	+ } else {
	+ ufshci_printf(ctrlr,
	+ "Not supported WriteBooster buffer type: 0x%x\n",
	+ dev->wb_buffer_type);
	+ goto out;
	+ }
	+
	+ if (alloc_units == 0) {
	+ ufshci_printf(ctrlr, "The WriteBooster buffer size is zero\n");
	+ goto out;
	+ }
	+
	+ dev->wb_buffer_size_mb = alloc_units *
	+ dev->geo_desc.bAllocationUnitSize *
	+ (be32toh(dev->geo_desc.dSegmentSize)) /
	+ (mega_byte / UFSHCI_SECTOR_SIZE);
	+
	+ /* Set to flush when 40% of the available buffer size remains */
	+ dev->write_booster_flush_threshold = UFSHCI_ATTR_WB_AVAILABLE_40;
	+
	+ /*
	+ * Check if WriteBooster Buffer lifetime is left.
	+ * WriteBooster Buffer lifetime — percent of life used based on P/E
	+ * cycles. If "preserve user space" is enabled, writes to normal user
	+ * space also consume WB life since the area is shared.
	+ */
	+ error = ufshci_dev_is_write_booster_buffer_life_time_left(ctrlr,
	+ &is_life_time_left);
	+ if (error)
	+ goto out;
	+
	+ if (!is_life_time_left) {
	+ ufshci_printf(ctrlr,
	+ "There is no WriteBooster buffer life time left.\n");
	+ goto out;
	+ }
	+
	+ ufshci_printf(ctrlr, "WriteBooster Enabled\n");
	+ return (0);
	+out:
	+ ufshci_dev_disable_write_booster(ctrlr);
	+ return (error);
	+}
	\ No newline at end of file
	diff --git a/sys/dev/ufshci/ufshci_pci.c b/sys/dev/ufshci/ufshci_pci.c
	--- a/sys/dev/ufshci/ufshci_pci.c
	+++ b/sys/dev/ufshci/ufshci_pci.c
	@@ -53,7 +53,8 @@
	{ 0x98fa8086, "Intel Lakefield UFS Host Controller",
	UFSHCI_REF_CLK_19_2MHz,
	UFSHCI_QUIRK_LONG_PEER_PA_TACTIVATE \|
	- UFSHCI_QUIRK_WAIT_AFTER_POWER_MODE_CHANGE },
	+ UFSHCI_QUIRK_WAIT_AFTER_POWER_MODE_CHANGE \|
	+ UFSHCI_QUIRK_CHANGE_LANE_AND_GEAR_SEPARATELY },
	{ 0x54ff8086, "Intel UFS Host Controller", UFSHCI_REF_CLK_19_2MHz },
	{ 0x00000000, NULL } };

	diff --git a/sys/dev/ufshci/ufshci_private.h b/sys/dev/ufshci/ufshci_private.h
	--- a/sys/dev/ufshci/ufshci_private.h
	+++ b/sys/dev/ufshci/ufshci_private.h
	@@ -46,6 +46,8 @@
	#define UFSHCI_UTR_ENTRIES (32)
	#define UFSHCI_UTRM_ENTRIES (8)

	+#define UFSHCI_SECTOR_SIZE (512)
	+
	struct ufshci_controller;

	struct ufshci_completion_poll_status {
	@@ -209,6 +211,15 @@
	struct ufshci_geometry_descriptor geo_desc;

	uint32_t unipro_version;
	+
	+ /* WriteBooster */
	+ bool is_wb_enabled;
	+ bool is_wb_flush_enabled;
	+ uint32_t wb_buffer_type;
	+ uint32_t wb_buffer_size_mb;
	+ uint32_t wb_user_space_config_option;
	+ uint8_t wb_dedicated_lu;
	+ uint32_t write_booster_flush_threshold;
	};

	/*
	@@ -224,7 +235,8 @@
	2 /* Need an additional 200 ms of PA_TActivate */
	#define UFSHCI_QUIRK_WAIT_AFTER_POWER_MODE_CHANGE \
	4 /* Need to wait 1250us after power mode change */
	-
	+#define UFSHCI_QUIRK_CHANGE_LANE_AND_GEAR_SEPARATELY \
	+ 8 /* Need to change the number of lanes before changing HS-GEAR. */
	uint32_t ref_clk;

	struct cam_sim *ufshci_sim;
	@@ -349,6 +361,7 @@
	int ufshci_dev_init_uic_power_mode(struct ufshci_controller *ctrlr);
	int ufshci_dev_init_ufs_power_mode(struct ufshci_controller *ctrlr);
	int ufshci_dev_get_descriptor(struct ufshci_controller *ctrlr);
	+int ufshci_dev_config_write_booster(struct ufshci_controller *ctrlr);

	/* Controller Command */
	void ufshci_ctrlr_cmd_send_nop(struct ufshci_controller *ctrlr,
	diff --git a/sys/dev/ufshci/ufshci_reg.h b/sys/dev/ufshci/ufshci_reg.h
	--- a/sys/dev/ufshci/ufshci_reg.h
	+++ b/sys/dev/ufshci/ufshci_reg.h
	@@ -274,7 +274,7 @@
	#define UFSHCI_HCS_REG_UTMRLRDY_MASK (0x1)
	#define UFSHCI_HCS_REG_UCRDY_SHIFT (3)
	#define UFSHCI_HCS_REG_UCRDY_MASK (0x1)
	-#define UFSHCI_HCS_REG_UPMCRS_SHIFT (7)
	+#define UFSHCI_HCS_REG_UPMCRS_SHIFT (8)
	#define UFSHCI_HCS_REG_UPMCRS_MASK (0x7)
	#define UFSHCI_HCS_REG_UTPEC_SHIFT (12)
	#define UFSHCI_HCS_REG_UTPEC_MASK (0xF)
	diff --git a/sys/dev/ufshci/ufshci_sysctl.c b/sys/dev/ufshci/ufshci_sysctl.c
	--- a/sys/dev/ufshci/ufshci_sysctl.c
	+++ b/sys/dev/ufshci/ufshci_sysctl.c
	@@ -152,6 +152,7 @@
	struct sysctl_ctx_list *ctrlr_ctx;
	struct sysctl_oid ctrlr_tree, que_tree, *ioq_tree;
	struct sysctl_oid_list ctrlr_list, ioq_list;
	+ struct ufshci_device *dev = &ctrlr->ufs_dev;
	#define QUEUE_NAME_LENGTH 16
	char queue_name[QUEUE_NAME_LENGTH];
	int i;
	@@ -177,6 +178,25 @@
	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "cap", CTLFLAG_RD,
	&ctrlr->cap, 0, "Number of I/O queue pairs");

	+ SYSCTL_ADD_BOOL(ctrlr_ctx, ctrlr_list, OID_AUTO, "wb_enabled",
	+ CTLFLAG_RD, &dev->is_wb_enabled, 0, "WriteBooster enable/disable");
	+
	+ SYSCTL_ADD_BOOL(ctrlr_ctx, ctrlr_list, OID_AUTO, "wb_flush_enabled",
	+ CTLFLAG_RD, &dev->is_wb_flush_enabled, 0,
	+ "WriteBooster flush enable/disable");
	+
	+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "wb_buffer_type",
	+ CTLFLAG_RD, &dev->wb_buffer_type, 0, "WriteBooster type");
	+
	+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "wb_buffer_size_mb",
	+ CTLFLAG_RD, &dev->wb_buffer_size_mb, 0,
	+ "WriteBooster buffer size in MB");
	+
	+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO,
	+ "wb_user_space_config_option", CTLFLAG_RD,
	+ &dev->wb_user_space_config_option, 0,
	+ "WriteBooster preserve user space mode");
	+
	SYSCTL_ADD_PROC(ctrlr_ctx, ctrlr_list, OID_AUTO, "timeout_period",
	CTLTYPE_UINT \| CTLFLAG_RW \| CTLFLAG_MPSAFE, &ctrlr->timeout_period,
	0, ufshci_sysctl_timeout_period, "IU",
	diff --git a/sys/dev/ufshci/ufshci_uic_cmd.c b/sys/dev/ufshci/ufshci_uic_cmd.c
	--- a/sys/dev/ufshci/ufshci_uic_cmd.c
	+++ b/sys/dev/ufshci/ufshci_uic_cmd.c
	@@ -14,7 +14,7 @@
	int
	ufshci_uic_power_mode_ready(struct ufshci_controller *ctrlr)
	{
	- uint32_t is;
	+ uint32_t is, hcs;
	int timeout;

	/* Wait for the IS flag to change */
	@@ -40,6 +40,15 @@
	DELAY(10);
	}

	+ /* Check HCS power mode change request status */
	+ hcs = ufshci_mmio_read_4(ctrlr, hcs);
	+ if (UFSHCIV(UFSHCI_HCS_REG_UPMCRS, hcs) != 0x01) {
	+ ufshci_printf(ctrlr,
	+ "Power mode change request status error: 0x%x\n",
	+ UFSHCIV(UFSHCI_HCS_REG_UPMCRS, hcs));
	+ return (ENXIO);
	+ }
	+
	return (0);
	}

	@@ -112,6 +121,7 @@
	struct ufshci_uic_cmd uic_cmd, uint32_t return_value)
	{
	int error;
	+ uint32_t config_result_code;

	mtx_lock(&ctrlr->uic_cmd_lock);

	@@ -134,6 +144,13 @@
	if (error)
	return (ENXIO);

	+ config_result_code = ufshci_mmio_read_4(ctrlr, ucmdarg2);
	+ if (config_result_code) {
	+ ufshci_printf(ctrlr,
	+ "Failed to send UIC command. (config result code = 0x%x)\n",
	+ config_result_code);
	+ }
	+
	if (return_value != NULL)
	*return_value = ufshci_mmio_read_4(ctrlr, ucmdarg3);

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