D4908.id12238.diff
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	Index: head/sys/dev/sfxge/common/ef10_impl.h
	===================================================================
	--- head/sys/dev/sfxge/common/ef10_impl.h
	+++ head/sys/dev/sfxge/common/ef10_impl.h
	@@ -45,6 +45,47 @@
	#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
	#endif

	+extern __checkReturn efx_rc_t
	+efx_mcdi_get_port_assignment(
	+ __in efx_nic_t *enp,
	+ __out uint32_t *portp);
	+
	+extern __checkReturn efx_rc_t
	+efx_mcdi_get_port_modes(
	+ __in efx_nic_t *enp,
	+ __out uint32_t *modesp);
	+
	+extern __checkReturn efx_rc_t
	+efx_mcdi_get_mac_address_pf(
	+ __in efx_nic_t *enp,
	+ __out_ecount_opt(6) uint8_t mac_addrp[6]);
	+
	+extern __checkReturn efx_rc_t
	+efx_mcdi_get_mac_address_vf(
	+ __in efx_nic_t *enp,
	+ __out_ecount_opt(6) uint8_t mac_addrp[6]);
	+
	+extern __checkReturn efx_rc_t
	+efx_mcdi_get_clock(
	+ __in efx_nic_t *enp,
	+ __out uint32_t *sys_freqp);
	+
	+extern __checkReturn efx_rc_t
	+efx_mcdi_get_vector_cfg(
	+ __in efx_nic_t *enp,
	+ __out_opt uint32_t *vec_basep,
	+ __out_opt uint32_t *pf_nvecp,
	+ __out_opt uint32_t *vf_nvecp);
	+
	+extern __checkReturn efx_rc_t
	+ef10_get_datapath_caps(
	+ __in efx_nic_t *enp);
	+
	+extern __checkReturn efx_rc_t
	+ef10_external_port_mapping(
	+ __in efx_nic_t *enp,
	+ __in uint32_t port,
	+ __out uint8_t *external_portp);


	#ifdef __cplusplus
	Index: head/sys/dev/sfxge/common/efx_impl.h
	===================================================================
	--- head/sys/dev/sfxge/common/efx_impl.h
	+++ head/sys/dev/sfxge/common/efx_impl.h
	@@ -358,6 +358,7 @@

	typedef struct efx_nic_ops_s {
	efx_rc_t (eno_probe)(efx_nic_t );
	+ efx_rc_t (eno_board_cfg)(efx_nic_t );
	efx_rc_t (eno_set_drv_limits)(efx_nic_t , efx_drv_limits_t*);
	efx_rc_t (eno_reset)(efx_nic_t );
	efx_rc_t (eno_init)(efx_nic_t );
	Index: head/sys/dev/sfxge/common/efx_nic.c
	===================================================================
	--- head/sys/dev/sfxge/common/efx_nic.c
	+++ head/sys/dev/sfxge/common/efx_nic.c
	@@ -247,6 +247,7 @@

	static efx_nic_ops_t __efx_nic_falcon_ops = {
	falcon_nic_probe, /* eno_probe */
	+ NULL, /* eno_board_cfg */
	NULL, /* eno_set_drv_limits */
	falcon_nic_reset, /* eno_reset */
	falcon_nic_init, /* eno_init */
	@@ -266,6 +267,7 @@

	static efx_nic_ops_t __efx_nic_siena_ops = {
	siena_nic_probe, /* eno_probe */
	+ NULL, /* eno_board_cfg */
	NULL, /* eno_set_drv_limits */
	siena_nic_reset, /* eno_reset */
	siena_nic_init, /* eno_init */
	@@ -285,6 +287,7 @@

	static efx_nic_ops_t __efx_nic_hunt_ops = {
	ef10_nic_probe, /* eno_probe */
	+ hunt_board_cfg, /* eno_board_cfg */
	ef10_nic_set_drv_limits, /* eno_set_drv_limits */
	ef10_nic_reset, /* eno_reset */
	ef10_nic_init, /* eno_init */
	@@ -300,6 +303,27 @@

	#endif /* EFSYS_OPT_HUNTINGTON */

	+#if EFSYS_OPT_MEDFORD
	+
	+static efx_nic_ops_t __efx_nic_medford_ops = {
	+ ef10_nic_probe, /* eno_probe */
	+ medford_board_cfg, /* eno_board_cfg */
	+ ef10_nic_set_drv_limits, /* eno_set_drv_limits */
	+ ef10_nic_reset, /* eno_reset */
	+ ef10_nic_init, /* eno_init */
	+ ef10_nic_get_vi_pool, /* eno_get_vi_pool */
	+ ef10_nic_get_bar_region, /* eno_get_bar_region */
	+#if EFSYS_OPT_DIAG
	+ ef10_sram_test, /* eno_sram_test */
	+ ef10_nic_register_test, /* eno_register_test */
	+#endif /* EFSYS_OPT_DIAG */
	+ ef10_nic_fini, /* eno_fini */
	+ ef10_nic_unprobe, /* eno_unprobe */
	+};
	+
	+#endif /* EFSYS_OPT_MEDFORD */
	+
	+
	__checkReturn efx_rc_t
	efx_nic_create(
	__in efx_family_t family,
	@@ -364,6 +388,24 @@
	break;
	#endif /* EFSYS_OPT_HUNTINGTON */

	+#if EFSYS_OPT_MEDFORD
	+ case EFX_FAMILY_MEDFORD:
	+ enp->en_enop = (efx_nic_ops_t *)&__efx_nic_medford_ops;
	+ /*
	+ * FW_ASSISTED_TSO ommitted as Medford only supports firmware
	+ * assisted TSO version 2, not the v1 scheme used on Huntington.
	+ */
	+ enp->en_features =
	+ EFX_FEATURE_IPV6 \|
	+ EFX_FEATURE_LINK_EVENTS \|
	+ EFX_FEATURE_PERIODIC_MAC_STATS \|
	+ EFX_FEATURE_MCDI \|
	+ EFX_FEATURE_MAC_HEADER_FILTERS \|
	+ EFX_FEATURE_MCDI_DMA \|
	+ EFX_FEATURE_PIO_BUFFERS;
	+ break;
	+#endif /* EFSYS_OPT_MEDFORD */
	+
	default:
	rc = ENOTSUP;
	goto fail2;
	Index: head/sys/dev/sfxge/common/hunt_impl.h
	===================================================================
	--- head/sys/dev/sfxge/common/hunt_impl.h
	+++ head/sys/dev/sfxge/common/hunt_impl.h
	@@ -54,6 +54,13 @@
	*/
	#define EF10_RX_WPTR_ALIGN 8

	+/*
	+ * Max byte offset into the packet the TCP header must start for the hardware
	+ * to be able to parse the packet correctly.
	+ * FIXME: Move to ef10_impl.h when it is included in all driver builds.
	+ */
	+#define EF10_TCP_HEADER_OFFSET_LIMIT 208
	+
	/* Invalid RSS context handle */
	#define EF10_RSS_CONTEXT_INVALID (0xffffffff)

	@@ -165,6 +172,10 @@
	__in efx_nic_t *enp);

	extern __checkReturn efx_rc_t
	+hunt_board_cfg(
	+ __in efx_nic_t *enp);
	+
	+extern __checkReturn efx_rc_t
	ef10_nic_set_drv_limits(
	__inout efx_nic_t *enp,
	__in efx_drv_limits_t *edlp);
	Index: head/sys/dev/sfxge/common/hunt_nic.c
	===================================================================
	--- head/sys/dev/sfxge/common/hunt_nic.c
	+++ head/sys/dev/sfxge/common/hunt_nic.c
	@@ -40,7 +40,7 @@

	#include "ef10_tlv_layout.h"

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	efx_mcdi_get_port_assignment(
	__in efx_nic_t *enp,
	__out uint32_t *portp)
	@@ -84,7 +84,7 @@
	return (rc);
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	efx_mcdi_get_port_modes(
	__in efx_nic_t *enp,
	__out uint32_t *modesp)
	@@ -204,7 +204,7 @@
	return (rc);
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	efx_mcdi_get_mac_address_pf(
	__in efx_nic_t *enp,
	__out_ecount_opt(6) uint8_t mac_addrp[6])
	@@ -262,7 +262,7 @@
	return (rc);
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	efx_mcdi_get_mac_address_vf(
	__in efx_nic_t *enp,
	__out_ecount_opt(6) uint8_t mac_addrp[6])
	@@ -325,7 +325,7 @@
	return (rc);
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	efx_mcdi_get_clock(
	__in efx_nic_t *enp,
	__out uint32_t *sys_freqp)
	@@ -375,7 +375,7 @@
	return (rc);
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	efx_mcdi_get_vector_cfg(
	__in efx_nic_t *enp,
	__out_opt uint32_t *vec_basep,
	@@ -888,7 +888,7 @@
	return (efx_mcdi_unlink_piobuf(enp, vi_index));
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	ef10_get_datapath_caps(
	__in efx_nic_t *enp)
	{
	@@ -991,6 +991,13 @@
	(1 << TLV_PORT_MODE_10G_10G_10G_10G),
	1
	},
	+ {
	+ EFX_FAMILY_MEDFORD,
	+ (1 << TLV_PORT_MODE_10G) \|
	+ (1 << TLV_PORT_MODE_10G_10G) \|
	+ (1 << TLV_PORT_MODE_10G_10G_10G_10G),
	+ 1
	+ },
	/* Supported modes requiring 2 outputs per port */
	{
	EFX_FAMILY_HUNTINGTON,
	@@ -999,18 +1006,25 @@
	(1 << TLV_PORT_MODE_40G_10G_10G) \|
	(1 << TLV_PORT_MODE_10G_10G_40G),
	2
	- }
	- /*
	- * NOTE: Medford modes will require 4 outputs per port:
	- * TLV_PORT_MODE_10G_10G_10G_10G_Q
	- * TLV_PORT_MODE_10G_10G_10G_10G_Q2
	- * The Q2 mode routes outputs to external port 2. Support for this
	- * will require a new field specifying the number to add after
	- * scaling by stride. This is fixed at 1 currently.
	- */
	+ },
	+ {
	+ EFX_FAMILY_MEDFORD,
	+ (1 << TLV_PORT_MODE_40G) \|
	+ (1 << TLV_PORT_MODE_40G_40G) \|
	+ (1 << TLV_PORT_MODE_40G_10G_10G) \|
	+ (1 << TLV_PORT_MODE_10G_10G_40G),
	+ 2
	+ },
	+ /* Supported modes requiring 4 outputs per port */
	+ {
	+ EFX_FAMILY_MEDFORD,
	+ (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) \|
	+ (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
	+ 4
	+ },
	};

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	ef10_external_port_mapping(
	__in efx_nic_t *enp,
	__in uint32_t port,
	@@ -1063,7 +1077,7 @@
	return (rc);
	}

	-static __checkReturn efx_rc_t
	+ __checkReturn efx_rc_t
	hunt_board_cfg(
	__in efx_nic_t *enp)
	{
	@@ -1319,7 +1333,7 @@
	* Maximum number of bytes into the frame the TCP header can start for
	* firmware assisted TSO to work.
	*/
	- encp->enc_tx_tso_tcp_header_offset_limit = 208;
	+ encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;

	return (0);

	@@ -1360,6 +1374,7 @@
	ef10_nic_probe(
	__in efx_nic_t *enp)
	{
	+ efx_nic_ops_t *enop = enp->en_enop;
	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
	efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
	efx_rc_t rc;
	@@ -1379,7 +1394,7 @@
	if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
	goto fail3;

	- if ((rc = hunt_board_cfg(enp)) != 0)
	+ if ((rc = enop->eno_board_cfg(enp)) != 0)
	if (rc != EACCES)
	goto fail4;

	Index: head/sys/dev/sfxge/common/medford_impl.h
	===================================================================
	--- head/sys/dev/sfxge/common/medford_impl.h
	+++ head/sys/dev/sfxge/common/medford_impl.h
	@@ -37,7 +37,29 @@
	extern "C" {
	#endif

	+/* Alignment requirement for value written to RX WPTR:
	+ * the WPTR must be aligned to an 8 descriptor boundary
	+ *
	+ * FIXME: Is this the same on Medford as Huntington?
	+ */
	+#define MEDFORD_RX_WPTR_ALIGN 8
	+
	+
	+
	+#ifndef ER_EZ_TX_PIOBUF_SIZE
	+#define ER_EZ_TX_PIOBUF_SIZE 4096
	+#endif
	+
	+
	#define MEDFORD_PIOBUF_NBUFS (16)
	+#define MEDFORD_PIOBUF_SIZE (ER_EZ_TX_PIOBUF_SIZE)
	+
	+#define MEDFORD_MIN_PIO_ALLOC_SIZE (MEDFORD_PIOBUF_SIZE / 32)
	+
	+
	+extern __checkReturn efx_rc_t
	+medford_board_cfg(
	+ __in efx_nic_t *enp);


	#ifdef __cplusplus
	Index: head/sys/dev/sfxge/common/medford_nic.c
	===================================================================
	--- head/sys/dev/sfxge/common/medford_nic.c
	+++ head/sys/dev/sfxge/common/medford_nic.c
	@@ -40,7 +40,205 @@

	#include "ef10_tlv_layout.h"

	+ __checkReturn efx_rc_t
	+medford_board_cfg(
	+ __in efx_nic_t *enp)
	+{
	+ efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
	+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
	+ uint8_t mac_addr[6] = { 0 };
	+ uint32_t board_type = 0;
	+ hunt_link_state_t hls;
	+ efx_port_t *epp = &(enp->en_port);
	+ uint32_t port;
	+ uint32_t pf;
	+ uint32_t vf;
	+ uint32_t mask;
	+ uint32_t flags;
	+ uint32_t sysclk;
	+ uint32_t base, nvec;
	+ efx_rc_t rc;
	+
	+ /*
	+ * FIXME: Likely to be incomplete and incorrect.
	+ * Parts of this should be shared with Huntington.
	+ */
	+
	+ if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
	+ goto fail1;
	+
	+ /*
	+ * NOTE: The MCDI protocol numbers ports from zero.
	+ * The common code MCDI interface numbers ports from one.
	+ */
	+ emip->emi_port = port + 1;
	+
	+ if ((rc = ef10_external_port_mapping(enp, port,
	+ &encp->enc_external_port)) != 0)
	+ goto fail2;
	+
	+ /*
	+ * Get PCIe function number from firmware (used for
	+ * per-function privilege and dynamic config info).
	+ * - PCIe PF: pf = PF number, vf = 0xffff.
	+ * - PCIe VF: pf = parent PF, vf = VF number.
	+ */
	+ if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
	+ goto fail3;
	+
	+ encp->enc_pf = pf;
	+ encp->enc_vf = vf;
	+
	+ /* MAC address for this function */
	+ if (EFX_PCI_FUNCTION_IS_PF(encp)) {
	+ rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
	+ if ((rc == 0) && (mac_addr[0] & 0x02)) {
	+ /*
	+ * If the static config does not include a global MAC
	+ * address pool then the board may return a locally
	+ * administered MAC address (this should only happen on
	+ * incorrectly programmed boards).
	+ */
	+ rc = EINVAL;
	+ }
	+ } else {
	+ rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
	+ }
	+ if (rc != 0)
	+ goto fail4;
	+
	+ EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
	+
	+ /* Board configuration */
	+ rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
	+ if (rc != 0) {
	+ /* Unprivileged functions may not be able to read board cfg */
	+ if (rc == EACCES)
	+ board_type = 0;
	+ else
	+ goto fail5;
	+ }
	+
	+ encp->enc_board_type = board_type;
	+ encp->enc_clk_mult = 1; /* not used for Medford */
	+
	+ /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
	+ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
	+ goto fail6;
	+
	+ /* Obtain the default PHY advertised capabilities */
	+ if ((rc = hunt_phy_get_link(enp, &hls)) != 0)
	+ goto fail7;
	+ epp->ep_default_adv_cap_mask = hls.hls_adv_cap_mask;
	+ epp->ep_adv_cap_mask = hls.hls_adv_cap_mask;
	+
	+ if (EFX_PCI_FUNCTION_IS_VF(encp)) {
	+ /*
	+ * Interrupt testing does not work for VFs. See bug50084.
	+ * FIXME: Does this still apply to Medford?
	+ */
	+ encp->enc_bug41750_workaround = B_TRUE;
	+ }
	+
	+ /* Chained multicast is always enabled on Medford */
	+ encp->enc_bug26807_workaround = B_TRUE;
	+
	+ /* Get sysclk frequency (in MHz). */
	+ if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
	+ goto fail8;
	+
	+ /*
	+ * The timer quantum is 1536 sysclk cycles, documented for the
	+ * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
	+ */
	+ encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
	+ encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
	+ FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
	+
	+ /* Check capabilities of running datapath firmware */
	+ if ((rc = ef10_get_datapath_caps(enp)) != 0)
	+ goto fail9;
	+
	+ /* Alignment for receive packet DMA buffers */
	+ encp->enc_rx_buf_align_start = 1;
	+
	+ /* FIXME: RX DMA end padding is configurable on Medford */
	+ encp->enc_rx_buf_align_end = 64;
	+
	+ /* Alignment for WPTR updates */
	+ encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
	+
	+ /*
	+ * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
	+ * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
	+ * resources (allocated to this PCIe function), which is zero until
	+ * after we have allocated VIs.
	+ */
	+ encp->enc_evq_limit = 1024;
	+ encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
	+ encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
	+
	+ encp->enc_buftbl_limit = 0xFFFFFFFF;
	+
	+ encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
	+ encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
	+ encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
	+
	+ /*
	+ * Get the current privilege mask. Note that this may be modified
	+ * dynamically, so this value is informational only. DO NOT use
	+ * the privilege mask to check for sufficient privileges, as that
	+ * can result in time-of-check/time-of-use bugs.
	+ */
	+ if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0)
	+ goto fail10;
	+
	+ encp->enc_privilege_mask = mask;
	+
	+ /* Get interrupt vector limits */
	+ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
	+ if (EFX_PCI_FUNCTION_IS_PF(encp))
	+ goto fail11;
	+
	+ /* Ignore error (cannot query vector limits from a VF). */
	+ base = 0;
	+ nvec = 1024;
	+ }
	+ encp->enc_intr_vec_base = base;
	+ encp->enc_intr_limit = nvec;
	+
	+ /*
	+ * Maximum number of bytes into the frame the TCP header can start for
	+ * firmware assisted TSO to work.
	+ */
	+ encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
	+
	+ return (0);
	+
	+fail11:
	+ EFSYS_PROBE(fail11);
	+fail10:
	+ EFSYS_PROBE(fail10);
	+fail9:
	+ EFSYS_PROBE(fail9);
	+fail8:
	+ EFSYS_PROBE(fail8);
	+fail7:
	+ EFSYS_PROBE(fail7);
	+fail6:
	+ EFSYS_PROBE(fail6);
	+fail5:
	+ EFSYS_PROBE(fail5);
	+fail4:
	+ EFSYS_PROBE(fail4);
	+fail3:
	+ EFSYS_PROBE(fail3);
	+fail2:
	+ EFSYS_PROBE(fail2);
	+fail1:
	+ EFSYS_PROBE1(fail1, efx_rc_t, rc);

	-
	+ return (rc);
	+}

	#endif /* EFSYS_OPT_MEDFORD */

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