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Index: share/man/man4/rtsx.4
===================================================================
--- share/man/man4/rtsx.4
+++ share/man/man4/rtsx.4
@@ -24,7 +24,7 @@
.\"
.\" $FreeBSD$
.\"
-.Dd April 25, 2021
+.Dd February 10, 2022
.Dt RTSX 4
.Os
.Sh NAME
@@ -70,6 +70,8 @@
.It
RTS525A
.It
+RTS5260
+.It
RTL8411B
.El
.Pp
@@ -103,6 +105,17 @@
.An Jesper Schmitz Mouridsen Aq Mt jsm@FreeBSD.org
.Sh CONTRIBUTORS
.An Lutz Bichler Aq Mt Lutz.Bichler@gmail.com
+.Sh DEBUGGING INFORMATION
+.Em dev.rtsx.0.debug_mask
+can be set with the following masks:
+.Bl -bullet
+.It
+0x01 - to show the basic flow of the driver,
+.It
+0x02 - to trace the SD commands,
+.It
+0x04 - to trace the tuning phase.
+.El
.Sh BUGS
.Bl -bullet
.It
Index: sys/dev/rtsx/rtsx.c
===================================================================
--- sys/dev/rtsx/rtsx.c
+++ sys/dev/rtsx/rtsx.c
@@ -132,7 +132,10 @@
uint8_t rtsx_read_only; /* card read only status */
uint8_t rtsx_inversion; /* inversion of card detection and read only status */
uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */
- uint8_t rtsx_debug; /* print debugging */
+ uint8_t rtsx_debug_mask; /* debugging mask */
+#define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */
+#define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */
+#define RTSX_DEBUG_TUNING 0x04 /* debug tuning */
#ifdef MMCCAM
uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */
#endif /* MMCCAM */
@@ -165,11 +168,12 @@
#define RTSX_RTS522A 0x522a
#define RTSX_RTS525A 0x525a
#define RTSX_RTS5249 0x5249
+#define RTSX_RTS5260 0x5260
#define RTSX_RTL8402 0x5286
#define RTSX_RTL8411 0x5289
#define RTSX_RTL8411B 0x5287
-#define RTSX_VERSION "2.1c"
+#define RTSX_VERSION "2.1d"
static const struct rtsx_device {
uint16_t vendor_id;
@@ -182,6 +186,7 @@
{ RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"},
{ RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"},
{ RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"},
+ { RTSX_REALTEK, RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe MMC/SD Card Reader"},
{ RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"},
{ RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"},
{ RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"},
@@ -209,6 +214,7 @@
static int rtsx_map_sd_drive(int index);
static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc);
static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc);
+static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc);
static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *);
static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val);
static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val);
@@ -555,7 +561,7 @@
status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */
sc->rtsx_intr_status = status;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status);
/* Ack interrupts. */
@@ -655,7 +661,7 @@
#else /* !MMCCAM */
if (sc->rtsx_mmc_dev == NULL) {
#endif /* MMCCAM */
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "Card inserted\n");
sc->rtsx_read_count = sc->rtsx_write_count = 0;
@@ -682,10 +688,10 @@
#else /* !MMCCAM */
if (sc->rtsx_mmc_dev != NULL) {
#endif /* MMCCAM */
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "Card removed\n");
- if (sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n",
sc->rtsx_read_count, sc->rtsx_write_count);
#ifdef MMCCAM
@@ -715,7 +721,6 @@
static int
rtsx_init(struct rtsx_softc *sc)
{
- bool rtsx_init_debug = false;
uint8_t version;
uint8_t val;
int error;
@@ -781,10 +786,10 @@
if (!(reg & 0x80)) {
sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F;
sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07;
- } else if (bootverbose || rtsx_init_debug) {
+ } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
break;
@@ -799,10 +804,10 @@
sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
if (reg & 0x4000)
sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
- } else if (bootverbose || rtsx_init_debug) {
+ } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev,
"card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n",
sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
@@ -816,15 +821,16 @@
sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03);
- } else if (bootverbose || rtsx_init_debug) {
+ } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
break;
case RTSX_RTS525A:
case RTSX_RTS5249:
+ case RTSX_RTS5260:
sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
if ((reg & 0x1000000)) {
@@ -834,10 +840,10 @@
sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
if (reg & 0x4000)
sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
- } else if (bootverbose || rtsx_init_debug) {
+ } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev,
"card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n",
sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
@@ -853,10 +859,10 @@
sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6;
reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1);
sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07;
- } else if (bootverbose || rtsx_init_debug) {
+ } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1);
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev,
"card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
@@ -867,17 +873,17 @@
reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
if (!(reg & 0x1000000)) {
sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03);
- } else if (bootverbose || rtsx_init_debug) {
+ } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev,
"card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
break;
}
- if (bootverbose || rtsx_init_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags);
/* Enable interrupts. */
@@ -1199,6 +1205,27 @@
else
RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
break;
+ case RTSX_RTS5260:
+ /* Set mcu_cnt to 7 to ensure data can be sampled properly. */
+ RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07);
+ RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D);
+ /* force no MDIO*/
+ RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE);
+ /*Modify SDVCC Tune Default Parameters!*/
+ RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
+ RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL);
+ RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE);
+ /* Rest L1SUB Config */
+ RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF);
+ RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN);
+ RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN);
+ RTSX_BITOP(sc, RTSX_RB_FLUSH, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE);
+ if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
+ RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
+ else
+ RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
+ RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE);
+ break;
case RTSX_RTL8402:
case RTSX_RTL8411:
RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
@@ -1273,6 +1300,22 @@
return (0);
}
+static int
+rtsx_rts5260_fill_driving(struct rtsx_softc *sc)
+{
+ u_char driving_3v3[4][3] = {
+ {0x11, 0x11, 0x11},
+ {0x22, 0x22, 0x22},
+ {0x55, 0x55, 0x55},
+ {0x33, 0x33, 0x33},
+ };
+ RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
+ RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
+ RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
+
+ return (0);
+}
+
static int
rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val)
{
@@ -1396,7 +1439,7 @@
static int
rtsx_bus_power_off(struct rtsx_softc *sc)
{
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n");
/* Disable SD clock. */
@@ -1419,6 +1462,10 @@
RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA);
RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK);
break;
+ case RTSX_RTS5260:
+ RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF);
+ RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF);
+ break;
case RTSX_RTL8402:
case RTSX_RTL8411:
case RTSX_RTL8411B:
@@ -1455,6 +1502,7 @@
break;
case RTSX_RTS525A:
case RTSX_RTS5249:
+ case RTSX_RTS5260:
RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
@@ -1491,7 +1539,7 @@
static int
rtsx_bus_power_on(struct rtsx_softc *sc)
{
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n");
/* Select SD card. */
@@ -1522,6 +1570,7 @@
break;
case RTSX_RTS525A:
case RTSX_RTS5249:
+ case RTSX_RTS5260:
RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
@@ -1609,6 +1658,26 @@
RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK,
RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2);
break;
+ case RTSX_RTS5260:
+ RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
+ RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
+ RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON);
+ RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON);
+
+ DELAY(20000);
+
+ /* Initialize SD_CFG1 register */
+ RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE);
+ RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE);
+ RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff);
+ RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_MS_STOP | RTSX_SD_CLR_ERR,
+ RTSX_MS_STOP | RTSX_SD_CLR_ERR);
+ /* Reset SD_CFG3 register */
+ RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN);
+ RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG,
+ RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1);
+ RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE);
+ break;
case RTSX_RTL8402:
case RTSX_RTL8411:
case RTSX_RTL8411B:
@@ -1661,7 +1730,7 @@
}
RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width);
- if (bootverbose || sc->rtsx_debug) {
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
char *busw[] = {
"1 bit",
"4 bits",
@@ -1680,7 +1749,7 @@
sc->rtsx_ios_timing = timing;
}
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing);
switch (timing) {
@@ -1734,7 +1803,7 @@
uint8_t clk_divider, n, div, mcu;
int error = 0;
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq);
if (freq == RTSX_SDCLK_OFF) {
@@ -1821,7 +1890,7 @@
static int
rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu)
{
- if (bootverbose || sc->rtsx_debug) {
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n",
(sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth);
device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n",
@@ -1851,7 +1920,7 @@
static void
rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point)
{
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point);
rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
@@ -1865,7 +1934,7 @@
static void
rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point)
{
- if (bootverbose || sc->rtsx_debug == 2)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING)
device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point);
rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
@@ -1932,7 +2001,7 @@
error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd);
if (error) {
- if (bootverbose || sc->rtsx_debug == 2)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING)
device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error);
rtsx_sd_wait_data_idle(sc);
rtsx_clear_error(sc);
@@ -2001,7 +2070,7 @@
final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX;
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev,
"rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n",
phase_map, start_final, len_final, final_phase);
@@ -2154,7 +2223,7 @@
static void
rtsx_send_cmd(struct rtsx_softc *sc)
{
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n");
sc->rtsx_intr_status = 0;
@@ -2181,6 +2250,15 @@
/* Stop DMA transfer. */
WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
+ switch (sc->rtsx_device_id) {
+ case RTSX_RTS5260:
+ rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0,
+ RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST,
+ RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST);
+ rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
+ break;
+ }
+
rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
@@ -2240,7 +2318,7 @@
uint8_t rsp_type;
uint16_t reg;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode);
/* Convert response type. */
@@ -2321,7 +2399,7 @@
if (ISSET(cmd->flags, MMC_RSP_PRESENT)) {
uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem);
- if (bootverbose) {
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) {
device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]);
}
@@ -2350,7 +2428,7 @@
((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16);
}
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n",
cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
@@ -2373,7 +2451,7 @@
read = ISSET(cmd->data->flags, MMC_DATA_READ);
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n",
read ? "Read" : "Write",
(unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len);
@@ -2491,7 +2569,7 @@
/* Run the command queue. */
rtsx_send_cmd(sc);
} else {
- if (bootverbose && cmd->opcode == ACMD_SEND_SCR) {
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) {
uint8_t *ptr = cmd->data->data;
device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
ptr[0], ptr[1], ptr[2], ptr[3],
@@ -2643,7 +2721,7 @@
cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
RTSX_MAX_DATA_BLKLEN : cmd->data->len;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",
read ? "Read" : "Write",
(unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len);
@@ -2679,7 +2757,7 @@
cmd = sc->rtsx_req->cmd;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode);
rtsx_set_resp(sc, cmd);
@@ -2792,7 +2870,7 @@
cmd = sc->rtsx_req->cmd;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode);
read = ISSET(cmd->data->flags, MMC_DATA_READ);
@@ -2869,47 +2947,47 @@
if (cts->ios_valid & MMC_CLK) {
ios->clock = new_ios->clock;
sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock);
}
if (cts->ios_valid & MMC_VDD) {
ios->vdd = new_ios->vdd;
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd);
}
if (cts->ios_valid & MMC_CS) {
ios->chip_select = new_ios->chip_select;
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select);
}
if (cts->ios_valid & MMC_BW) {
ios->bus_width = new_ios->bus_width;
sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width);
}
if (cts->ios_valid & MMC_PM) {
ios->power_mode = new_ios->power_mode;
sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode);
}
if (cts->ios_valid & MMC_BT) {
ios->timing = new_ios->timing;
sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing);
}
if (cts->ios_valid & MMC_BM) {
ios->bus_mode = new_ios->bus_mode;
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode);
}
#if __FreeBSD_version >= 1300000
if (cts->ios_valid & MMC_VCCQ) {
ios->vccq = new_ios->vccq;
sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq);
}
#endif /* __FreeBSD_version >= 1300000 */
@@ -3002,7 +3080,7 @@
return (EINVAL);
}
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(bus, "Read ivar #%d, value %#x / #%d\n",
which, *(int *)result, *(int *)result);
@@ -3014,11 +3092,11 @@
{
struct rtsx_softc *sc;
- if (bootverbose)
+ sc = device_get_softc(bus);
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(bus, "Write ivar #%d, value %#x / #%d\n",
which, (int)value, (int)value);
- sc = device_get_softc(bus);
switch (which) {
case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */
sc->rtsx_host.ios.bus_mode = value;
@@ -3080,7 +3158,7 @@
sc = device_get_softc(bus);
ios = &sc->rtsx_host.ios;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(bus, "rtsx_mmcbr_update_ios()\n");
/* if MMCBR_IVAR_BUS_WIDTH updated. */
@@ -3196,6 +3274,12 @@
if ((error = rtsx_rts5249_fill_driving(sc)))
return (error);
break;
+ case RTSX_RTS5260:
+ RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
+ RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33);
+ if ((error = rtsx_rts5260_fill_driving(sc)))
+ return (error);
+ break;
case RTSX_RTL8402:
RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
RTSX_BITOP(sc, RTSX_LDO_CTL,
@@ -3213,7 +3297,7 @@
DELAY(300);
}
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD))
device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);
return (0);
@@ -3234,7 +3318,7 @@
sc = device_get_softc(bus);
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n",
(hs400) ? "true" : "false");
@@ -3274,24 +3358,18 @@
phase_map = 0xffffffff;
for (i = 0; i < RTSX_RX_TUNING_CNT; i++) {
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING))
device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n",
i, raw_phase_map[i]);
phase_map &= raw_phase_map[i];
}
- if (bootverbose || sc->rtsx_debug)
+ if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map);
if (phase_map) {
final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map);
if (final_phase != 0xff) {
- if (sc->rtsx_debug == 1) {
- sc->rtsx_debug = 2;
- rtsx_sd_change_rx_phase(sc, final_phase);
- sc->rtsx_debug = 1;
- } else {
- rtsx_sd_change_rx_phase(sc, final_phase);
- }
+ rtsx_sd_change_rx_phase(sc, final_phase);
}
}
@@ -3307,7 +3385,7 @@
sc = device_get_softc(bus);
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n");
return (0);
@@ -3336,7 +3414,7 @@
sc->rtsx_intr_trans_ok = NULL;
sc->rtsx_intr_trans_ko = rtsx_req_done;
- if (bootverbose)
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n",
cmd->opcode, cmd->arg, cmd->flags,
cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
@@ -3406,10 +3484,10 @@
{
struct rtsx_softc *sc;
- if (bootverbose)
+ sc = device_get_softc(bus);
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(bus, "rtsx_mmcbr_acquire_host()\n");
- sc = device_get_softc(bus);
RTSX_LOCK(sc);
while (sc->rtsx_bus_busy)
msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0);
@@ -3424,10 +3502,10 @@
{
struct rtsx_softc *sc;
- if (bootverbose)
+ sc = device_get_softc(bus);
+ if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
device_printf(bus, "rtsx_mmcbr_release_host()\n");
- sc = device_get_softc(bus);
RTSX_LOCK(sc);
sc->rtsx_bus_busy--;
wakeup(&sc->rtsx_bus_busy);
@@ -3502,7 +3580,7 @@
sc->rtsx_read_only = 0;
sc->rtsx_inversion = 0;
sc->rtsx_force_timing = 0;
- sc->rtsx_debug = 0;
+ sc->rtsx_debug_mask = 0;
sc->rtsx_read_count = 0;
sc->rtsx_write_count = 0;
@@ -3534,14 +3612,14 @@
&sc->rtsx_inversion, 0, "Inversion of card detection and read only status");
SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW,
&sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50");
- SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug", CTLFLAG_RWTUN,
- &sc->rtsx_debug, 0, "Debugging flag");
+ SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN,
+ &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)");
SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS,
&sc->rtsx_read_count, 0, "Count of read operations");
SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS,
&sc->rtsx_write_count, 0, "Count of write operations");
- if (bootverbose || sc->rtsx_debug)
+ if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion);
/* Allocate IRQ. */
Index: sys/dev/rtsx/rtsxreg.h
===================================================================
--- sys/dev/rtsx/rtsxreg.h
+++ sys/dev/rtsx/rtsxreg.h
@@ -356,6 +356,7 @@
#define RTSX_SD_RSP_TYPE_R7 0x01
#define RTSX_SD_CFG3 0xFDA2
+#define RTSX_SD30_CLK_END_EN 0x10
#define RTSX_SD_RSP_80CLK_TIMEOUT_EN 0x01
#define RTSX_SD_STAT1 0xFDA3
@@ -477,6 +478,14 @@
#define RTSX_SD_DATA_STATE 0xFDB6
#define RTSX_SD_DATA_IDLE 0x80
+#define RTSX_REG_SD_STOP_SDCLK_CFG 0xFDB8
+#define RTSX_SD30_CLK_STOP_CFG_EN 0x04
+#define RTSX_SD30_CLK_STOP_CFG0 0x01
+#define RTSX_SD30_CLK_STOP_CFG1 0x02
+
+#define RTSX_REG_PRE_RW_MODE 0xFD70
+#define RTSX_EN_INFINITE_MODE 0x01
+
/* ping-pong buffer 2 */
#define RTSX_PPBUF_BASE2 0xFA00
#define RTSX_PPBUF_SIZE 256
@@ -519,6 +528,8 @@
#define RTSX_RBCTL 0xFE34
#define RTSX_RB_FLUSH 0x80
+#define RTSX_U_AUTO_DMA_EN_MASK 0x20
+#define RTSX_U_AUTO_DMA_DISABLE 0x00
#define RTSX_CFGADDR0 0xFE35
#define RTSX_CFGADDR1 0xFE36
@@ -685,6 +696,8 @@
#define RTSX_FORCE_ASPM_NO_ASPM 0x00
#define RTSX_PM_CLK_FORCE_CTL 0xFE58
+#define RTSX_CLK_PM_EN 0x01
+
#define RTSX_FUNC_FORCE_CTL 0xFE59
#define RTSX_FUNC_FORCE_UPME_XMT_DBG 0x02
@@ -701,6 +714,10 @@
#define RTSX_PM_EVENT_DEBUG 0xFE71
#define RTSX_PME_DEBUG_0 0x08
+#define RTSX_L1SUB_CONFIG1 0xFE8D
+#define RTSX_AUX_CLK_ACTIVE_SEL_MASK 0x01
+#define RTSX_MAC_CKSW_DONE 0x00
+
#define RTSX_L1SUB_CONFIG2 0xFE8E
#define RTSX_L1SUB_AUTO_CFG 0x02
@@ -708,6 +725,10 @@
#define RTSX_DUMMY_REG 0xFE90
+#define RTSX_RTS5260_DMA_RST_CTL_0 0xFEBF
+#define RTSX_RTS5260_DMA_RST 0x80
+#define RTSX_RTS5260_ADMA3_RST 0x40
+
#define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */
#define RTSX_PETXCFG_CLKREQ_PIN 0x08
@@ -724,6 +745,10 @@
#define RTSX_OOBS_AUTOK_DIS 0x80
#define RTSX_OOBS_VAL_MASK 0x1F
+#define RTSX_LDO_DV18_CFG 0xFF70
+#define RTSX_DV331812_MASK 0x70
+#define RTSX_DV331812_33 0x70
+
#define RTSX_LDO_CONFIG2 0xFF71
#define RTSX_LDO_D3318_MASK 0x07
#define RTSX_LDO_D3318_33V 0x07
@@ -735,6 +760,8 @@
#define RTSX_LDO_VCC_CFG0 0xFF72
#define RTSX_LDO_VCC_LMTVTH_MASK 0x30
#define RTSX_LDO_VCC_LMTVTH_2A 0x10
+#define RTSX_RTS5260_DVCC_TUNE_MASK 0x70
+#define RTSX_RTS5260_DVCC_33 0x70
#define RTSX_LDO_VCC_CFG1 0xFF73
#define RTSX_LDO_VCC_REF_TUNE_MASK 0x30
@@ -743,6 +770,11 @@
#define RTSX_LDO_VCC_1V8 0x04
#define RTSX_LDO_VCC_3V3 0x07
#define RTSX_LDO_VCC_LMT_EN 0x08
+/*RTS5260*/
+#define RTSX_LDO_POW_SDVDD1_MASK 0x08
+#define RTSX_LDO_POW_SDVDD1_ON 0x08
+#define RTSX_LDO_POW_SDVDD1_OFF 0x00
+
#define RTSX_LDO_VIO_CFG 0xFF75
#define RTSX_LDO_VIO_TUNE_MASK 0x07
@@ -769,6 +801,9 @@
#define RTSX_IC_VERSION_C 0x02
#define RTSX_IC_VERSION_D 0x03
+#define RTSX_RTS5260_AUTOLOAD_CFG4 0xFF7F
+#define RTSX_RTS5260_MIMO_DISABLE 0x8A
+
#define RTSX_PCR_SETTING_REG1 0x724
#define RTSX_PCR_SETTING_REG2 0x814
#define RTSX_PCR_SETTING_REG3 0x747

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