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Index: sys/arm/arm/locore-v6.S
===================================================================
--- sys/arm/arm/locore-v6.S
+++ sys/arm/arm/locore-v6.S
@@ -76,6 +76,25 @@
mov r10, r2 /* Save meta data */
mov r11, r3 /* Future expansion */
+#if __ARM_ARCH >= 7
+ /* Leave HYP mode */
+ mrs r0, cpsr
+ and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */
+ teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */
+ bne no_hyp
+ adr lr, no_hyp
+
+ /* We're in HYP, set SVC32 as target mode */
+ mrs r0, spsr
+ bic r0, r0, #(PSR_MODE)
+ orr r0, r0, #(PSR_SVC32_MODE)
+ msr spsr, r0
+
+ MSR_ELR_HYP(14) /* msr elr_hyp, lr */
+ ERET /* eret */
+no_hyp:
+#endif
+
/*
* Check whether data cache is enabled. If it is, then we know
* current tags are valid (not power-on garbage values) and there
@@ -398,6 +417,26 @@
#if defined(SMP)
ASENTRY_NP(mpentry)
+
+#if __ARM_ARCH >= 7
+ /* Leave HYP mode */
+ mrs r0, cpsr
+ and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */
+ teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */
+ bne no_hyp_mp
+ adr lr, no_hyp_mp
+
+ /* We're in HYP, set SVC32 as target mode */
+ mrs r0, spsr
+ bic r0, r0, #(PSR_MODE)
+ orr r0, r0, #(PSR_SVC32_MODE)
+ msr spsr, r0
+
+ MSR_ELR_HYP(14) /* msr elr_hyp, lr */
+ ERET /* eret */
+no_hyp_mp:
+#endif
+
/* Make sure interrupts are disabled. */
cpsid ifa
Index: sys/arm/include/asm.h
===================================================================
--- sys/arm/include/asm.h
+++ sys/arm/include/asm.h
@@ -228,6 +228,8 @@
#define DSB dsb
#define DMB dmb
#define WFI wfi
+#define MSR_ELR_HYP(regnum) .word (0xe12ef300 | regnum)
+#define ERET .word 0xe160006e
#elif __ARM_ARCH == 6
#define ISB mcr CP15_CP15ISB
#define DSB mcr CP15_CP15DSB

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