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Index: sys/arm/conf/ARMADA38X
===================================================================
--- sys/arm/conf/ARMADA38X
+++ sys/arm/conf/ARMADA38X
@@ -93,5 +93,7 @@
# L2 Cache
device pl310
+options PLATFORM
+
# FDT
options FDT
Index: sys/arm/conf/ARMADAXP
===================================================================
--- sys/arm/conf/ARMADAXP
+++ sys/arm/conf/ARMADAXP
@@ -84,9 +84,16 @@
#PCI/PCIE
device pci
+# Timers
+device mpcore_timer
+
# Flattened Device Tree
options FDT # Configure using FDT/DTB data
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=db78460.dts
options INTRNG
+
+# ArmadaXP does not use pl310, add to satisfy compiler
+device pl310
+options PLATFORM
Index: sys/arm/mv/armada38x/armada38x_mp.c
===================================================================
--- sys/arm/mv/armada38x/armada38x_mp.c
+++ sys/arm/mv/armada38x/armada38x_mp.c
@@ -43,9 +43,13 @@
#include "pmsu.h"
-int cpu_reset_deassert(void);
+#include <machine/platformvar.h>
-int
+static int cpu_reset_deassert(void);
+void mv_a38x_platform_mp_setmaxid(platform_t plate);
+void mv_a38x_platform_mp_start_ap(platform_t plate);
+
+static int
cpu_reset_deassert(void)
{
bus_space_handle_t vaddr;
@@ -122,7 +126,7 @@
}
void
-platform_mp_setmaxid(void)
+mv_a38x_platform_mp_setmaxid(platform_t plate)
{
/* Armada38x family supports maximum 2 cores */
@@ -131,7 +135,7 @@
}
void
-platform_mp_start_ap(void)
+mv_a38x_platform_mp_start_ap(platform_t plate)
{
int rv;
Index: sys/arm/mv/armada38x/armada38x_pl310.h
===================================================================
--- /dev/null
+++ sys/arm/mv/armada38x/armada38x_pl310.h
@@ -0,0 +1,35 @@
+/*-
+ * Copyright (c) 2017 Semihalf.
+ * Copyright (c) 2017 Stormshield.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ARMADA38X_PL310_H
+#define ARMADA38X_PL310_H
+#include <machine/platformvar.h>
+
+void mv_a38x_platform_pl310_init(platform_t plat, struct pl310_softc *sc);
+void mv_a38x_platform_pl310_write_ctrl(platform_t plat, struct pl310_softc *sc, uint32_t val);
+void mv_a38x_platform_pl310_write_debug(platform_t plat, struct pl310_softc *sc, uint32_t val);
+
+#endif
Index: sys/arm/mv/armada38x/armada38x_pl310.c
===================================================================
--- sys/arm/mv/armada38x/armada38x_pl310.c
+++ sys/arm/mv/armada38x/armada38x_pl310.c
@@ -41,8 +41,14 @@
#include <machine/bus.h>
#include <machine/pl310.h>
+#include "armada38x_pl310.h"
+
+#include <machine/platform.h>
+#include <machine/platformvar.h>
+#include "platform_pl310_if.h"
+
void
-platform_pl310_init(struct pl310_softc *sc)
+mv_a38x_platform_pl310_init(platform_t plat, struct pl310_softc *sc)
{
uint32_t reg;
@@ -63,14 +69,14 @@
}
void
-platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val)
+mv_a38x_platform_pl310_write_ctrl(platform_t plat, struct pl310_softc *sc, uint32_t val)
{
pl310_write4(sc, PL310_CTRL, val);
}
void
-platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val)
+mv_a38x_platform_pl310_write_debug(platform_t plat, struct pl310_softc *sc, uint32_t val)
{
pl310_write4(sc, PL310_DEBUG_CTRL, val);
Index: sys/arm/mv/armada38x/std.armada38x
===================================================================
--- sys/arm/mv/armada38x/std.armada38x
+++ sys/arm/mv/armada38x/std.armada38x
@@ -1,6 +1,4 @@
# $FreeBSD$
-files "../mv/armada38x/files.armada38x"
-files "../mv/files.mv"
files "../mv/files.arm7"
cpu CPU_CORTEXA
machine arm armv7
Index: sys/arm/mv/armadaxp/armadaxp_mp.c
===================================================================
--- sys/arm/mv/armadaxp/armadaxp_mp.c
+++ sys/arm/mv/armadaxp/armadaxp_mp.c
@@ -49,6 +49,8 @@
#include <arm/mv/mvwin.h>
+#include <machine/platformvar.h>
+
#define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700)
#define CPU_DIVCLK_CTRL0 0x00
#define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08
@@ -66,6 +68,9 @@
void armadaxp_init_coher_fabric(void);
int platform_get_ncpus(void);
+void mv_axp_platform_mp_setmaxid(platform_t plat);
+void mv_axp_platform_mp_start_ap(platform_t plat);
+
/* Coherency Fabric registers */
static uint32_t
read_cpu_clkdiv(uint32_t reg)
@@ -82,7 +87,7 @@
}
void
-platform_mp_setmaxid(void)
+mv_axp_platform_mp_setmaxid(platform_t plat)
{
mp_ncpus = platform_get_ncpus();
@@ -94,7 +99,7 @@
extern vm_offset_t mptramp_pmu_boot;
void
-platform_mp_start_ap(void)
+mv_axp_platform_mp_start_ap(platform_t plat)
{
uint32_t reg, *src, *dst, cpu_num, div_val, cputype;
vm_offset_t pmu_boot_off;
Index: sys/arm/mv/armadaxp/std.mv78x60
===================================================================
--- sys/arm/mv/armadaxp/std.mv78x60
+++ sys/arm/mv/armadaxp/std.mv78x60
@@ -2,4 +2,3 @@
include "../mv/std-pj4b.mv"
include "../mv/armadaxp/std.armadaxp"
-files "../mv/armadaxp/files.armadaxp"
Index: sys/arm/mv/armv5_machdep.c
===================================================================
--- sys/arm/mv/armv5_machdep.c
+++ sys/arm/mv/armv5_machdep.c
@@ -61,12 +61,7 @@
#include <machine/machdep.h>
#include <machine/platform.h>
-#if __ARM_ARCH < 6
#include <machine/cpu-v4.h>
-#else
-#include <machine/cpu-v6.h>
-#include <machine/pte-v6.h>
-#endif
#include <arm/mv/mvreg.h> /* XXX */
#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */
@@ -76,16 +71,7 @@
#include <dev/ofw/ofw_bus_subr.h>
static int platform_mpp_init(void);
-#if defined(SOC_MV_ARMADAXP)
-void armadaxp_init_coher_fabric(void);
-void armadaxp_l2_init(void);
-#endif
-#if defined(SOC_MV_ARMADA38X)
-int armada38x_win_set_iosync_barrier(void);
-int armada38x_scu_enable(void);
-int armada38x_open_bootrom_win(void);
-int armada38x_mbus_optimization(void);
-#endif
+void cpu_reset(void);
#define MPP_PIN_MAX 68
#define MPP_PIN_CELLS 2
@@ -291,46 +277,8 @@
if (soc_decode_win() != 0)
printf("WARNING: could not re-initialise decode windows! "
"Running with existing settings...\n");
-#if defined(SOC_MV_ARMADAXP)
-#if !defined(SMP)
- /* For SMP case it should be initialized after APs are booted */
- armadaxp_init_coher_fabric();
-#endif
- armadaxp_l2_init();
-#endif
-
-#if defined(SOC_MV_ARMADA38X)
- /* Configure timers' base frequency */
- arm_tmr_change_frequency(get_cpu_freq() / 2);
-
- /*
- * Workaround for Marvell Armada38X family HW issue
- * between Cortex-A9 CPUs and on-chip devices that may
- * cause hang on heavy load.
- * To avoid that, map all registers including PCIe IO
- * as strongly ordered instead of device memory.
- */
- pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO);
-
- /* Set IO Sync Barrier bit for all Mbus devices */
- if (armada38x_win_set_iosync_barrier() != 0)
- printf("WARNING: could not map CPU Subsystem registers\n");
- if (armada38x_mbus_optimization() != 0)
- printf("WARNING: could not enable mbus optimization\n");
- if (armada38x_scu_enable() != 0)
- printf("WARNING: could not enable SCU\n");
-#ifdef SMP
- /* Open window to bootROM memory - needed for SMP */
- if (armada38x_open_bootrom_win() != 0)
- printf("WARNING: could not open window to bootROM\n");
-#endif
-#endif
}
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
-#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2)
-#else
#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)
-#endif
static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
{ 0, 0, 0, }
};
@@ -338,20 +286,19 @@
static int
platform_sram_devmap(struct devmap_entry *map)
{
-#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
phandle_t child, root;
u_long base, size;
/*
* SRAM range.
*/
+ if ((root = OF_finddevice("/")) == 0)
+ return (ENXIO);
+
if ((child = OF_finddevice("/sram")) != 0)
if (ofw_bus_node_is_compatible(child, "mrvl,cesa-sram") ||
ofw_bus_node_is_compatible(child, "mrvl,scratchpad"))
goto moveon;
- if ((root = OF_finddevice("/")) == 0)
- return (ENXIO);
-
if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
(child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
goto out;
@@ -366,7 +313,6 @@
return (0);
out:
-#endif
return (ENOENT);
}
@@ -408,20 +354,10 @@
i = 0;
devmap_register_table(&fdt_devmap[0]);
-#ifdef SOC_MV_ARMADAXP
- vm_paddr_t cur_immr_pa;
+ if ((root = OF_finddevice("/")) == -1)
+ return (ENXIO);
/*
- * Acquire SoC registers' base passed by u-boot and fill devmap
- * accordingly. DTB is going to be modified basing on this data
- * later.
- */
- __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
- cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
- if (cur_immr_pa != 0)
- fdt_immr_pa = cur_immr_pa;
-#endif
- /*
* IMMR range.
*/
fdt_devmap[i].pd_va = fdt_immr_va;
@@ -440,8 +376,6 @@
* PCI range(s).
* PCI range(s) and localbus.
*/
- if ((root = OF_finddevice("/")) == -1)
- return (ENXIO);
for (child = OF_child(root); child != 0; child = OF_peer(child)) {
if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
/*
@@ -485,7 +419,6 @@
return (0);
}
-#if __ARM_ARCH < 6
struct arm32_dma_range *
bus_dma_get_range(void)
{
@@ -499,9 +432,16 @@
return (0);
}
-#endif
-#if defined(CPU_MV_PJ4B)
+void
+cpu_reset(void)
+{
+
+ write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
+ write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
+ while(1);
+}
+
#ifdef DDB
#include <ddb/ddb.h>
@@ -557,5 +497,3 @@
db_printf("show vtop <virt_addr>\n");
}
#endif /* DDB */
-#endif /* CPU_MV_PJ4B */
-
Index: sys/arm/mv/armv7_machdep.c
===================================================================
--- /dev/null
+++ sys/arm/mv/armv7_machdep.c
@@ -0,0 +1,478 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2017 Semihalf.
+ * Copyright (c) 1994-1998 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Brini.
+ * 4. The name of the company nor the name of the author may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
+ */
+
+#include "opt_ddb.h"
+#include "opt_platform.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/devmap.h>
+#include <sys/kernel.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <arm/arm/mpcore_timervar.h>
+#include <arm/arm/nexusvar.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+#include <machine/machdep.h>
+#include <machine/platform.h>
+#include <machine/platformvar.h>
+#include <machine/pte-v6.h>
+
+#include <arm/mv/mvreg.h>
+#include <arm/mv/mvvar.h>
+#include <arm/mv/mvwin.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include "opt_platform.h"
+#include "platform_if.h"
+
+#include "platform_pl310_if.h"
+#include "armada38x/armada38x_pl310.h"
+
+static int platform_mpp_init(void);
+int armada38x_win_set_iosync_barrier(void);
+int armada38x_scu_enable(void);
+int armada38x_open_bootrom_win(void);
+int armada38x_mbus_optimization(void);
+
+vm_offset_t mv_platform_lastaddr(platform_t plate);
+int mv_platform_probe_and_attach(platform_t plate);
+void mv_platform_gpio_init(platform_t plate);
+void mv_cpu_reset(platform_t plat);
+
+void mv_a38x_platform_late_init(platform_t plate);
+int mv_a38x_platform_devmap_init(platform_t plate);
+void mv_axp_platform_late_init(platform_t plate);
+int mv_axp_platform_devmap_init(platform_t plate);
+
+void armadaxp_init_coher_fabric(void);
+void armadaxp_l2_init(void);
+
+#ifdef SMP
+void mv_a38x_platform_mp_setmaxid(platform_t plate);
+void mv_a38x_platform_mp_start_ap(platform_t plate);
+void mv_axp_platform_mp_setmaxid(platform_t plate);
+void mv_axp_platform_mp_start_ap(platform_t plate);
+#endif
+
+#define MPP_PIN_MAX 68
+#define MPP_PIN_CELLS 2
+#define MPP_PINS_PER_REG 8
+#define MPP_SEL(pin,func) (((func) & 0xf) << \
+ (((pin) % MPP_PINS_PER_REG) * 4))
+
+static void
+mv_busdma_tag_init(void *arg __unused)
+{
+ phandle_t node;
+ bus_dma_tag_t dmat;
+
+ /*
+ * If this platform has coherent DMA, create the parent DMA tag to pass
+ * down the coherent flag to all busses and devices on the platform,
+ * otherwise return without doing anything. By default create tag
+ * for all A38x-based platforms only.
+ */
+ if ((node = OF_finddevice("/")) == -1){
+ printf("no tree\n");
+ return;
+ }
+
+ if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0)
+ return;
+
+ bus_dma_tag_create(NULL, /* No parent tag */
+ 1, 0, /* alignment, bounds */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ BUS_SPACE_MAXSIZE, /* maxsize */
+ BUS_SPACE_UNRESTRICTED, /* nsegments */
+ BUS_SPACE_MAXSIZE, /* maxsegsize */
+ BUS_DMA_COHERENT, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &dmat);
+
+ nexus_set_dma_tag(dmat);
+
+}
+SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL);
+
+static int
+platform_mpp_init(void)
+{
+ pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
+ int mpp[MPP_PIN_MAX];
+ uint32_t ctrl_val, ctrl_offset;
+ pcell_t reg[4];
+ u_long start, size;
+ phandle_t node;
+ pcell_t pin_cells, *pinmap_ptr, pin_count;
+ ssize_t len;
+ int par_addr_cells, par_size_cells;
+ int tuple_size, tuples, rv, pins, i, j;
+ int mpp_pin, mpp_function;
+
+ /*
+ * Try to access the MPP node directly i.e. through /aliases/mpp.
+ */
+ if ((node = OF_finddevice("mpp")) != -1)
+ if (ofw_bus_node_is_compatible(node, "mrvl,mpp"))
+ goto moveon;
+ /*
+ * Find the node the long way.
+ */
+ if ((node = OF_finddevice("/")) == -1)
+ return (ENXIO);
+
+ if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
+ return (ENXIO);
+
+ if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
+ /*
+ * No MPP node. Fall back to how MPP got set by the
+ * first-stage loader and try to continue booting.
+ */
+ return (0);
+moveon:
+ /*
+ * Process 'reg' prop.
+ */
+ if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
+ &par_size_cells)) != 0)
+ return(ENXIO);
+
+ tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
+ len = OF_getprop(node, "reg", reg, sizeof(reg));
+ tuples = len / tuple_size;
+ if (tuple_size <= 0)
+ return (EINVAL);
+
+ rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
+ &start, &size);
+ if (rv != 0)
+ return (rv);
+ start += fdt_immr_va;
+
+ /*
+ * Process 'pin-count' and 'pin-map' props.
+ */
+ if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
+ return (ENXIO);
+ if (pin_count > MPP_PIN_MAX)
+ return (ERANGE);
+
+ if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
+ pin_cells = MPP_PIN_CELLS;
+ if (pin_cells > MPP_PIN_CELLS)
+ return (ERANGE);
+ tuple_size = sizeof(pcell_t) * pin_cells;
+
+ bzero(pinmap, sizeof(pinmap));
+ len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap));
+ if (len <= 0)
+ return (ERANGE);
+ if (len % tuple_size)
+ return (ERANGE);
+ pins = len / tuple_size;
+ if (pins > pin_count)
+ return (ERANGE);
+ /*
+ * Fill out a "mpp[pin] => function" table. All pins unspecified in
+ * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
+ */
+ bzero(mpp, sizeof(mpp));
+ pinmap_ptr = pinmap;
+ for (i = 0; i < pins; i++) {
+ mpp_pin = *pinmap_ptr;
+ mpp_function = *(pinmap_ptr + 1);
+ mpp[mpp_pin] = mpp_function;
+ pinmap_ptr += pin_cells;
+ }
+
+ /*
+ * Prepare and program MPP control register values.
+ */
+ ctrl_offset = 0;
+ for (i = 0; i < pin_count;) {
+ ctrl_val = 0;
+
+ for (j = 0; j < MPP_PINS_PER_REG; j++) {
+ if (i + j == pin_count - 1)
+ break;
+ ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
+ }
+ i += MPP_PINS_PER_REG;
+ bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
+ ctrl_val);
+
+ ctrl_offset += 4;
+ }
+
+ return (0);
+}
+
+vm_offset_t
+mv_platform_lastaddr(platform_t plat)
+{
+
+ return (fdt_immr_va);
+}
+
+int
+mv_platform_probe_and_attach(platform_t plate)
+{
+
+ if (fdt_immr_addr(MV_BASE) != 0)
+ while (1);
+ return (0);
+}
+
+void
+mv_platform_gpio_init(platform_t plate)
+{
+
+ /*
+ * Re-initialise MPP. It is important to call this prior to using
+ * console as the physical connection can be routed via MPP.
+ */
+ if (platform_mpp_init() != 0)
+ while (1);
+}
+
+void
+mv_a38x_platform_late_init(platform_t plate)
+{
+
+ /*
+ * Re-initialise decode windows
+ */
+ if (mv_check_soc_family() == MV_SOC_UNSUPPORTED)
+ panic("Unsupported SoC family\n");
+
+ if (soc_decode_win() != 0)
+ printf("WARNING: could not re-initialise decode windows! "
+ "Running with existing settings...\n");
+
+ /* Configure timers' base frequency */
+ arm_tmr_change_frequency(get_cpu_freq() / 2);
+
+ /*
+ * Workaround for Marvell Armada38X family HW issue
+ * between Cortex-A9 CPUs and on-chip devices that may
+ * cause hang on heavy load.
+ * To avoid that, map all registers including PCIe IO
+ * as strongly ordered instead of device memory.
+ */
+ pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO);
+
+ /* Set IO Sync Barrier bit for all Mbus devices */
+ if (armada38x_win_set_iosync_barrier() != 0)
+ printf("WARNING: could not map CPU Subsystem registers\n");
+ if (armada38x_mbus_optimization() != 0)
+ printf("WARNING: could not enable mbus optimization\n");
+ if (armada38x_scu_enable() != 0)
+ printf("WARNING: could not enable SCU\n");
+#ifdef SMP
+ /* Open window to bootROM memory - needed for SMP */
+ if (armada38x_open_bootrom_win() != 0)
+ printf("WARNING: could not open window to bootROM\n");
+#endif
+}
+
+void
+mv_axp_platform_late_init(platform_t plate)
+{
+ phandle_t node;
+ /*
+ * Re-initialise decode windows
+ */
+ if (soc_decode_win() != 0)
+ printf("WARNING: could not re-initialise decode windows! "
+ "Running with existing settings...\n");
+ if ((node = OF_finddevice("/")) == -1)
+ return;
+
+#if !defined(SMP)
+ /* For SMP case it should be initialized after APs are booted */
+ armadaxp_init_coher_fabric();
+#endif
+ armadaxp_l2_init();
+}
+
+#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2)
+static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
+ { 0, 0, 0, }
+};
+
+static int
+platform_sram_devmap(struct devmap_entry *map)
+{
+
+ return (ENOENT);
+}
+
+/*
+ * Construct devmap table with DT-derived config data.
+ */
+int
+mv_a38x_platform_devmap_init(platform_t plat)
+{
+ phandle_t root, child;
+ int i;
+
+ i = 0;
+ devmap_register_table(&fdt_devmap[0]);
+
+ if ((root = OF_finddevice("/")) == -1)
+ return (ENXIO);
+
+ /*
+ * IMMR range.
+ */
+ fdt_devmap[i].pd_va = fdt_immr_va;
+ fdt_devmap[i].pd_pa = fdt_immr_pa;
+ fdt_devmap[i].pd_size = fdt_immr_size;
+ i++;
+
+ /*
+ * SRAM range.
+ */
+ if (i < FDT_DEVMAP_MAX)
+ if (platform_sram_devmap(&fdt_devmap[i]) == 0)
+ i++;
+
+ /*
+ * PCI range(s).
+ * PCI range(s) and localbus.
+ */
+ for (child = OF_child(root); child != 0; child = OF_peer(child)) {
+ if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
+ /*
+ * Check space: each PCI node will consume 2 devmap
+ * entries.
+ */
+ if (i + 1 >= FDT_DEVMAP_MAX)
+ return (ENOMEM);
+
+ if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
+ MV_PCI_VA_MEM_BASE) != 0)
+ return (ENXIO);
+ i += 2;
+ }
+ }
+
+ return (0);
+}
+
+int
+mv_axp_platform_devmap_init(platform_t plate)
+{
+ vm_paddr_t cur_immr_pa;
+
+ /*
+ * Acquire SoC registers' base passed by u-boot and fill devmap
+ * accordingly. DTB is going to be modified basing on this data
+ * later.
+ */
+ __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
+ cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
+ if (cur_immr_pa != 0)
+ fdt_immr_pa = cur_immr_pa;
+
+ mv_a38x_platform_devmap_init(plate);
+
+ return (0);
+}
+
+void
+mv_cpu_reset(platform_t plat)
+{
+
+ write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
+ write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
+}
+
+static platform_method_t mv_a38x_methods[] = {
+ PLATFORMMETHOD(platform_devmap_init, mv_a38x_platform_devmap_init),
+ PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset),
+ PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr),
+ PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach),
+ PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init),
+ PLATFORMMETHOD(platform_late_init, mv_a38x_platform_late_init),
+ PLATFORMMETHOD(platform_pl310_init, mv_a38x_platform_pl310_init),
+ PLATFORMMETHOD(platform_pl310_write_ctrl, mv_a38x_platform_pl310_write_ctrl),
+ PLATFORMMETHOD(platform_pl310_write_debug, mv_a38x_platform_pl310_write_debug),
+#ifdef SMP
+ PLATFORMMETHOD(platform_mp_start_ap, mv_a38x_platform_mp_start_ap),
+ PLATFORMMETHOD(platform_mp_setmaxid, mv_a38x_platform_mp_setmaxid),
+#endif
+
+ PLATFORMMETHOD_END,
+};
+FDT_PLATFORM_DEF(mv_a38x, "mv_a38x", 0, "marvell,armada380", 100);
+
+static platform_method_t mv_axp_methods[] = {
+ PLATFORMMETHOD(platform_devmap_init, mv_axp_platform_devmap_init),
+ PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset),
+ PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr),
+ PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach),
+ PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init),
+ PLATFORMMETHOD(platform_late_init, mv_axp_platform_late_init),
+#ifdef SMP
+ PLATFORMMETHOD(platform_mp_start_ap, mv_axp_platform_mp_start_ap),
+ PLATFORMMETHOD(platform_mp_setmaxid, mv_axp_platform_mp_setmaxid),
+#endif
+
+ PLATFORMMETHOD_END,
+};
+FDT_PLATFORM_DEF(mv_axp, "mv_axp", 0, "marvell,armadaxp", 100);
+
Index: sys/arm/mv/files.arm7
===================================================================
--- sys/arm/mv/files.arm7
+++ sys/arm/mv/files.arm7
@@ -1,2 +1,38 @@
arm/mv/armada38x/armada38x.c standard
arm/mv/armadaxp/armadaxp.c standard
+
+arm/mv/gpio.c optional gpio
+arm/mv/mv_common.c standard
+arm/mv/mv_localbus.c standard
+arm/mv/armv7_machdep.c standard
+arm/mv/mv_pci_ctrl.c optional pci | fdt
+arm/mv/mv_pci.c optional pci
+arm/mv/mv_ts.c standard
+arm/mv/timer.c standard
+
+arm/mv/mpic.c standard
+arm/mv/armada/thermal.c optional fdt
+arm/mv/armada/wdt.c optional fdt
+arm/mv/armada38x/armada38x_mp.c optional smp
+arm/mv/armada38x/pmsu.c standard
+arm/mv/armada38x/armada38x_rtc.c standard
+arm/mv/armada38x/armada38x_pl310.c optional pl310
+dev/sdhci/sdhci_fdt.c optional sdhci
+
+arm/mv/rtc.c standard
+arm/mv/armadaxp/armadaxp_mp.c optional smp
+arm/mv/armadaxp/mptramp.S optional smp
+dev/cesa/cesa.c optional cesa
+dev/iicbus/twsi/mv_twsi.c optional twsi
+dev/mge/if_mge.c optional mge
+dev/neta/if_mvneta_fdt.c optional neta fdt
+dev/neta/if_mvneta.c optional neta mdio mii
+dev/nand/nfc_mv.c optional nand
+dev/mvs/mvs_soc.c optional mvs
+dev/uart/uart_dev_ns8250.c optional uart
+dev/uart/uart_dev_snps.c optional uart
+dev/usb/controller/ehci_mv.c optional ehci
+dev/usb/controller/xhci_mv.c optional xhci
+dev/ahci/ahci_mv_fdt.c optional ahci
+
+kern/kern_clocksource.c standard
Index: sys/arm/mv/files.mv
===================================================================
--- sys/arm/mv/files.mv
+++ sys/arm/mv/files.mv
@@ -15,7 +15,7 @@
arm/mv/gpio.c optional gpio
arm/mv/mv_common.c standard
arm/mv/mv_localbus.c standard
-arm/mv/mv_machdep.c standard
+arm/mv/armv5_machdep.c standard
arm/mv/mv_pci_ctrl.c optional pci | fdt
arm/mv/mv_pci.c optional pci
arm/mv/mv_ts.c standard
Index: sys/arm/mv/mv_common.c
===================================================================
--- sys/arm/mv/mv_common.c
+++ sys/arm/mv/mv_common.c
@@ -588,20 +588,6 @@
bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
}
-void
-cpu_reset(void)
-{
-
-#if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
- write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
- write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
-#else
- write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
- write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
-#endif
- while (1);
-}
-
uint32_t
cpu_extra_feat(void)
{
Index: sys/arm/mv/std-pj4b.mv
===================================================================
--- sys/arm/mv/std-pj4b.mv
+++ sys/arm/mv/std-pj4b.mv
@@ -1,6 +1,5 @@
# $FreeBSD$
-files "../mv/files.mv"
files "../mv/files.arm7"
cpu CPU_MV_PJ4B
machine arm armv7

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