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diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -665,6 +665,18 @@
/* ID_AA64ISAR1_EL1 */
+static const struct mrs_field_value id_aa64isar1_ls64[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LS64, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_V, "LS64v"),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_ACCDATA, "LS64+ACCDATA"),
+ MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64isar1_xs[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, XS, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
static const struct mrs_field_value id_aa64isar1_i8mm[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
MRS_FIELD_VALUE_END,
@@ -687,6 +699,7 @@
static const struct mrs_field_value id_aa64isar1_bf16[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_BF16_EBF, "EBF16"),
MRS_FIELD_VALUE_END,
};
@@ -820,6 +833,8 @@
};
static const struct mrs_field id_aa64isar1_fields[] = {
+ MRS_FIELD(ID_AA64ISAR1, LS64, false, MRS_EXACT, id_aa64isar1_ls64),
+ MRS_FIELD(ID_AA64ISAR1, XS, false, MRS_EXACT, id_aa64isar1_xs),
MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER,
id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps),
MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh,
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -656,11 +656,11 @@
/* ID_AA64ISAR1_EL1 */
#define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1)
-#define ID_AA64ISAR1_EL1_op0 0x3
-#define ID_AA64ISAR1_EL1_op1 0x0
-#define ID_AA64ISAR1_EL1_CRn 0x0
-#define ID_AA64ISAR1_EL1_CRm 0x6
-#define ID_AA64ISAR1_EL1_op2 0x1
+#define ID_AA64ISAR1_EL1_op0 3
+#define ID_AA64ISAR1_EL1_op1 0
+#define ID_AA64ISAR1_EL1_CRn 0
+#define ID_AA64ISAR1_EL1_CRm 6
+#define ID_AA64ISAR1_EL1_op2 1
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK)
@@ -731,6 +731,7 @@
#define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK)
#define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_DGH_SHIFT 48
#define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK)
@@ -741,6 +742,18 @@
#define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK)
#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
+#define ID_AA64ISAR1_XS_SHIFT 56
+#define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT)
+#define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK)
+#define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT)
+#define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT)
+#define ID_AA64ISAR1_LS64_SHIFT 60
+#define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT)
+#define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK)
+#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT)
+#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT)
+#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT)
+#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT)
/* ID_AA64ISAR2_EL1 */
#define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1)

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