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D18270.id50869.diff
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D18270.id50869.diff
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Index: sys/dev/sfxge/common/ef10_nic.c
===================================================================
--- sys/dev/sfxge/common/ef10_nic.c
+++ sys/dev/sfxge/common/ef10_nic.c
@@ -1799,6 +1799,21 @@
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
goto fail6;
+ /*
+ * Firmware with support for *_FEC capability bits does not
+ * report that the corresponding *_FEC_REQUESTED bits are supported.
+ * Add them here so that drivers understand that they are supported.
+ */
+ if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
+ epp->ep_phy_cap_mask |=
+ (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
+ if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
+ epp->ep_phy_cap_mask |=
+ (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
+ if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
+ epp->ep_phy_cap_mask |=
+ (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
+
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
goto fail7;
Index: sys/dev/sfxge/common/efx_phy.c
===================================================================
--- sys/dev/sfxge/common/efx_phy.c
+++ sys/dev/sfxge/common/efx_phy.c
@@ -221,11 +221,6 @@
}
}
-#define EFX_PHY_CAP_FEC_REQ_MASK \
- (1U << EFX_PHY_CAP_BASER_FEC_REQUESTED) | \
- (1U << EFX_PHY_CAP_RS_FEC_REQUESTED) | \
- (1U << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED)
-
__checkReturn efx_rc_t
efx_phy_adv_cap_set(
__in efx_nic_t *enp,
@@ -239,8 +234,7 @@
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
- /* Ignore don't care bits of FEC (FEC EFX_PHY_CAP_*_REQUESTED) */
- if ((mask & ~(epp->ep_phy_cap_mask | EFX_PHY_CAP_FEC_REQ_MASK)) != 0) {
+ if ((mask & ~epp->ep_phy_cap_mask) != 0) {
rc = ENOTSUP;
goto fail1;
}
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D18270: sfxge(4): modify phy caps to indicate FEC request
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