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Index: sys/amd64/amd64/pmap.c
===================================================================
--- sys/amd64/amd64/pmap.c
+++ sys/amd64/amd64/pmap.c
@@ -1539,13 +1539,13 @@
}
for (j = 0; i < ndmpdp; i++, j++) {
pdp_p[i] = DMPDphys + ptoa(j);
- pdp_p[i] |= X86_PG_RW | X86_PG_V;
+ pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
}
/*
* Instead of using a 1G page for the memory containing the kernel,
- * use 2M pages with appropriate permissions. (If using 1G pages,
- * this will partially overwrite the PDPEs above.)
+ * use 2M pages with read-only and no-execute permissions. (If using 1G
+ * pages, this will partially overwrite the PDPEs above.)
*/
if (ndm1g) {
pd_p = (pd_entry_t *)DMPDkernphys;
@@ -1555,7 +1555,7 @@
bootaddr_rwx(i << PDRSHIFT);
for (i = 0; i < nkdmpde; i++)
pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
- X86_PG_V;
+ X86_PG_V | pg_nx;
}
/* And recursively map PML4 to itself in order to get PTmap */
@@ -1566,7 +1566,7 @@
/* Connect the Direct Map slot(s) up to the PML4. */
for (i = 0; i < ndmpdpphys; i++) {
p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
- p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
+ p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
}
/* Connect the KVA slots up to the PML4 */

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