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Index: head/sys/dev/cxgbe/common/t4_hw.c
===================================================================
--- head/sys/dev/cxgbe/common/t4_hw.c
+++ head/sys/dev/cxgbe/common/t4_hw.c
@@ -725,10 +725,14 @@
switch (chip_version) {
case CHELSIO_T4:
+ if (adapter->flags & IS_VF)
+ return FW_T4VF_REGMAP_SIZE;
return T4_REGMAP_SIZE;
case CHELSIO_T5:
case CHELSIO_T6:
+ if (adapter->flags & IS_VF)
+ return FW_T4VF_REGMAP_SIZE;
return T5_REGMAP_SIZE;
}
@@ -1207,6 +1211,18 @@
0x27e00, 0x27e04,
};
+ static const unsigned int t4vf_reg_ranges[] = {
+ VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
+ VF_MPS_REG(A_MPS_VF_CTL),
+ VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
+ VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
+ VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
+ VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
+ FW_T4VF_MBDATA_BASE_ADDR,
+ FW_T4VF_MBDATA_BASE_ADDR +
+ ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
+ };
+
static const unsigned int t5_reg_ranges[] = {
0x1008, 0x10c0,
0x10cc, 0x10f8,
@@ -1982,6 +1998,18 @@
0x51300, 0x51308,
};
+ static const unsigned int t5vf_reg_ranges[] = {
+ VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
+ VF_MPS_REG(A_MPS_VF_CTL),
+ VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
+ VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
+ VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
+ VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
+ FW_T4VF_MBDATA_BASE_ADDR,
+ FW_T4VF_MBDATA_BASE_ADDR +
+ ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
+ };
+
static const unsigned int t6_reg_ranges[] = {
0x1008, 0x101c,
0x1024, 0x10a8,
@@ -2559,6 +2587,18 @@
0x51300, 0x51324,
};
+ static const unsigned int t6vf_reg_ranges[] = {
+ VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
+ VF_MPS_REG(A_MPS_VF_CTL),
+ VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
+ VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
+ VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
+ VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
+ FW_T6VF_MBDATA_BASE_ADDR,
+ FW_T6VF_MBDATA_BASE_ADDR +
+ ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
+ };
+
u32 *buf_end = (u32 *)(buf + buf_size);
const unsigned int *reg_ranges;
int reg_ranges_size, range;
@@ -2570,18 +2610,33 @@
*/
switch (chip_version) {
case CHELSIO_T4:
- reg_ranges = t4_reg_ranges;
- reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
+ if (adap->flags & IS_VF) {
+ reg_ranges = t4vf_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
+ } else {
+ reg_ranges = t4_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
+ }
break;
case CHELSIO_T5:
- reg_ranges = t5_reg_ranges;
- reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
+ if (adap->flags & IS_VF) {
+ reg_ranges = t5vf_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
+ } else {
+ reg_ranges = t5_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
+ }
break;
case CHELSIO_T6:
- reg_ranges = t6_reg_ranges;
- reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
+ if (adap->flags & IS_VF) {
+ reg_ranges = t6vf_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
+ } else {
+ reg_ranges = t6_reg_ranges;
+ reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
+ }
break;
default:
Index: head/sys/dev/cxgbe/t4_main.c
===================================================================
--- head/sys/dev/cxgbe/t4_main.c
+++ head/sys/dev/cxgbe/t4_main.c
@@ -8765,7 +8765,7 @@
}
case CHELSIO_T4_REGDUMP: {
struct t4_regdump *regs = (struct t4_regdump *)data;
- int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE;
+ int reglen = t4_get_regs_len(sc);
uint8_t *buf;
if (regs->len < reglen) {

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