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D17783.diff
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Index: head/sys/riscv/include/pte.h
===================================================================
--- head/sys/riscv/include/pte.h
+++ head/sys/riscv/include/pte.h
@@ -78,7 +78,7 @@
#define PTE_V (1 << 0) /* Valid */
#define PTE_RWX (PTE_R | PTE_W | PTE_X)
#define PTE_RX (PTE_R | PTE_X)
-#define PTE_KERN (PTE_V | PTE_RWX | PTE_A | PTE_D)
+#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D)
#define PTE_PPN0_S 10
#define PTE_PPN1_S 19
Index: head/sys/riscv/riscv/locore.S
===================================================================
--- head/sys/riscv/riscv/locore.S
+++ head/sys/riscv/riscv/locore.S
@@ -94,7 +94,7 @@
add t3, t4, t2
li t5, 0
2:
- li t0, (PTE_KERN)
+ li t0, (PTE_KERN | PTE_X)
slli t2, t4, PTE_PPN1_S /* << PTE_PPN1_S */
or t5, t0, t2
sd t5, (s1) /* Store PTE entry to position */
Index: head/sys/riscv/riscv/pmap.c
===================================================================
--- head/sys/riscv/riscv/pmap.c
+++ head/sys/riscv/riscv/pmap.c
@@ -2010,7 +2010,7 @@
}
int
-pmap_fault_fixup(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
+pmap_fault_fixup(pmap_t pmap, vm_offset_t va, vm_prot_t ftype)
{
pt_entry_t orig_l3;
pt_entry_t new_l3;
@@ -2027,12 +2027,13 @@
orig_l3 = pmap_load(l3);
if ((orig_l3 & PTE_V) == 0 ||
- ((prot & VM_PROT_WRITE) != 0 && (orig_l3 & PTE_W) == 0) ||
- ((prot & VM_PROT_READ) != 0 && (orig_l3 & PTE_R) == 0))
+ (ftype == VM_PROT_WRITE && (orig_l3 & PTE_W) == 0) ||
+ (ftype == VM_PROT_EXECUTE && (orig_l3 & PTE_X) == 0) ||
+ (ftype == VM_PROT_READ && (orig_l3 & PTE_R) == 0))
goto done;
new_l3 = orig_l3 | PTE_A;
- if ((prot & VM_PROT_WRITE) != 0)
+ if (ftype == VM_PROT_WRITE)
new_l3 |= PTE_D;
if (orig_l3 != new_l3) {
@@ -2088,7 +2089,9 @@
pa = VM_PAGE_TO_PHYS(m);
pn = (pa / PAGE_SIZE);
- new_l3 = PTE_V | PTE_R | PTE_X | PTE_A;
+ new_l3 = PTE_V | PTE_R | PTE_A;
+ if (prot & VM_PROT_EXECUTE)
+ new_l3 |= PTE_X;
if (flags & VM_PROT_WRITE)
new_l3 |= PTE_D;
if (prot & VM_PROT_WRITE)
@@ -2464,7 +2467,9 @@
pa = VM_PAGE_TO_PHYS(m);
pn = (pa / PAGE_SIZE);
- entry = (PTE_V | PTE_R | PTE_X);
+ entry = PTE_V | PTE_R;
+ if (prot & VM_PROT_EXECUTE)
+ entry |= PTE_X;
entry |= (pn << PTE_PPN0_S);
/*
Index: head/sys/riscv/riscv/trap.c
===================================================================
--- head/sys/riscv/riscv/trap.c
+++ head/sys/riscv/riscv/trap.c
@@ -207,9 +207,11 @@
if ((frame->tf_scause == EXCP_FAULT_STORE) ||
(frame->tf_scause == EXCP_STORE_PAGE_FAULT)) {
- ftype = (VM_PROT_READ | VM_PROT_WRITE);
+ ftype = VM_PROT_WRITE;
+ } else if (frame->tf_scause == EXCP_INST_PAGE_FAULT) {
+ ftype = VM_PROT_EXECUTE;
} else {
- ftype = (VM_PROT_READ);
+ ftype = VM_PROT_READ;
}
if (pmap_fault_fixup(map->pmap, va, ftype))
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D17783: Restrict setting PTE execute permissions on RISC-V.
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