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diff --git a/usr.sbin/bhyve/pci_ahci.c b/usr.sbin/bhyve/pci_ahci.c
--- a/usr.sbin/bhyve/pci_ahci.c
+++ b/usr.sbin/bhyve/pci_ahci.c
@@ -118,7 +118,6 @@
#else
#define DPRINTF(format, arg...)
#endif
-#define WPRINTF(format, arg...) printf(format, ##arg)
#define AHCI_PORT_IDENT 20 + 1
@@ -343,7 +342,7 @@
irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
break;
default:
- WPRINTF("unsupported fis type %d", ft);
+ EPRINTLN("unsupported fis type %d", ft);
return;
}
if (fis[2] & ATA_S_ERROR) {
@@ -1802,7 +1801,7 @@
handle_packet_cmd(p, slot, cfis);
break;
default:
- WPRINTF("Unsupported cmd:%02x", cfis[2]);
+ EPRINTLN("Unsupported cmd:%02x", cfis[2]);
ahci_write_fis_d2h(p, slot, cfis,
(ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
break;
@@ -1847,7 +1846,7 @@
#endif
if (cfis[0] != FIS_TYPE_REGH2D) {
- WPRINTF("Not a H2D FIS:%02x", cfis[0]);
+ EPRINTLN("Not a H2D FIS:%02x", cfis[0]);
return;
}
@@ -2134,7 +2133,7 @@
case AHCI_P_TFD:
case AHCI_P_SIG:
case AHCI_P_SSTS:
- WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
+ EPRINTLN("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
break;
case AHCI_P_SCTL:
p->sctl = value;
@@ -2209,7 +2208,7 @@
else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
pci_ahci_port_write(sc, offset, value);
else
- WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
+ EPRINTLN("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
pthread_mutex_unlock(&sc->mtx);
}
@@ -2307,7 +2306,7 @@
value = pci_ahci_port_read(sc, offset);
else {
value = 0;
- WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
+ EPRINTLN("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
regoff);
}
value >>= 8 * (regoff & 0x3);

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