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Fri, May 10
Wed, May 8
Tue, May 7
Rebase on new macros
Fri, May 3
Thu, May 2
I've been thinking about adding PAGE_SIZE_MAX/PAGE_SHIFT_MAX or similar to arm64 to define the largest page size the kernel could support. We could then use that here if it's defined.
Tue, Apr 30
Mon, Apr 29
Wed, Apr 24
I've thought about this and think we should only read ap_cpuid after the MMU is enabled. The same physical address should be mapped with the same memory type for all virtual addresses, however this isn't possible for ap_cpuid when the MMU is disabled.
Tue, Apr 23
In D44868#1022920, @emaste wrote:Do we need to add support to e.g. ELF Tool Chain readelf and nm to decode these values?
A flag. https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst#st_other-values lists it under Processor specific st_other flags.
Fri, Apr 19
- Fix a comment
- Remove debugging
Given it's a single instruction being written we could just ignore DIC & IDC, I expect the overhead would be less than a system call & this is an uncommon operation. We wouldn't even need to read ctr_el0 as the smallest cacheline size is the same as the instruction size.
Thu, Apr 18
Add missing WITH/WITHOUT files
Rebase and disable until we can check all relavant toolchains support it
It's not very useful as a module as it provides infrastructure other devices need, e.g. their clock, or a reset line. If it was a module these drivers would fail to attach if they were built into the kernel.
Wed, Apr 17
We could look at that as a follow up, however I'm unlikely to have time to make such a change and have it ready and well tested for 14.1 given it's due to be branched in just over 2 weeks.
Tue, Apr 16
Functions that take an SVE register as an argument, or use one for the return value are marked with STO_AARCH64_VARIANT_PCS [1]. In glibc it looks like they avoid lazy resolution for all variant pcs functions. As there are more reasons than just SVE for a function to be marked as a variant, and more reasons could be added in the future I think it's the only safe option.
Rebase and check the SVE registers are only set once
Rework to not guarentee the SVE registers are saved over a syscall other than sigreturn.
The ABI doesn't require SVE registers to be saved on a function call so extend this to a system call.
As dropping the SVE state on all system calls could get expensive only do it on context switch when in one.
Rename to PHYS_IN_DMAP_RANGE
Mon, Apr 15
Apr 12 2024
I don't think we need to store the SCE registers in getcontextx. It's a function call that doesn't take an SVE register as an argument so the ABI doesn't require the upper bits of SVE registers to be preserved. We could restore the SVE registers in setcontextx if they are in the list of registers.
Apr 11 2024
Apr 10 2024
It looks like the icache handling is missing after writing the brk instruction. I think this could be done from userspace as VPIPT i-cache has been removed from the architecture [1].