bhyve: Add arm64 support to the gdb stub

[markj]

Summary

Sponsored by: Innovate UK

[andrew]

It looks like the icache handling is missing after writing the brk instruction. I think this could be done from userspace as VPIPT i-cache has been removed from the architecture [1].

[1] https://lore.kernel.org/linux-arm-kernel/[e-mail]/T/

usr.sbin/bhyve/gdb.c

249

Can we fix this to be 8? It's a bug that we only support the lower 32 bits of spsr in GDB as the register. The PPEND field is in bit 33 so would be missed from this.

[markj]

In D44740#1019798, @andrew wrote:

It looks like the icache handling is missing after writing the brk instruction. I think this could be done from userspace as VPIPT i-cache has been removed from the architecture [1].

[1] https://lore.kernel.org/linux-arm-kernel/[e-mail]/T/

It'd seem a bit easier to do it in the kernel, so that we don't have to check the DIC and IDC again like identify_cpu_sysinit() already does. Perhaps a sysarch command to flush the icache would be acceptable? If not I can do it in userspace.

[andrew]

Given it's a single instruction being written we could just ignore DIC & IDC, I expect the overhead would be less than a system call & this is an uncommon operation. We wouldn't even need to read ctr_el0 as the smallest cacheline size is the same as the instruction size.

usr.sbin/bhyve/gdb.c

326–347

I have this in my local version of gdb.c. If fixes an issue with getting the ttbr* addresses, and the guest mode.

[markj]

Handle review comments

• Invalidate the icache after updating guest memory.
• Widen SPSR.
• Mask off extra flags in TTBR registers.

[andrew]

usr.sbin/bhyve/gdb.c

1112

We should be setting the lower bits of esr. It looks like you can get them from vmexit->u.hyp.esr_el2.