arm: Add ARM PL022 Synchronous Serial Port driver

[jhibbits]

Summary

ARM pl022 is a general purpose synchronous serial port controller,
implementing SPI, SSI, and National Microwire frame formats. The driver
currently only supports SPI format.

One limitation of the driver is that hardware only raises an interrupt
if the RX queue contains at least 4 characters, so fewer than 4
characters in the queue may result in data never being received.

Obtained from: Juniper Networks, Inc.

[br]

sys/arm/arm/pl022.h

47

For the bit definition I usually omit prefix (i.e. PL022_), and put extra space after tab.
that allows easier navigation with bare eye.
example sys/arm64/iommu/smmureg.h

[andrew]

One limitation of the driver is that hardware only raises an interrupt if the RX queue contains at least 4 characters, so fewer than 4 characters in the queue may result in data never being received.

Do you not receive the SSPRTINTR interrupt?

sys/arm/arm/pl022.c

136

217

230

ditto

[jhibbits]

In D45211#1036945, @andrew wrote:

One limitation of the driver is that hardware only raises an interrupt if the RX queue contains at least 4 characters, so fewer than 4 characters in the queue may result in data never being received.

Do you not receive the SSPRTINTR interrupt?

Nope, and it's documented in the reference (DDI0194H):

3.4.1
SSPRXINTR
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

sys/arm/arm/pl022.c

136

Oops, and I'm usually the one to give grief over style(9), myself. Will take a closer pass, along with the others.

[andrew]

In D45211#1036969, @jhibbits wrote:

3.4.1
SSPRXINTR
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

That's a different interrupt, see 3.4.4 SSPRTINTR of the same document.

[jhibbits]

In D45211#1036980, @andrew wrote:

In D45211#1036969, @jhibbits wrote:

3.4.1
SSPRXINTR
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.

That's a different interrupt, see 3.4.4 SSPRTINTR of the same document.

Ah, sorry, I had misread. Apparently I don't get the SSPRTINTR on the device I have, as it seems to time out (2 second timeout) on 3-byte messages, and the interrupt is enabled. Maybe it's an issue with my particular device?

[jhibbits]

Address style feedback.