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Differential D45226

Fix SSTC extension support
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Authored by br on Fri, May 17, 8:19 AM.
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Details

Reviewers
mhorne
jrtc27
Group Reviewers
riscv
Commits
rGddd0d4f4cd65: riscv: Fix SSTC extension support
Summary

Based on SSTC spec (1):

"If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp. This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value."

This fixes operation in Spike with SSTC extension enabled, e.g.

$ spike --isa RV64IMAFDCH_zicntr_zihpm_sstc

[1]. https://tools.cloudbear.ru/docs/riscv-sstc-0.5.4-20211013.pdf

Test Plan

Tested in Spike only

Diff Detail

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rG FreeBSD src repository
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Event Timeline

br requested review of this revision.Fri, May 17, 8:19 AM
br created this revision.
mhorne accepted this revision.Fri, May 17, 2:19 PM
mhorne added inline comments.
sys/riscv/riscv/timer.c
147

We can rely on sign-extension or should it be -1UL?

This revision is now accepted and ready to land.Fri, May 17, 2:19 PM
br updated this revision to Diff 138703.Fri, May 17, 10:29 PM

use UL suffix to not rely on sign-extension

This revision now requires review to proceed.Fri, May 17, 10:29 PM
mhorne accepted this revision.Wed, May 22, 1:48 PM
This revision is now accepted and ready to land.Wed, May 22, 1:48 PM
Closed by commit rGddd0d4f4cd65: riscv: Fix SSTC extension support (authored by br). · Explain WhyWed, May 22, 4:07 PM
This revision was automatically updated to reflect the committed changes.
br added a commit: rGddd0d4f4cd65: riscv: Fix SSTC extension support.
Herald added a subscriber: imp. · View Herald TranscriptWed, May 22, 4:07 PM

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Diff 138930

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sys/riscv/riscv/timer.c

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