Change Details

Perform ISA parsing per-CPU. We currently perform per-CPU ISA parsing all in one go, in fill_elf_hwcap() at SI_SUB_CPU. Instead, let's have each CPU call this (renamed) function as part of identify_cpu(). This makes some additions to this code simpler, and allows feature parsing for the BSP to take place much earlier. It also ensures we will only perform this parsing for enabled CPUs. Currently the loop does not guard against harts which will never enter the kernel, such as the management hart on the HiFive Unmatched which has no MMU.

riscv: rework CPU identification [3/6] Perform all parsing+reporting on CPU 0. Make use of the SMP hooks cpu_mp_start() and cpu_mp_announce() to identify and print secondary CPU info, respectively. Eliminate the SYSINIT from identcpu.c. We still need to walk the /cpus list in the device tree, but now do this one CPU at a time, as a step in the identify_cpu() procedure. This is slightly less error prone, and allows us to parse ISA features for CPU 0 much earlier. This causes secondary processor identification to be printed much earlier in boot; everything is done by SI_SUB_CPU, SI_ORDER_THIRD. Adjust some other printf calls so that we get enough useful info to debug under bootverbose.

Perform ISA parsing per-CPU.riscv: rework CPU identification [3/6] We currently perform per-CPU ISA parsing all in one go, inPerform all parsing+reporting on CPU 0. Make use of the SMP hooks cpu_mp_start() and cpu_mp_announce() to fill_elf_hwcap() at SI_SUB_CPU. Insteadidentify and print secondary CPU info, let's have each CPU call this (renamed) function as part of identify_cpu()respectively. This makes some additions to this code simpler,Eliminate the SYSINIT from identcpu.c. and allows featureWe still need to walk the /cpus parsing for the BSP to take place much earlier.list in the device tree, but now do this one CPU at a time, It also ensures we willas a step in only perform tthe identify_cpu() procedure. This parsing for enabled CPUs.is slightly less error prone, Currently the loop does notand guard against harts which will never enter the kernel, such as theallows us to parse ISA features for CPU 0 much earlier. This causes secondary processor identification to be printed much management hart on the HiFive Unmatched which has no MMUearlier in boot; everything is done by SI_SUB_CPU, SI_ORDER_THIRD. Adjust some other printf calls so that we get enough useful info to debug under bootverbose.