Change Details

Support for 2nd scheme of managing A (accessed) and D (dirty) bits of PTE. Schemes described in page 61 of riscv-privileged-v1.10.pdf document. QEMU uses 1st scheme. Spike has a compile-time macro RISCV_ENABLE_DIRTY to switch between schemes. RocketCore and derivatives (e.g. lowRISC) support 2nd scheme only. This patch enables support for both schemes by setting A and D bits on kernel page tables.

Support for 2nd scheme of managing A (accessed) and D (dirty) bits of PTE. Schemes described in page 61 of riscv-privileged-v1.10.pdf document. QEMU uses 1st scheme. Spike has a compile-time macro RISCV_ENABLE_DIRTY to switch between schemes. RocketCore and derivatives (e.g. lowRISC) support 2nd scheme only.

Support for 2nd scheme of managing A (accessed) and D (dirty) bits of PTE. Schemes described in page 61 of riscv-privileged-v1.10.pdf document. QEMU uses 1st scheme. Spike has a compile-time macro RISCV_ENABLE_DIRTY to switch between schemes. RocketCore and derivatives (e.g. lowRISC) support 2nd scheme only. This patch enables support for both schemes by setting A and D bits on kernel page tables.