Change Details

TSO tested on I219. Interesting observation: performance is lower on this particular SPT-era NIC. This is due to the Intel-recommended workaround for " i218-i219 Specification Update 1.5.4.5" -- this lowers the throughput by 200mbit/s. If I disable the code (E1000_TARC0_CB_MULTIQ_2_REQ), I am able to get full performance at well under half the CPU usage. I'll see if there is a better way to do this but I may not be able to change it without help from Intel.

TSO tested on I219. Interesting observation: performance is lower on this particular SPT-era NIC. This is due to the Intel-recommended workaround for " i218-i219 Specification Update 1.5.4.5" -- this lowers the throughput by 200mbit/s. If I disable the code (E1000_TARC0_CB_MULTIQ_2_REQ), I am able to get full performance at well under half the CPU usage. I'll see if there is a better way to do this but I may not be able to change it without help from Intel. It's just an older generation part so the newer I219s can do TSO after a careful reading of the spec update, I'll consider that after more testing.

TSO tested on I219. Interesting observation: performance is lower on this particular SPT-era NIC. This is due to the Intel-recommended workaround for " i218-i219 Specification Update 1.5.4.5" -- this lowers the throughput by 200mbit/s. If I disable the code (E1000_TARC0_CB_MULTIQ_2_REQ), I am able to get full performance at well under half the CPU usage. I'll see if there is a better way to do this but I may not be able to change it without help from Intel. It's just an older generation part so the newer I219s can do TSO after a careful reading of the spec update, I'll consider that after more testing.