Change Details

The PLIC registers are divided up by "context" which is purposefully left ambiguous in the PLIC spec. In Sifive compatible PLIC implementations (most existing implementations), the mapping from hart to context is not 1-to-1. Instead each hart has an interrupt context for machine mode and supervisor mode. Fix the calculation to always target the supervisor contexts. The incorrect calculations went previously unnoticed due to the way the PLIC was initialized by the bootloader firmware. Relevant PLIC specs: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc https://sifive.cdn.prismic.io/sifive%2Fdc4980ff-17db-448b-b521-4c7ab26b7488_sifive+u54-mc+manual+v19.08.pdf (Chapter 10)

The PLIC registers are divided up by "context" which is purposefully left ambiguous in the PLIC spec. Currently we assume each CPU number corresponds 1-to-1 with a context number, but that is not correct. Most existing PLIC implementations (such as SiFive's) have multiple contexts per-cpu. For example, a single CPU might have a context for machine mode interrupts and a context for supervisor mode interrupts. To complicate things further, FreeBSD renumbers the CPUs during boot, but the PLIC driver still assumes that CPU ID equals the RISC-V hart number, meaning interrupt enables/claims might be performed for the wrong context registers. To fix this, we must calculate each CPU's context number during attachment. This is done by reading the interrupt properties from the device tree, from which a mapping from context to RISC-V hart to CPU number can be created Relevant PLIC specs: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc https://sifive.cdn.prismic.io/sifive%2Fdc4980ff-17db-448b-b521-4c7ab26b7488_sifive+u54-mc+manual+v19.08.pdf (Chapter 10)

The PLIC registers are divided up by "context" which is purposefully left ambiguous in the PLIC spec. In Sifive compatible PLICCurrently we assume each CPU number implementations (most existing implementations),corresponds 1-to-1 with a context number, but that is not correct. the mapping from hartMost to context is not 1-to-1. Instead each hart has an interruptexisting PLIC implementations (such as SiFive's) have multiple context fors machine mode and supervisor mode.per-cpu. For example, Fix the calculation to always targeta single CPU might have a context for machine mode theinterrupts and a context for supervisor contextsmode interrupts. The incorrect calculations went previouslyTo complicate unnoticed due to the waythings further, FreeBSD renumbers the PLIC was initialized byCPUs during boot, but the bootloaderPLIC firmware.driver still assumes that CPU ID equals the RISC-V hart number, meaning interrupt enables/claims might be performed for the wrong context registers. To fix this, we must calculate each CPU's context number during attachment. This is done by reading the interrupt properties from the device tree, from which a mapping from context to RISC-V hart to CPU number can be created Relevant PLIC specs: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc https://sifive.cdn.prismic.io/sifive%2Fdc4980ff-17db-448b-b521-4c7ab26b7488_sifive+u54-mc+manual+v19.08.pdf (Chapter 10)