Change Details

When a PL310 cache is used in a system that provides hardware coherency, the entire outer cache operations are useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, various controllers and the Cortex-A9. For this purpose there was enabled an easy way to substitute pl310 cpufuncs.cf_l2cache_drain_writebuf callback in the platform code. Marvell common initialization code makes use of it, replacing harmful pl310_drain_writebuf by no-op, in case dma-coherent property under parent simple-bus is found. Also for proper DMA-coherent operation, MBUS windows attribute update was required.

In order to work properly in IO-coherent mode, MBUS windows attributes have to be updated. Detect the mode, basing on 'dma-coherent' property under /soc node in the device tree.

When a PL310 cache is usedIn order to work properly in a system that provides hardwareIO-coherent mode, MBUS windows attributes coherency,have to be updated. the entire outer cache operations are uselessDetect the mode, and can bebasing on 'dma-coherent' property skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, various controllers and the Cortex-A9. For this purpose there was enabled an easy way to substitute pl310 cpufuncs.cf_l2cache_drain_writebuf callback in the platform code. Marvell common initialization code makes use of it, replacing harmful pl310_drain_writebuf by no-op, in case dma-coherent property under parent simple-bus is found. Also for proper DMA-coherent operation, MBUS windows attribute update was requiredunder /soc node in the device tree.