Change Details

We need a correct value of ttbr0 to operate. I am not sure why it is zero in my case. When scheduler returns us back to thread0 we need to have correct ttbr0 value so hardware page walker can translate addresses. This value will be loaded to ttbr0 register in cpu_switch() function called by scheduler. This is similar to RISC-V where we already do this. This is a fix for Qualcomm Snapdragon 410E (Cortex A-53) SoC used in DragonBoard 410c. Without this fix the Qualcomm board goes to reboot on any access to VA space.

We need a correct value of ttbr0 to operate. I am not sure why it is zero in my case. When scheduler returns us back to thread0 we need to have correct ttbr0 value so hardware page walker can translate addresses. This value will be loaded to ttbr0 register in cpu_switch() function called by scheduler. This is similar to RISC-V where we already do this. This is a fix for Qualcomm Snapdragon 410E (Cortex A-53) SoC used in DragonBoard 410c. Without this fix the Qualcomm board goes to reboot on any access to VA space. UPDATE: My comment is wrong, we don't need ttbr0 for address translation in kernel, because ttbr0 is user page table base register. However it looks like Qualcomm (And Nvidia?) proceed a sanity check, and writing 0 to this register leads to reboot on Qualcomm. So based on this and similar to other kernel threads, do install the value of kernel pmap L0 directory to TTBR0.

We need a correct value of ttbr0 to operate. I am not sure why it is zero in my case. When scheduler returns us back to thread0 we need to have correct ttbr0 value so hardware page walker can translate addresses. This value will be loaded to ttbr0 register in cpu_switch() function called by scheduler. This is similar to RISC-V where we already do this. This is a fix for Qualcomm Snapdragon 410E (Cortex A-53) SoC used in DragonBoard 410c. Without this fix the Qualcomm board goes to reboot on any access to VA space. UPDATE: My comment is wrong, we don't need ttbr0 for address translation in kernel, because ttbr0 is user page table base register. However it looks like Qualcomm (And Nvidia?) proceed a sanity check, and writing 0 to this register leads to reboot on Qualcomm. So based on this and similar to other kernel threads, do install the value of kernel pmap L0 directory to TTBR0.