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so it is visible to a CPU which might pick up the thread for execution. For instance, consider the CLFLUSHOPT loop in pmap_invalidate_cache_pages(): the partially accumulated flushes might stay in the write-combining buffer for some time, and if the thread was switched to other CPU in the middle of the loop, potentially we get two partially formed buffers. I suspect this might affect even userspace code, Intel SDM states that interrupts and exceptions flush store buffers, but this is said in context of WB memory.

so it is visible to a CPU which might pick up the thread for execution. On Intel, all writes, in particular write-combining store buffers, are flushed by a locked operation, so the thread lock taken on the switch part should be enough. On some AMD models, the APM is self-contradictory: one place states that the locked operation is enough, but the description of CLFLUSH is explicit to mention that on models without CLFLUSHOPT only MFENCE would do it.

so it is visible to a CPU which might pick up the thread for execution. For instanceOn Intel, all writes, consider the CLFLUSHOPT loop in pmap_invalidate_cache_pages(): the partially accumulated flushes might stay in the write-combining buffer for some timein particular write-combining store buffers, and if the thread was switched to other CPU in the middle of the loopare flushed by a locked operation, potentially we get two partially formed buffersso the thread lock taken on the switch part should be enough. I suspect this might affect even userspace codeOn some AMD models, Intel SDM states that interrupts and exceptions flush store buffersthe APM is self-contradictory: one place states that the locked operation is enough, but thise description of CLFLUSH is said in context of WB memoryexplicit to mention that on models without CLFLUSHOPT only MFENCE would do it.