The patch below was booted multiuser on desktop haswell-class machine, ivy laptop and sandybridge two-socket xeon, also on the Core2 two-socket/5400 box. The later machine has ahci controller which has MSI block of 16 interrupts, so MSI (without -X) was tested as well.
For review, please note that the patch naturally splits into changes to the interrupt code, and DMAR IR support. I would highly appreaciate a review of the code outside x86/iommu, and definitely will understand if you do not want to read iommy changes proper.