Change Details

Tested with LS1046A SoC. Contains classes and functions that can be used with various QorIQ Layerscape SoCs. Clock nodes available for peripherals should be named according to scheme "cg-<node_name>-<node_index". Node names are used for lookup in ofw_mapper function. PLL nodes cannot be written. Additional divider nodes are created on PLL outputs. Uses built-in clk_mux nodes to represent CMUX and HWACCEL clock nodes. This is a preparation patch for NXP LS1046A SoC support.

Tested with LS1046A SoC. Contains classes and functions that can be used with various QorIQ Layerscape SoCs. PLL nodes cannot be written. Additional divider nodes are created on PLL outputs. Uses built-in clk_mux nodes to represent CMUX and HWACCEL clock nodes. This is a preparation patch for NXP LS1046A SoC support.

Tested with LS1046A SoC. Contains classes and functions that can be used with various QorIQ Layerscape SoCs. Clock nodes available for peripherals should be named according to scheme "cg-<node_name>-<node_index". Node names are used for lookup in ofw_mapper function. PLL nodes cannot be written. Additional divider nodes are created on PLL outputs. Uses built-in clk_mux nodes to represent CMUX and HWACCEL clock nodes. This is a preparation patch for NXP LS1046A SoC support.