Change Details

The EIC7700 has non-coherent DMAs but predate the standard RISC-V Zicbom extension, so we need to use the SiFive CCache controller for non-standard cache management operations. Not sure about file location as this supports EIC7700 only, but could be adopted later to support standard cache management bits as well.

The EIC7700 has non-coherent DMAs but predate the standard RISC-V Zicbom extension, so we need to use the SiFive CCache controller for non-standard cache management operations. Not sure about file location as this supports EIC7700 only, but could be adopted later to support earlier SiFive SoCs as well.

The EIC7700 has non-coherent DMAs but predate the standard RISC-V Zicbom extension, so we need to use the SiFive CCache controller for non-standard cache management operations. Not sure about file location as this supports EIC7700 only, but could be adopted later to support standard cache management bitearlier SiFive SoCs as well.