Change Details

The PLIC registers are divided up by "context" which is purposefully left ambiguous in the PLIC spec. In Sifive compatible PLIC implementations (most existing implementations), the mapping from hart to context is not 1-to-1. Instead each hart has an interrupt context for machine mode and supervisor mode. Fix the calculation to always target the supervisor contexts. The incorrect calculations went previously unnoticed due to the way the PLIC was initialized by the bootloader firmware.

The PLIC registers are divided up by "context" which is purposefully left ambiguous in the PLIC spec. In Sifive compatible PLIC implementations (most existing implementations), the mapping from hart to context is not 1-to-1. Instead each hart has an interrupt context for machine mode and supervisor mode. Fix the calculation to always target the supervisor contexts. The incorrect calculations went previously unnoticed due to the way the PLIC was initialized by the bootloader firmware. Relevant PLIC specs: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc https://sifive.cdn.prismic.io/sifive%2Fdc4980ff-17db-448b-b521-4c7ab26b7488_sifive+u54-mc+manual+v19.08.pdf (Chapter 10)

The PLIC registers are divided up by "context" which is purposefully left ambiguous in the PLIC spec. In Sifive compatible PLIC implementations (most existing implementations), the mapping from hart to context is not 1-to-1. Instead each hart has an interrupt context for machine mode and supervisor mode. Fix the calculation to always target the supervisor contexts. The incorrect calculations went previously unnoticed due to the way the PLIC was initialized by the bootloader firmware. Relevant PLIC specs: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc https://sifive.cdn.prismic.io/sifive%2Fdc4980ff-17db-448b-b521-4c7ab26b7488_sifive+u54-mc+manual+v19.08.pdf (Chapter 10)