Change Details

Mapping the frame buffer with WC (Write Combined) memory type, can in practice cause some memory transactions to be rate-limited at a fraction of the memory frame buffer write rate. WC allows one core to queue up many globally visible write transactions. Some unrelated transactions may end up having to wait for all the queued up PCI writes to be flushed. The solution is to map the frame buffer as uncachable which prevents the queueing of more than one PCI write. Submitted by: Marc De La Gueronniere <mdelagueronniere@verisign.com> MFC after: 1 week Sponsored by: Verisign, Inc.

Mapping the framebuffer with WC (Write Combined) memory type can, in practice, cause some memory transactions to be rate-limited at a fraction of the fb write rate. WC allows one core to queue up many globally visible write transactions, and in the process some unrelated transactions may end up having to wait for all of the queued up PCI writes to be flushed. Add an hw.efifb.cache_attr tunable to allow mapping the framebuffer as uncacheable instead. We should likely be taking a more careful approach of checking the memory map to determine which cacheability attributes are feasible, but the knob lets us use our historically functional behavior while offering a convenient way to switch on a stock kernel. The only valid values for hw.efifb.cache_attr at this time are "uc" and "wc". Original patch by Marc De La Gueronniere <mdelagueronniere@verisign.com> MFC after: 1 week Sponsored by: Verisign, Inc. Sponsored by: Klara, Inc.

Mapping the frame buffer with WC (Write Combined) memory type can, can in practice causein practice, cause some memory transactions to be rate-limited at a fraction of the memory frame buffer fraction of the fb write rate. WC allows one core to queue up many globally visible write transactions. Some unrelatedglobally visible write transactions may end up having to wait for all the queued up PCI writes, and in the process some unrelated transactions may end up having to wait for all of the queued up PCI writes to be flushed. The solution is to map the frame buffer as uncachable which preventsAdd an hw.efifb.cache_attr tunable to allow mapping the queueing offramebuffer as more than one PCI writeuncacheable instead. We should likely be taking a more careful approach of checking the memory map to determine which cacheability attributes are feasible, but the knob lets us use our historically functional behavior while offering a convenient way to switch on a stock kernel. Submitted by: Marc De La Gueronniere <mdelagueronniere@verisign.com>The only valid values for hw.efifb.cache_attr at this time are "uc" and "wc". Original patch by Marc De La Gueronniere <mdelagueronniere@verisign.com> MFC after: 1 week Sponsored by: Verisignn, Inc. Sponsored by: Klara, Inc.