Change Details

Some early PCIe chipsets are explicitly listed in the white-list to enable use of the MMIO config space accesses, perhaps because ACPI tables were not reliable source of the base MCFG address at that time. During very early stage of boot, see pci_early_quirks.c, we cannot map 255MB of registers because the method used overflows initial kernel page tables. Continue using the io config method until pmap is bootstrapped enough. There is a mention in the Intel documentation for corresponding chipsets that OS must use either io port or MMIO access method, but we already break this rule by reading MCFGbase register, so one more access seems to be innocent. PR: 236838

Some early PCIe chipsets are explicitly listed in the white-list to enable use of the MMIO config space accesses, perhaps because ACPI tables were not reliable source of the base MCFG address at that time. During very early stage of boot, see pci_early_quirks.c, we cannot map 255MB of registers because the method used overflows initial kernel page tables. Remove fallback for some old Intel chipsets where the MCFG base is read from the known chipset register, instead use io access until MCFG is parsed. There is a mention in the Intel documentation for corresponding chipsets that OS must use either io port or MMIO access method, but we already break this rule by reading MCFGbase register, so one more access seems to be innocent. PR: 236838

Some early PCIe chipsets are explicitly listed in the white-list to enable use of the MMIO config space accesses, perhaps because ACPI tables were not reliable source of the base MCFG address at that time. During very early stage of boot, see pci_early_quirks.c, we cannot map 255MB of registers because the method used overflows initial kernel page tables. Continue using the io config method until pmap is bootstrapped enoughRemove fallback for some old Intel chipsets where the MCFG base is read from the known chipset register, instead use io access until MCFG is parsed. There is a mention in the Intel documentation for corresponding chipsets that OS must use either io port or MMIO access method, but we already break this rule by reading MCFGbase register, so one more access seems to be innocent. PR: 236838