Index: stable/4/release/doc/en_US.ISO8859-1/hardware/common/dev.sgml
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--- stable/4/release/doc/en_US.ISO8859-1/hardware/common/dev.sgml	(revision 90007)
+++ stable/4/release/doc/en_US.ISO8859-1/hardware/common/dev.sgml	(revision 90008)
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 <!--
 
 	The "Supported Devices" section of the release notes.
 	Generally processor-independent, with conditional text
 	inclusion handling any architecture-dependent text.
 
 	Within each subsection describing a class of hardware
 	(i.e. Ethernet interfaces), list broad groups of devices
 	alphabetically as paragraphs sorted alphabetically (frequently
 	these groups will be arranged by manufacturer, i.e. 3Com
 	Ethernet interfaces).  In cases where a group of devices
 	consists of multiple models (such as the 3C501, 3C503, etc.),
 	list each specific model or set of closely-related models as
 	a separate item in an itemized list, sorted alphabetically.
 	Where applicable, a "Miscellaneous" section may follow all
 	other named sections.
 
 	These guidelines are not hard-and-fast rules, and exceptions
 	will occur.  Following these guidelines (vague as they may be)
 	is highly recommended to try to keep the formatting of
 	this section consistent.
 
 	We give manpage references using the &man entities where
 	possible.  If a driver has no manpage (and consequently no
 	&man entity, we simply give the name of the driver).  
 	Please avoid doing &man entity conversions unless you
 	know for sure that an entity and manpage exist; sweeps through
 	this file to fix "missed" conversions are likely to break the
 	build.
 -->
 
 <sect1>
   <sect1info>
     <pubdate>$FreeBSD$</pubdate>
   </sect1info>
 
   <title>Supported Devices</title>
 
   <para>This section describes the devices currently known to be
   supported by with &os; on the &arch.print; platform.  Other configurations
   may also work, but simply have not been tested yet.  Feedback,
   updates, and corrections to this list are encouraged.</para>
 
   <para>Where possible, the drivers applicable to each device or class
   of devices is listed.  If the driver in question has a manual page
   in the &os; base distribution (most should), it is referenced here.</para>
 
   <sect2>
     <title>Disk Controllers</title>
       <para arch="i386,alpha">IDE/ATA controllers (&man.ata.4; driver)
         <itemizedlist>
 	   <listitem>
 	     <para>Acerlabs Aladdin</para>
 	   </listitem>
 	   <listitem>
 	     <para>AMD 756, 766</para>
 	   </listitem>
 	   <listitem>
 	     <para>CMD 646, 648 ATA66, and 649 ATA100</para>
 	   </listitem>
 	   <listitem>
 	     <para>Cypress 82C693</para>
 	   </listitem>
 	   <listitem>
 	     <para>Cyrex 5530</para>
 	   </listitem>
 	   <listitem>
 	     <para>HighPoint HPT366 ATA66, HPT370 ATA100, HPT372 ATA133</para>
 	   </listitem>
 	   <listitem>
 		<para>Intel PIIX, PIIX3, PIIX4</para>
 	   </listitem>
 	   <listitem>
 		<para>Intel ICH ATA66, ICH2 ATA100, ICH3 ATA100</para>
 	   </listitem>
 	   <listitem>
 		<para>Promise ATA100 OEM chip (pdc20265)</para>
 	   </listitem>
 	   <listitem>
 		<para>Promise Fasttrak-33, -66, -100 TX2/TX4</para>
 	   </listitem>
 	   <listitem>
 		<para>Promise Ultra-33, -66, -100</para>
 	   </listitem>
 	   <listitem>
 		<para>ServerWorks ROSB4 ATA33</para>
 	   </listitem>
 	   <listitem>
 	        <para>SiS 530, 540, 620</para>
 	   </listitem>
 	   <listitem>
 	        <para>SiS 630, 633, 635, 730, 733, 735</para>
 	   </listitem>
 	   <listitem>
 		<para>SiS 5591</para>
 	   </listitem>
 	   <listitem>
 		<para>VIA 82C586 ATA33, 82C596 ATA66, 82C686a ATA66, 82C686b ATA100</para>
 	   </listitem>
       </itemizedlist>
     </para>
     <para arch="i386,alpha">Adaptec SCSI Controllers
       <itemizedlist>
         <listitem arch="i386">
 	  <para>Adaptec 1535 ISA SCSI controllers</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 154x series ISA SCSI controllers 
 	  (&man.aha.4; driver)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 164x series MCA SCSI controllers (&man.aha.4; 
 	  driver)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 174x series EISA SCSI controller in standard
 	  and enhanced mode (&man.aha.4; and &man.ahb.4; driver)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 274x series EISA SCSI controllers, including
 	  narrow and wide variants (&man.ahc.4;
 	  driver)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 284x series VLB SCSI controllers, including
 	  narrow and wide variants (&man.ahc.4;
 	  driver)</para>
 	</listitem>
 	<listitem arch="i386,alpha">
 	  <para>Adaptec 19160/291x/2920/2930/2940/2950/29160/3940/3950/3960/39160/398x/494x
 	  series PCI SCSI controllers, including
 	  Narrow/Wide/Twin/Ultra/Ultra2 variants (&man.ahc.4;
 	  driver)</para>
 	</listitem>
 	<listitem arch="i386,alpha">
 	  <para>Adaptec AIC7770, AIC7850, AIC7860, AIC7870, AIC7880, 
 	  and AIC789x on-board
 	  SCSI controllers (&man.ahc.4; driver)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 1510 series ISA SCSI controllers (not for
 	  bootable devices)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec 152x series ISA SCSI controllers (&man.aha.4;
 	  driver)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Adaptec AIC-6260 and AIC-6360 based boards, which
 	  includes the AHA-152x and SoundBlaster SCSI cards
 	  (&man.aic.4; driver)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Adaptec 2100S/32x0S/34x0S SCSI RAID
     controllers (&man.asr.4; driver)</para>
 
     <para arch="i386">Adaptec 2000S/2005S Zero-Channel RAID controllers
     (&man.asr.4; driver)</para>
 
     <para arch="i386">Adaptec 2400A ATA-100 RAID controller
     (&man.asr.4; driver)</para>
 
     <para arch="i386">Adaptec FSA family RAID controllers (&man.aac.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>Adaptec AAC-2622</para>
 	</listitem>
 	<listitem>
 	  <para>Adaptec AAC-364</para>
 	</listitem>
 	<listitem>
 	  <para>Adaptec SCSI RAID 5400S</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 2/QC</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 2/Si</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 3/Di</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 3/QC</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 3/Si</para>
 	</listitem>
 	<listitem>
 	  <para>HP NetRAID-4M</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">AdvanSys SCSI controllers (all models, &man.adv.4; and
     &man.adw.4; drivers)</para>
 
     <para arch="i386">BusLogic MultiMaster <quote>W</quote> Series Host Adapters
     (&man.bt.4; driver):
       <itemizedlist>
 	<listitem>
 	  <para>BT-948</para>
 	</listitem>
 	<listitem>
 	  <para>BT-958</para>
 	</listitem>
 	<listitem>
 	  <para>BT-958D</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">BusLogic MultiMaster <quote>C</quote> Series Host Adapters
     (&man.bt.4; driver):
       <itemizedlist>
         <listitem>
 	  <para>BT-946C</para>
 	</listitem>
 	<listitem>
 	  <para>BT-956C</para>
 	</listitem>
 	<listitem>
 	  <para>BT-956CD</para>
 	</listitem>
 	<listitem>
 	  <para>BT-445C</para>
 	</listitem>
 	<listitem>
 	  <para>BT-747C</para>
 	</listitem>
 	<listitem>
 	  <para>BT-757C</para>
 	</listitem>
 	<listitem>
 	  <para>BT-757CD</para>
 	</listitem>
 	<listitem>
 	  <para>BT-545C</para>
 	</listitem>
 	<listitem>
 	  <para>BT-540CF</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">BusLogic MultiMaster <quote>S</quote> Series Host Adapters
     (&man.bt.4; driver):
       <itemizedlist>
 	<listitem>
 	  <para>BT-445S</para>
 	</listitem>
 	<listitem>
 	  <para>BT-747S</para>
 	</listitem>
 	<listitem>
 	  <para>BT-747D</para>
 	</listitem>
 	<listitem>
 	  <para>BT-757S</para>
 	</listitem>
 	<listitem>
 	  <para>BT-757D</para>
 	</listitem>
 	<listitem>
 	  <para>BT-545S</para>
 	</listitem>
 	<listitem>
 	  <para>BT-542D</para>
 	</listitem>
 	<listitem>
 	  <para>BT-742A</para>
 	</listitem>
 	<listitem>
 	  <para>BT-542B</para>
 	</listitem>
       </itemizedlist>
     </para>
     
     <para arch="i386">BusLogic MultiMaster <quote>A</quote> Series Host Adapters
     (&man.bt.4; driver):
       <itemizedlist>
         <listitem>
 	  <para>BT-742A</para>
 	</listitem>
 	<listitem>
 	  <para>BT-542B</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <note arch="i386">
       <para>BusLogic/Mylex <quote>Flashpoint</quote> adapters are not yet
       supported.</para>
     </note>
     <note arch="i386">
       <para>AMI FastDisk controllers that are true BusLogic
       MultiMaster clones are also supported.</para>
     </note>
     
     <note arch="i386">
       <para>The Buslogic/Bustek BT-640 and Storage Dimensions SDC3211B
       and SDC3211F Microchannel (MCA) bus adapters are also
       supported.</para>
     </note>
 
     <para arch="i386">DPT SmartCACHE Plus, SmartCACHE III, SmartRAID III, SmartCACHE IV and
     SmartRAID IV SCSI/RAID controllers (&man.dpt.4; driver)</para>
 
     <para arch="i386">DPT SmartRAID V and VI SCSI RAID controllers
     (&man.asr.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>PM1554</para>
 	</listitem>
         <listitem>
 	  <para>PM2554</para>
 	</listitem>
         <listitem>
 	  <para>PM2654</para>
 	</listitem>
         <listitem>
 	  <para>PM2865</para>
 	</listitem>
         <listitem>
 	  <para>PM2754</para>
 	</listitem>
         <listitem>
 	  <para>PM3755</para>
 	</listitem>
         <listitem>
 	  <para>PM3757</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">AMI MegaRAID Express and Enterprise family RAID controllers
     (&man.amr.4; driver)
       <itemizedlist>
         <listitem>
           <para>MegaRAID Series 418</para>
         </listitem>
 	<listitem>
 	  <para>MegaRAID Enterprise 1200 (Series 428)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Enterprise 1300 (Series 434)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Enterprise 1400 (Series 438)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Enterprise 1500 (Series 467)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Enterprise 1600 (Series 471)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Elite 1500 (Series 467)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Elite 1600 (Series 493)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Express 100 (Series 466WS)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Express 200 (Series 466)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Express 300 (Series 490)</para>
 	</listitem>
 	<listitem>
 	  <para>MegaRAID Express 500 (Series 475)</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 2/SC</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 2/DC</para>
 	</listitem>
 	<listitem>
 	  <para>Dell PERC 3/DCL</para>
 	</listitem>
 	<listitem>
 	  <para>HP NetRaid-1si</para>
 	</listitem>
 	<listitem>
 	  <para>HP NetRaid-3si</para>
 	</listitem>
 	<listitem>
 	  <para>HP Embedded NetRaid</para>
 	</listitem>
       </itemizedlist>
 
       <note>
 	<para arch="i386">Booting from these controllers is supported.  EISA
 	adapters are not supported.</para>
 
 	<para arch="alpha">Booting from these controllers is not
 	supported due to SRM limitations.</para>
       </note>
     </para>
 
     <para arch="i386,alpha">Mylex DAC960 and DAC1100 RAID controllers with 2.x, 3.x, 4.x
     and 5.x firmware (&man.mlx.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>DAC960P</para>
 	</listitem>
 	<listitem>
 	  <para>DAC960PD</para>
 	</listitem>
 	<listitem>
 	  <para>DAC960PDU</para>
 	</listitem>
 	<listitem>
 	  <para>DAC960PL</para>
 	</listitem>
 	<listitem>
 	  <para>DAC960PJ</para>
 	</listitem>
 	<listitem>
 	  <para>DAC960PG</para>
 	</listitem>
 	<listitem>
 	  <para>AcceleRAID 150</para>
 	</listitem>
 	<listitem>
 	  <para>AcceleRAID 250</para>
 	</listitem>
 	<listitem>
 	  <para>eXtremeRAID 1100</para>
 	</listitem>
       </itemizedlist>
 
       <note>
 	<para arch="i386">Booting from these controllers is supported. EISA adapters
 	are not supported.</para>
 
 	<para arch="alpha">Booting from these controllers is not
 	supported due to SRM limitations.  This list includes
 	controllers sold by Digital/Compaq in Alpha systems in the
 	StorageWorks family, e.g. KZPSC or KZPAC.</para>
       </note>
     </para>
 
     <para arch="i386">Mylex PCI to SCSI RAID controllers with 6.x firmware
     (&man.mly.4; driver)
       <itemizedlist>
         <listitem>
           <para>AcceleRAID 160</para>
         </listitem>
 	<listitem>
 	  <para>AcceleRAID 170</para>
         </listitem>
 	<listitem>
 	  <para>AcceleRAID 352</para>
         </listitem>
 	<listitem>
 	  <para>eXtremeRAID 2000</para>
         </listitem>
 	<listitem>
 	  <para>eXtremeRAID 3000</para>
         </listitem>
       </itemizedlist>
 
       <note>
 	<para>Compatible Mylex controllers not listed should work, but
 	have not been verified.</para>
       </note>
     </para>
 
     <para arch="i386">3ware Escalade ATA RAID controllers (&man.twe.4; driver)
       <itemizedlist>
         <listitem arch="i386">
           <para>5000 series</para>
 	</listitem>
 
         <listitem arch="i386">
           <para>6000 series</para>
 	</listitem>
 
         <listitem arch="i386">
           <para>7000 series</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">LSI/SymBios (formerly NCR) 53C810, 53C810a, 53C815, 53C825,
     53C825a, 53C860, 53C875, 53C875a, 53C876, 53C885, 53C895, 53C895a,
     53C896, 53C1010-33, 53C1010-66, 53C1000, 53C1000R PCI
     SCSI controllers, either embedded on motherboard or on add-on
     boards (&man.ncr.4; and &man.sym.4; drivers)
       <itemizedlist>
         <listitem>
 	  <para>ASUS SC-200, SC-896</para>
 	</listitem>
         <listitem>
 	  <para>Data Technology DTC3130 (all variants)</para>
 	</listitem>
         <listitem>
 	  <para>DawiControl DC2976UW</para>
 	</listitem>
         <listitem>
 	  <para>Diamond FirePort (all)</para>
 	</listitem>
         <listitem>
 	  <para>NCR cards (all)</para>
 	</listitem>
         <listitem>
 	  <para>Symbios cards (all)</para>
 	</listitem>
         <listitem>
 	  <para>Tekram DC390W, 390U, 390F, 390U2B, 390U2W, 390U3D, and
 	  390U3W</para>
 	</listitem>
         <listitem>
 	  <para>Tyan S1365</para>
 	</listitem>
       </itemizedlist>
     </para>      
         
     <para arch="i386">NCR 53C500 based PC-Card SCSI host adapters (ncv
     driver)
       <itemizedlist>
         <listitem>
           <para>IO DATA PCSC-DV</para>
         </listitem>
 	<listitem>
 	  <para>KME KXLC002 (TAXAN ICD-400PN, etc.), KXLC004</para>
         </listitem>
 	<listitem>
 	  <para>Macnica Miracle SCSI-II mPS110</para>
         </listitem>
 	<listitem>
 	  <para>Media Intelligent MSC-110, MSC-200</para>
         </listitem>
 	<listitem>
 	  <para>NEC PC-9801N-J03R</para>
         </listitem>
 	<listitem>
 	  <para>New Media Corporation BASICS SCSI</para>
         </listitem>
 	<listitem>
 	  <para>Qlogic Fast SCSI</para>
         </listitem>
 	<listitem>
 	  <para>RATOC REX-9530, REX-5572 (as SCSI only)</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">TMC 18C30, 18C50 based ISA/PC-Card SCSI host
     adapters (stg driver)
       <itemizedlist>
         <listitem>
           <para>Future Domain SCSI2GO</para>
         </listitem>
 	<listitem>
 	  <para>IBM SCSI PCMCIA Card</para>
         </listitem>
 	<listitem>
 	  <para>ICM PSC-2401 SCSI</para>
         </listitem>
 	<listitem>
 	  <para>Melco IFC-SC</para>
         </listitem>
 	<listitem>
 	  <para>RATOC REX-5536, REX-5536AM, REX-5536M,
 	  REX-9836A</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Qlogic controllers and variants (&man.isp.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Qlogic 1020, 1040 SCSI and Ultra SCSI host
 	  adapters</para>
 	</listitem>
 	<listitem>
 	  <para>Qlogic 1240 dual Ultra SCSI controllers</para>
 	</listitem>
 	<listitem>
 	  <para>Qlogic 1080 Ultra2 LVD and 1280 Dual Ultra2 LVD
 	  controllers</para>
 	</listitem>
 	<listitem>
 	  <para>Qlogic 12160 Ultra3 LVD controllers</para>
 	</listitem>
 	<listitem>
 	  <para>Qlogic 2100 and Qlogic 2200 Fibre Channel SCSI
 	  controllers</para>
 	</listitem>
 	<listitem>
 	  <para>Qlogic 2300 and Qlogic 2312 2-Gigabit Fibre Channel SCSI
 	  controllers</para>
 	</listitem>
 	<listitem>
 	  <para>Performance Technology SBS440 ISP1000 variants</para>
 	</listitem>
 	<listitem>
 	  <para>Performance Technology SBS450 ISP1040 variants</para>
 	</listitem>
 	<listitem>
 	  <para>Performance Technology SBS470 ISP2100 variants</para>
 	</listitem>
 	<listitem>
 	  <para>Antares Microsystems P-0033 ISP2100 variants</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">DTC 3290 EISA SCSI controller in 1542 emulation mode.</para>
 
     <para>Tekram DC390 and DC390T controllers, maybe other cards based
     on the AMD 53c974 as well (&man.amd.4; driver)</para>
 
     <para arch="i386">Workbit Ninja SCSI-3 based PC-Card SCSI host
     adapters (nsp driver)
       <itemizedlist>
         <listitem>
           <para>Alpha-Data AD-PCS201</para>
         </listitem>
 	<listitem>
 	  <para>IO DATA CBSC16</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Parallel to SCSI interfaces (&man.vpo.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>AIC 7110 SCSI controller (built-in to Iomega ZIP drive)</para>
         </listitem>
         <listitem>
 	  <para>Iomega Jaz Traveller interface</para>
         </listitem>
         <listitem>
 	  <para>Iomega MatchMaker SCSI interface (built-in to Iomega
 	  ZIP+ drive)</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">SCSI adapters utilizing the Command Interface
     for SCSI-3 Support (ciss driver)
       <itemizedlist>
 	<listitem>
 	  <para>Compaq Smart Array 5* series (5300, 5i, 532)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para>With all supported SCSI controllers, full support is
     provided for SCSI-I, SCSI-II, and SCSI-III peripherals, including
     hard disks, optical disks, tape drives (including DAT, 8mm
     Exabyte, Mammoth, and DLT), medium changers, processor target
     devices and CD-ROM drives.  WORM devices that support CD-ROM
     commands are supported for read-only access by the CD-ROM drivers
     (such as &man.cd.4;).  WORM/CD-R/CD-RW writing support is provided
     by &man.cdrecord.1;, which is a part of the
     <port>sysutils/cdrtools</port> port in the Ports Collection.</para>
 
     <para>The following CD-ROM type systems are supported at this
     time:
       <itemizedlist>
         <listitem>
           <para>SCSI interface (also includes ProAudio Spectrum and
           SoundBlaster SCSI) (&man.cd.4;)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Matsushita/Panasonic (Creative SoundBlaster)
 	  proprietary interface (562/563 models) (&man.matcd.4;)</para>
 	</listitem>
 	<listitem arch="i386">
 	  <para>Sony proprietary interface (all models) (&man.scd.4;)</para>
 	</listitem>
 	<listitem>
 	  <para>ATAPI IDE interface (&man.acd.4;)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">The following drivers were supported under the old SCSI
     subsystem, but are not yet supported under the new CAM SCSI
     subsystem:
       <itemizedlist>
         <listitem>
 	  <para>NCR5380/NCR53400 (<quote>ProAudio Spectrum</quote>)
 	  SCSI controller</para>
 	</listitem>
         <listitem>
 	  <para>UltraStor 14F, 24F and 34F SCSI controllers.
 	    <note>
 	      <para>There is work-in-progress to port the
               UltraStor driver to the new CAM SCSI framework, but no
               estimates on when or if it will be completed.</para>
             </note>
           </para>
 	</listitem>
         <listitem>
 	  <para>Seagate ST01/02 SCSI controllers</para>
 	</listitem>
         <listitem>
 	  <para>Future Domain 8xx/950 series SCSI controllers</para>
 	</listitem>
         <listitem>
 	  <para>WD7000 SCSI controller</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">The following device is unmaintained:
       <itemizedlist>
         <listitem>
 	  <para>Mitsumi proprietary CD-ROM interface (all
 	  models) (&man.mcd.4;)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
   </sect2>
   <sect2 id="ethernet">
     <title>Ethernet Interfaces</title>
 
     <para arch="i386,alpha">Adaptec Duralink PCI Fast Ethernet adapters based on the Adaptec
     AIC-6915 Fast Ethernet controller chip (&man.sf.4 driver)
       <itemizedlist>
         <listitem>
           <para>ANA-62011 64-bit single port 10/100baseTX adapter</para>
         </listitem>
 	<listitem>
 	  <para>ANA-62022 64-bit dual port 10/100baseTX adapter</para>
         </listitem>
 	<listitem>
 	  <para>ANA-62044 64-bit quad port 10/100baseTX adapter</para>
         </listitem>
 	<listitem>
 	  <para>ANA-69011 32-bit single port 10/100baseTX
 	  adapter</para>
         </listitem>
 	<listitem>
 	  <para>ANA-62020 64-bit single port 100baseFX adapter</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Allied-Telesis AT1700 and RE2000 cards
     (&man.fe.4; driver)</para>
 
     <para arch="i386">Alteon Networks PCI Gigabit Ethernet NICs based on the Tigon
     1 and Tigon 2 chipsets (&man.ti.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>3Com 3c985-SX (Tigon 1 and 2)</para>
         </listitem>
         <listitem>
           <para>Alteon AceNIC (Tigon 1 and 2)</para>
         </listitem>
         <listitem>
           <para>Alteon AceNIC 1000baseT (Tigon 2)</para>
         </listitem>
 	<listitem>
 	  <para>Asante PCI 1000BASE-SX Gigabit Ethernet Adapter</para>
 	</listitem>
 	<listitem>
 	  <para>Asante GigaNIX1000T Gigabit Ethernet Adapter</para>
 	</listitem>
 	<listitem>
 	  <para>DEC/Compaq EtherWORKS 1000</para>
         </listitem>
 	<listitem>
 	  <para>Farallon PN9000SX</para>
 	</listitem>
 	<listitem>
 	  <para>NEC Gigabit Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>Netgear GA620 (Tigon 2)</para>
         </listitem>
 	<listitem>
 	  <para>Netgear GA620T (Tigon 2, 1000baseT)</para>
         </listitem>
 	<listitem>
 	  <para>Silicon Graphics Gigabit Ethernet</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">AMD PCnet NICs (&man.lnc.4; and &man.pcn.4; drivers)
       <itemizedlist>
         <listitem>
           <para>AMD PCnet/PCI (79c970 & 53c974 or 79c974)</para>
         </listitem>
         <listitem>
           <para>AMD PCnet/FAST</para>
         </listitem>
 	<listitem>
 	  <para>Isolan AT 4141-0 (16 bit)</para>
 	</listitem>
 	<listitem>
 	  <para>Isolink 4110 (8 bit)</para>
 	</listitem>
         <listitem>
           <para>PCnet/FAST+</para>
         </listitem>
         <listitem>
           <para>PCnet/FAST III</para>
         </listitem>
         <listitem>
           <para>PCnet/PRO</para>
         </listitem>
         <listitem>
           <para>PCnet/Home</para>
         </listitem>
         <listitem>
           <para>HomePNA</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">SMC 83c17x (EPIC)-based Ethernet NICs (&man.tx.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>SMC EtherPower II 9432 series</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">National Semiconductor DS8390-based Ethernet NICs, including
     Novell NE2000 and clones
     (&man.ed.4; driver)
       <itemizedlist>
         <listitem arch="i386,alpha">
 	  <para>3C503 Etherlink II (&man.ed.4; driver)</para>
         </listitem>
         <listitem arch="i386">
 	  <para>DEC Etherworks DE305</para>
         </listitem>
 	<listitem arch="i386">
 	  <para>Hewlett-Packard PC Lan+ 27247B and 27252A</para>
 	</listitem>
         <listitem>
 	  <para>NetVin 5000</para>
         </listitem>
         <listitem>
           <para>Novell NE1000, NE2000, and NE2100</para>
 	</listitem>
         <listitem>
 	  <para>RealTek 8029</para>
         </listitem>
         <listitem>
 	  <para>SMC Elite 16 WD8013 Ethernet interface</para>
 	</listitem>
         <listitem>
 	  <para>SMC Elite Ultra</para>
 	</listitem>
         <listitem>
 	  <para>SMC WD8003E, WD8003EBT, WD8003W, WD8013W, WD8003S,
 	  WD8003SBT and WD8013EBT and clones</para>
 	</listitem>
         <listitem>
 	  <para>Surecom NE-34</para>
         </listitem>
         <listitem>
 	  <para>VIA VT86C926</para>
         </listitem>
         <listitem>
 	  <para>Winbond W89C940</para>
         </listitem>
       </itemizedlist>
     </para>    
 
     <para arch="i386">NE2000 compatible PC-Card (PCMCIA) Ethernet and
     FastEthernet cards (&man.ed.4; driver)
       <itemizedlist>
         <listitem>
           <para>AR-P500 Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>Accton EN2212/EN2216/UE2216</para>
         </listitem>
 	<listitem>
 	  <para>Allied Telesis CentreCOM LA100-PCM_V2</para>
         </listitem>
 	<listitem>
 	  <para>AmbiCom 10BaseT card</para>
         </listitem>
 	<listitem>
 	  <para>BayNetworks NETGEAR FA410TXC Fast Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>CNet BC40 adapter</para>
         </listitem>
 	<listitem>
 	  <para>COREGA Ether PCC-T/EtherII PCC-T/FEther PCC-TXF/PCC-TXD</para>
         </listitem>
 	<listitem>
 	  <para>Compex Net-A adapter</para>
         </listitem>
 	<listitem>
 	  <para>CyQ've ELA-010</para>
         </listitem>
 	<listitem>
 	  <para>D-Link DE-650/660</para>
         </listitem>
 	<listitem>
 	  <para>Danpex EN-6200P2</para>
         </listitem>
 	<listitem>
 	  <para>Elecom Laneed LD-CDL/TX</para>
         </listitem>
 	<listitem>
 	  <para>IO DATA PCLATE</para>
         </listitem>
 	<listitem>
 	  <para>IBM Creditcard Ethernet I/II</para>
         </listitem>
 	<listitem>
 	  <para>IC-CARD Ethernet/IC-CARD+ Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>Linksys EC2T/PCMPC100,EtherFast 10/100 PC Card
 	  (PCMPC100 V2)</para>
         </listitem>
 	<listitem>
 	  <para>Melco LPC-T/LPC2-T/LPC2-CLT/LPC2-TX/LPC3-TX/LPC3-CLX</para>
         </listitem>
 	<listitem>
 	  <para>NDC Ethernet Instant-Link</para>
         </listitem>
 	<listitem>
 	  <para>National Semiconductor InfoMover NE4100</para>
         </listitem>
 	<listitem>
 	  <para>NetGear FA-410TX</para>
 	</listitem>
 	<listitem>
 	  <para>Network Everywhere Ethernet 10BaseT PC Card</para>
         </listitem>
 	<listitem>
 	  <para>Planex FNW-3600-T</para>
         </listitem>
 	<listitem>
 	  <para>Socket LP-E</para>
         </listitem>
 	<listitem>
 	  <para>Surecom EtherPerfect EP-427</para>
         </listitem>
 	<listitem>
 	  <para>TDK LAK-CD031,Grey Cell GCS2000 Ethernet Card</para>
         </listitem>
 	<listitem>
 	  <para>Telecom Device SuperSocket RE450T</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">RealTek RTL 8002 Pocket Ethernet (&man.rdp.4;
     driver)</para>
 
     <para arch="i386,alpha">RealTek 8129/8139 Fast Ethernet NICs (&man.rl.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>Accton <quote>Cheetah</quote> EN1207D (MPX 5030/5038;
 	  RealTek 8139 clone)</para>
         </listitem>
         <listitem>
           <para>Allied Telesyn AT2550</para>
         </listitem>
 	<listitem>
 	  <para>Allied Telesyn AT2500TX</para>
         </listitem>
 	<listitem>
 	  <para>D-Link DFE-538TX</para>
 	</listitem>
         <listitem>
           <para>Farallon NetLINE 10/100 PCI</para>
         </listitem>
 	<listitem>
 	  <para>Genius GF100TXR (RTL8139)</para>
         </listitem>
 	<listitem>
 	  <para>KTX-9130TX 10/100 Fast Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>NDC Communications NE100TX-E</para>
         </listitem>
 	<listitem>
 	  <para>Netronix Inc. EA-1210 NetEther 10/100</para>
         </listitem>
 	<listitem>
 	  <para>OvisLink LEF-8129TX</para>
         </listitem>
 	<listitem>
 	  <para>OvisLink LEF-8139TX</para>
         </listitem>
 	<listitem>
 	  <para>SMC EZ Card 10/100 PCI 1211-TX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Lite-On 82c168/82c169 PNIC Fast Ethernet NICs (&man.dc.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>Kingston KNE110TX</para>
         </listitem>
         <listitem>
           <para>LinkSys EtherFast LNE100TX</para>
         </listitem>
 	<listitem>
 	  <para>Matrox FastNIC 10/100</para>
         </listitem>
 	<listitem>
 	  <para>NetGear FA310-TX Rev. D1</para>
         </listitem>
       </itemizedlist
     </para>
 
     <para arch="i386,alpha">Macronix 98713, 98713A, 98715, 98715A and 98725 Fast
     Ethernet NICs (&man.dc.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>Accton EN1217 (98715A)</para>
         </listitem>
 	<listitem>
 	  <para>Adico AE310TX (98715A)</para>
         </listitem>
 	<listitem>
 	  <para>Compex RL100-TX (98713 or 98713A)</para>
         </listitem>
 	<listitem>
 	  <para>CNet Pro120A (98713 or 98713A)</para>
         </listitem>
 	<listitem>
 	  <para>CNet Pro120B (98715)</para>
         </listitem>
         <listitem>
           <para>NDC Communications SFA100A (98713A)</para>
         </listitem>
 	<listitem>
 	  <para>SVEC PN102TX (98713)</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Macronix/Lite-On PNIC II LC82C115 Fast Ethernet NICs
     (&man.dc.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>LinkSys EtherFast LNE100TX Version 2</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Winbond W89C840F Fast Ethernet NICs (&man.wb.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Trendware TE100-PCIE</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">VIA Technologies VT3043 <quote>Rhine I</quote> and VT86C100A
     <quote>Rhine II</quote> Fast Ethernet NICs (&man.vr.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>AOpen/Acer ALN-320</para>
         </listitem>
         <listitem>
 	  <para>D-Link DFE-530TX</para>
         </listitem>
         <listitem>
 	  <para>Hawking Technologies PN102TX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Silicon Integrated Systems SiS 900 and SiS 7016 PCI Fast
     Ethernet NICs (&man.sis.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>SiS 635 and 735 motherboard chipsets</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">National Semiconductor DP83815 Fast Ethernet NICs
     (&man.sis.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>NetGear FA311-TX</para>
         </listitem>
         <listitem>
 	  <para>NetGear FA312-TX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">National Semiconductor DP83820 and DP83821 Gigabit Ethernet
     NICs (&man.nge.4 driver)
       <itemizedlist>
         <listitem>
 	  <para>Addtron AEG320T</para>
         </listitem>
         <listitem>
 	  <para>Asante FriendlyNet GigaNIC 1000TA and 1000TPC</para>
         </listitem>
         <listitem>
 	  <para>D-Link DGE-500T</para>
         </listitem>
         <listitem>
 	  <para>LinkSys EG1032 (32-bit PCI) and EG1064 (64-bit PCI)</para>
         </listitem>
         <listitem>
 	  <para>Netgear GA622T</para>
         </listitem>
         <listitem>
 	  <para>SMC EZ Card 1000 (SMC9462TX)</para>
         </listitem>
         <listitem>
 	  <para>Surecom Technology EP-320G-TX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Sundance Technologies ST201 PCI Fast Ethernet NICs
     (&man.ste.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>D-Link DFE-550TX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">SysKonnect SK-984x PCI Gigabit Ethernet cards (&man.sk.4 drivers)
       <itemizedlist>
         <listitem>
 	  <para>SK-9821 1000baseT copper, single port</para>
         </listitem>
         <listitem>
 	  <para>SK-9822 1000baseT copper, dual port</para>
         </listitem>
         <listitem>
 	  <para>SK-9841 1000baseLX single mode fiber, single port</para>
         </listitem>
         <listitem>
 	  <para>SK-9842 1000baseLX single mode fiber, dual port</para>
         </listitem>
         <listitem>
 	  <para>SK-9843 1000baseSX multimode fiber, single port</para>
         </listitem>
         <listitem>
 	  <para>SK-9844 1000baseSX multimode fiber, dual port</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Texas Instruments ThunderLAN PCI NICs (&man.tl.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Compaq Netelligent 10, 10/100, 10/100
 	  Dual-Port</para>
         </listitem>
         <listitem arch="i386">
 	  <para>Compaq Netelligent 10/100 Proliant</para>
         </listitem>
         <listitem>
 	  <para>Compaq Netelligent 10/100 TX Embedded UTP, 10 T PCI
 	  UTP/Coax, 10/100 TX UTP</para>
         </listitem>
         <listitem>
 	  <para>Compaq NetFlex 3P, 3P Integrated, 3P w/BNC</para>
         </listitem>
         <listitem>
 	  <para>Olicom OC-2135/2138, OC-2325, OC-2326 10/100 TX UTP</para>
         </listitem>
         <listitem>
 	  <para>Racore 8165 10/100baseTX</para>
         </listitem>
         <listitem>
 	  <para>Racore 8148 10baseT/100baseTX/100baseFX
 	  multi-personality</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">ADMtek Inc. AL981-based PCI Fast Ethernet NICs (&man.dc.4;
     driver)</para>
 
     <para arch="i386,alpha">ADMtek Inc. AN985-based PCI Fast Ethernet NICs (&man.dc.4;
     driver)
       <itemizedlist>
         <listitem>
 	  <para>LinkSys EtherFast LNE100TX v4.0/4.1</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">ADMtek Inc. AN986-based USB Ethernet NICs (&man.aue.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Billionton USB100</para>
         </listitem>
         <listitem>
 	  <para>D-Link DSB-650TX</para>
         </listitem>
         <listitem>
 	  <para>LinkSys USB100TX</para>
         </listitem>
         <listitem>
 	  <para>Melco Inc. LUA-TX</para>
         </listitem>
         <listitem>
 	  <para>SMC 2202USB</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">CATC USB-EL1210A-based USB Ethernet NICs (&man.cue.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Belkin F5U011</para>
         </listitem>
         <listitem>
 	  <para>Belkin F5U111</para>
         </listitem>
         <listitem>
 	  <para>CATC Netmate</para>
         </listitem>
         <listitem>
 	  <para>CATC Netmate II</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Kawasaki LSI KU5KUSB101B-based USB Ethernet NICs
     (&man.kue.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>3Com 3c19250</para>
         </listitem>
 	<listitem>
 	  <para>Abocom URE 450</para>
         </listitem>
 	<listitem>
 	  <para>ADS Technologies USB-10BT</para>
         </listitem>
 	<listitem>
 	  <para>ATen UC10T</para>
         </listitem>
 	<listitem>
 	  <para>Corega USB-T</para>
         </listitem>
 	<listitem>
 	  <para>D-Link DSB-650</para>
         </listitem>
 	<listitem>
 	  <para>Entrega NET-USB-E45</para>
         </listitem>
         <listitem>
           <para>LinkSys USB10T</para>
         </listitem>
 	<listitem>
 	  <para>Netgear EA101</para>
         </listitem>
 	<listitem>
 	  <para>Peracom USB Ethernet Adapter</para>
         </listitem>
 	<listitem>
 	  <para>SMC 2102USB</para>
         </listitem>
 	<listitem>
 	  <para>SMC 2104USB</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">ASIX Electronics AX88140A PCI NICs (&man.dc.4; driver)
       <itemizedlist>
         <listitem>
           <para>Alfa Inc. GFC2204</para>
         </listitem>
 	<listitem>
 	  <para>CNet Pro110B</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">DEC EtherWORKS II and III NICs (&man.le.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>DE200, DE201, DE202, DE422</para>
 	</listitem>
         <listitem>
 	  <para>DE203, DE204, DE205</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">DEC DC21040, DC21041, DC21140, DC21141, DC21142, and DC21143
     based NICs (&man.de.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Asante</para>
         </listitem>
         <listitem>
 	  <para>Cogent EM100FX and EM440TX</para>
         </listitem>
         <listitem>
 	  <para>DEC DE425, DE435, DE450, and DE500</para>
         </listitem>
         <listitem>
 	  <para>SMC Etherpower 8432T, 9332, and 9334</para>
         </listitem>
 	<listitem>
 	  <para>ZYNX ZX 3xx</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">DEC/Intel 21143 based Fast Ethernet NICs (&man.dc.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>DEC DE500</para>
 	</listitem>
         <listitem>
           <para>Compaq Presario 7900 series built-in Ethernet</para>
         </listitem>
         <listitem>
 	  <para>D-Link DFE-570TX</para>
         </listitem>
         <listitem>
 	  <para>Kingston KNE100TX</para>
         </listitem>
         <listitem>
 	  <para>LinkSys EtherFast 10/100 Instant GigaDrive built-in Ethernet</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Davicom DM9100 and DM9102 PCI Fast Ethernet NICs (&man.dc.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Jaton Corporation XpressNet</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Conexant LANfinity RS7112 (MiniPCI) (&man.dc.4; driver)</para>
 
     <para arch="i386">Fujitsu MB86960A/MB86965A based Fast Ethernet NICs
     (&man.fe.4; driver)
       <itemizedlist>
         <listitem>
           <para>CONTEC C-NET(PC)C Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>Eiger Labs EPX-10BT</para>
         </listitem>
 	<listitem>
 	  <para>Fujitsu FMV-J182, FMV-J182A, MBH10302, MBH10303
 	  Ethernet PCMCIA</para>
         </listitem>
 	<listitem>
 	  <para>Fujitsu Towa LA501 Ethernet</para>
         </listitem>
 	<listitem>
 	  <para>HITACHI HT-4840-11</para>
         </listitem>
 	<listitem>
 	  <para>NextCom J Link NC5310</para>
         </listitem>
 	<listitem>
 	  <para>RATOC REX-5588, REX-9822, REX-4886, REX-R280</para>
         </listitem>
 	<listitem>
 	  <para>TDK LAK-CD021, LAK-CD021A, LAK-CD021BX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Intel 82557- or 82559-based Fast Ethernet NICs (&man.fxp.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Intel EtherExpress Pro/100B PCI Fast Ethernet</para>
         </listitem>
         <listitem>
 	  <para>Intel InBusiness 10/100 PCI Network Adapter</para>
         </listitem>
         <listitem>
 	  <para>Intel PRO/100+ Management Adapter</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Intel 82595-based Ethernet NICs (&man.ex.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Intel EtherExpress Pro/10 and Pro/10+ Ethernet</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Intel 82586-based Ethernet NICs (&man.ie.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>3Com 3C507 Etherlink 16/TP</para>
         </listitem>
         <listitem>
 	  <para>AT&amp;T Starlan 10 and Starlan Fiber</para>
         </listitem>
         <listitem>
 	  <para>EN100</para>
         </listitem>
         <listitem>
 	  <para>Intel EtherExpress 16</para>
         </listitem>
         <listitem>
 	  <para>RACAL Interlan NI5210</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">3Com 3C5x9 Etherlink III NICs (&man.ep.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>3C509</para>
         </listitem>
         <listitem>
 	  <para>3C529 MCA</para>
         </listitem>
         <listitem>
 	  <para>3C579 EISA</para>
         </listitem>
         <listitem>
 	  <para>3C589/589B/589C/589D/589E/XE589ET/574TX/574B
 	  PC-card/PCMCIA</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">3Com 3C501 8-bit ISA Ethernet NIC 
     (&man.el.4; driver)</para>
 
     <para arch="i386,alpha">3Com Etherlink XL-based NICs (&man.xl.4; driver)
       <itemizedlist>
 	<listitem>
 	  <para>3C900/905/905B/905C PCI</para>
         </listitem>
         <listitem>
 	  <para>3C556/556B MiniPCI</para>
         </listitem>
         <listitem>
 	  <para>3C450-TX HomeConnect adapter</para>
         </listitem>
         <listitem>
 	  <para>3c980/3c980B Fast Etherlink XL server adapter</para>
         </listitem>
         <listitem>
 	  <para>3cSOHO100-TX OfficeConnect adapter</para>
         </listitem>
         <listitem>
 	  <para>Dell Optiplex GX1 on-board 3C918</para>
         </listitem>
         <listitem>
 	  <para>Dell On-board 3C920</para>
         </listitem>
         <listitem>
 	  <para>Dell Precision on-board 3C905B</para>
         </listitem>
         <listitem>
 	  <para>Dell Latitude laptop docking station embedded 3C905-TX</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">3Com 3C59X series NICs (&man.vx.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>3C590 Etherlink III (PCI)</para>
 	</listitem>
         <listitem>
 	  <para>3C595 Fast Etherlink III (PCI)</para>
 	</listitem>
         <listitem>
 	  <para>3C592/3C597 (EISA)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Crystal Semiconductor CS89x0-based NICs 
     (&man.cs.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>IBM Etherjet ISA</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Megahertz X-Jack Ethernet PC-Card CC-10BT (sn
     driver)</para>
 
     <para arch="i386">Xircom CreditCard adapters (16 bit) and
     workalikes (xe driver)
       <itemizedlist>
 	<listitem>
 	  <para>Accton EN2226/Fast EtherCard (16-bit verison)</para>
         </listitem>
 	<listitem>
 	  <para>Compaq Netelligent 10/100 PC Card</para>
         </listitem>
 	<listitem>
 	  <para>Intel EtherExpress PRO/100 Mobile Adapter (16-bit
 	  verison)</para>
         </listitem>
 	<listitem>
 	  <para>Xircom 10/100 Network PC Card adapter</para>
         </listitem>
 	<listitem>
 	  <para>Xircom Realport card + modem(Ethernet part)</para>
         </listitem>
 	<listitem>
 	  <para>Xircom CreditCard Ethernet 10/100</para>
         </listitem>
 	<listitem>
 	  <para>Xircom CreditCard 10Base-T <quote>CreditCard Ethernet
 	  Adapter IIps</quote> (PS-CE2-10)</para>
         </listitem>
 	<listitem>
 	  <para>Xircom CreditCard Ethernet 10/100 + modem (Ethernet
 	  part)</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">National Semiconductor DP8393X (SONIC) Ethernet
     cards (snc driver)
       <itemizedlist>
         <listitem>
 	  <para>NEC PC-9801-83, -84, -103, and -104</para>
         </listitem>
         <listitem>
 	  <para>NEC PC-9801N-25 and -J02R</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Gigabit Ethernet cards based on the Level 1
     LXT1001 NetCellerator controller (&man.lge.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>D-Link DGE-500SX</para>
 	</listitem>
         <listitem>
 	  <para>SMC TigerCard 1000 (SMC9462SX)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Ethernet and Fast Ethernet NICs based on the 3Com
     3XP Typhoon/Sidewinder (3CR990) chipset (&man.txp.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>3Com 3CR990-TX-95</para>
         </listitem>
         <listitem>
 	  <para>3Com 3CR990-TX-97</para>
         </listitem>
         <listitem>
 	  <para>3Com 3CR990B-SRV</para>
         </listitem>
         <listitem>
 	  <para>3Com 3CR990B-TXM</para>
         </listitem>
         <listitem>
 	  <para>3Com 3CR990SVR95</para>
         </listitem>
         <listitem>
 	  <para>3Com 3CR990SVR97</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Gigabit Ethernet NICs based on the Broadcom BCM570x
     (&man.bge.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>3Com 3c996-T</para>
         </listitem>
         <listitem>
+	  <para>Netgear GA302T</para>
+        </listitem>
+        <listitem>
 	  <para>SysKonnect SK-9D21 and 9D41</para>
         </listitem>
         <listitem>
 	  <para>Built-in Gigabit Ethernet NICs on DELL PowerEdge 2550
 	  servers</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Gigabit Ethernet NICs based on the Intel 82542 and 82543
     controller chips (&man.wx.4;, &man.gx.4; and &man.em.4; drivers)
       <itemizedlist>
 	<listitem>
 	  <para>Intel PRO/1000 Gigabit Ethernet</para>
 	</listitem>
       </itemizedlist>
 
       <note>
         <para>The &man.wx.4; driver is deprecated.</para>
       </note>
 
       <note>
         <para>The &man.em.4; driver is officially supported by Intel, but
         is only supported on the i386.</para>
       </note>
 
     </para>
   </sect2>
 
   <sect2>
     <title>FDDI Interfaces</title>
     <para arch="i386,alpha">DEC DEFPA PCI (&man.fpa.4; driver)</para>
     <para arch="i386">DEC DEFEA EISA (&man.fpa.4; driver)</para>
   </sect2>
 
   <sect2>
     <title>ATM Interfaces</title>
     <para arch="i386">Efficient Networks, Inc. ENI-155p ATM PCI Adapters
     (hea driver)</para>
     <para arch="i386">FORE Systems, Inc. PCA-200E ATM PCI Adapters (hfa driver)</para>
     <para arch="i386">The ATM support in &os; supports the following signaling
     protocols:
       <itemizedlist>
         <listitem>
 	  <para>The ATM Forum UNI 3.1 signaling protocol</para>
 	</listitem>
 	<listitem>
           <para>The ATM Forum UNI 3.0 signaling protocol</para>
 	</listitem>
 	<listitem>
           <para>The ATM Forum ILMI address registration</para>
 	</listitem>
 	<listitem>
           <para>FORE Systems' proprietary SPANS signaling protocol</para>
 	</listitem>
 	<listitem>
           <para>Permanent Virtual Channels (PVCs)</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Support for the IETF <quote>Classical IP and ARP over
     ATM</quote> model is provided, compliant with the following RFCs
     and Internet Drafts:
       <itemizedlist>
         <listitem>
           <para>RFC 1483, <quote>Multiprotocol Encapsulation over ATM
           Adaptation Layer 5</quote></para>
 	</listitem>
         <listitem>
           <para>RFC 1577, <quote>Classical IP and ARP over ATM</quote></para>
         </listitem>
         <listitem>
           <para>RFC 1626, <quote>Default IP MTU for use over ATM
           AAL5</quote></para>
         </listitem>
         <listitem>
           <para>RFC 1755, <quote>ATM Signaling Support for IP over ATM</quote></para>
         </listitem>
         <listitem>
           <para>RFC 2225, <quote>Classical IP and ARP over ATM</quote></para>
         </listitem>
         <listitem>
           <para>RFC 2334, <quote>Server Cache Synchronization Protocol
 	  (SCSP)</quote></para>
         </listitem>
         <listitem>
 	  <para>Internet Draft
 	  <filename>draft-ietf-ion-scsp-atmarp-00.txt</filename>, <quote>A
 	  Distributed ATMARP Service Using SCSP</quote></para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Support for an ATM sockets interface is also provided.</para>
   </sect2>
   <sect2>
     <title>Wireless Network Interfaces</title>
 
     <para arch="i386">NCR / AT&amp;T / Lucent Technologies WaveLan T1-speed
     ISA/radio LAN cards (&man.wl.4; driver)</para>
 
     <para arch="i386">Lucent Technologies WaveLAN/IEEE 802.11 PCMCIA and ISA
     standard speed (2Mbps) and turbo speed (6Mbps) wireless network
     adapters and workalikes (&man.wi.4; driver)
       <note>
         <para>The ISA versions of these adapters are actually PCMCIA
         cards combined with an ISA to PCMCIA bridge card, so both kinds
         of devices work with the same driver.</para>
       </note>
       <itemizedlist>
         <listitem>
 	<para>NCR WaveLAN/IEEE 802.11</para>
 	</listitem>
 	<listitem>
 	<para>3COM 3crwe737A AirConnect Wireless LAN PC Card</para>
 	</listitem>
 	<listitem>
 	<para>Addtron AWA100</para>
 	</listitem>
 	<listitem>
 	<para>Cabletron RoamAbout 802.11 DS</para>
 	</listitem>
 	<listitem>
 	<para>Compaq WL100</para>
 	</listitem>
 	<listitem>
 	<para>Corega KK Wireless LAN PCC-11</para>
 	</listitem>
 	<listitem>	
 	<para>ELECOM Air@Hawk/LD-WL11/PCC</para>
 	</listitem>
 	<listitem>
 	<para>Farallon Skyline 11Mbps Wireless</para>
 	</listitem>
 	<listitem>
 	<para>ICOM SL-1100</para>
 	</listitem>
 	<listitem>
 	<para>Laneed Wireless card</para>
 	</listitem>
 	<listitem>
 	<para>Melco Airconnect WLI-PCM-L11</para>
 	</listitem>
 	<listitem>
 	<para>NEC Wireless Card CMZ-RT-WP</para>
 	</listitem>
 	<listitem>
 	<para>PLANEX GeoWave/GW-NS110</para>
 	</listitem>
 	<listitem>
 	<para>TDK LAK-CD011WL</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Aironet 802.11 wireless adapters (&man.an.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Aironet 4500/4800 series
 	  (PCMCIA, PCI, and ISA adapters are all supported)</para>
         </listitem>
         <listitem>
 	  <para>Cisco Systems Aironet 340 and 350 series
 	  (PCMCIA, PCI, and ISA adapters are all supported)</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Raytheon Raylink 2.4GHz wireless adapters (&man.ray.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Webgear Aviator</para>
         </listitem>
         <listitem>
 	  <para>Webgear Aviator Pro</para>
         </listitem>
         <listitem>
 	  <para>Raylink PC Card</para>
         </listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">AMD Am79C930 and Harris (Intersil) based 802.11 cards (awi driver)
       <itemizedlist>
         <listitem>
 	  <para>BayStack 650 and 660</para>
 	</listitem>
         <listitem>
 	  <para>Farallon SkyLINE Wireless</para>
 	</listitem>
         <listitem>
 	  <para>Icom SL-200</para>
 	</listitem>
         <listitem>
 	  <para>Melco WLI-PCM</para>
 	</listitem>
         <listitem>
 	  <para>NEL SSMagic</para>
 	</listitem>
         <listitem>
 	  <para>Netwave AirSurfer Plus and AirSurfer Pro</para>
 	</listitem>
         <listitem>
 	  <para>ZoomAir 4000</para>
 	</listitem>
       </itemizedlist>
     </para>
 
   </sect2>
 
   <sect2>
     <title>Miscellaneous Networks</title>
 
     <para arch="i386">Granch SBNI12 point-to-point communications
     adapters (sbni driver)
       <itemizedlist>
         <listitem>
 	  <para>SBNI12-XX and SBNI12D-XX ISA and PCI</para>
 	</listitem>
       </itemizedlist>
     </para>
   </sect2>
 
   <sect2>
     <title>ISDN Interfaces</title>
     <para arch="i386">AcerISDN P10 ISA PnP (experimental)</para>
     <para arch="i386">Asuscom ISDNlink 128K ISA</para>
     <para arch="i386">ASUSCOM P-IN100-ST-D (and other Winbond W6692-based cards)</para>
     <para arch="i386">AVM
       <itemizedlist>
         <listitem>
 	  <para>A1</para>
 	</listitem>
         <listitem>
 	  <para>B1 ISA (tested with V2.0)</para>
 	</listitem>
         <listitem>
 	  <para>B1 PCI (tested with V4.0)</para>
 	</listitem>
         <listitem>
 	  <para>Fritz!Card classic</para>
 	</listitem>
         <listitem>
 	  <para>Fritz!Card PnP</para>
 	</listitem>
         <listitem>
 	  <para>Fritz!Card PCI</para>
 	</listitem>
         <listitem>
 	  <para>T1</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Creatix
       <itemizedlist>
         <listitem>
 	  <para>ISDN-S0</para>
 	</listitem>
         <listitem>
 	  <para>ISDN-S0 P&amp;P</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Compaq Microcom 610 ISDN (Compaq series PSB2222I) ISA PnP</para>
     <para arch="i386">Dr. Neuhaus Niccy Go@ and compatibles</para>
     <para arch="i386">Dynalink IS64PH</para>
     <para arch="i386">Eicon Diehl DIVA 2.0 and 2.02</para>
     <para arch="i386">ELSA
       <itemizedlist>
         <listitem>
 	  <para>ELSA PCC-16</para>
 	</listitem>
         <listitem>
 	  <para>QuickStep 1000pro ISA</para>
 	</listitem>
         <listitem>
 	  <para>MicroLink ISDN/PCI</para>
 	</listitem>
         <listitem>
 	  <para>QuickStep 1000pro PCI</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">ITK ix1 Micro ( &lt; V.3, non-PnP version )</para>
     <para arch="i386">Sedlbauer Win Speed</para>
     <para arch="i386">Siemens I-Surf 2.0</para>
     <para arch="i386">TELEINT ISDN SPEED No.1 (experimental)</para>
     <para arch="i386">Teles
       <itemizedlist>
         <listitem>
 	  <para>S0/8</para>
 	</listitem>
         <listitem>
 	  <para>S0/16</para>
 	</listitem>
         <listitem>
 	  <para>S0/16.3</para>
 	</listitem>
         <listitem>
 	  <para>S0/16.3 PnP</para>
 	</listitem>
         <listitem>
 	  <para>16.3c ISA PnP (experimental)</para>
 	</listitem>
 	<listitem>
 	  <para>Teles PCI-TJ</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Traverse Technologies NETjet-S PCI</para>
     <para arch="i386">USRobotics Sportster ISDN TA intern</para>
     <para arch="i386">Winbond W6692 based PCI cards</para>
   </sect2>
 
   <sect2>
     <title>Multi-port Serial Interfaces</title>
     <para arch="i386,alpha">AST 4 port serial card using shared IRQ</para>
 
     <para arch="i386">ARNET serial cards (&man.ar.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>ARNET 8 port serial card using shared IRQ</para>
 	</listitem>
         <listitem>
 	  <para>ARNET (now Digiboard) Sync 570/i high-speed serial</para>
 	</listitem>
       </itemizedlist>
     </para>
     
     <para arch="i386">Boca multi-port serial cards
       <itemizedlist>
         <listitem>
 	  <para>Boca BB1004 4-Port serial card (Modems
 	  <emphasis>not</emphasis> supported)</para>
 	</listitem>
         <listitem>
 	  <para>Boca IOAT66 6-Port serial card (Modems supported)</para>
 	</listitem>
         <listitem>
 	  <para>Boca BB1008 8-Port serial card (Modems
 	  <emphasis>not</emphasis> supported)</para>
 	</listitem>
         <listitem>
 	  <para>Boca BB2016 16-Port serial card (Modems supported)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Comtrol Rocketport card (rp driver)</para>
 
     <para arch="i386">Cyclades Cyclom-y serial board (&man.cy.4; driver)</para>
 
     <para arch="i386">STB 4 port card using shared IRQ</para>
 
     <para arch="i386">DigiBoard intelligent serial cards (&man.dgb.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>DigiBoard PC/Xe series</para>
 	</listitem>
         <listitem>
 	  <para>DigiBoard PC/Xi series</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">SDL Communication serial boards
       <itemizedlist>
         <listitem>
 	  <para>SDL Communications Riscom/8 Serial Board (rc driver)</para>
 	</listitem>
         <listitem>
 	  <para>SDL Communications RISCom/N2 and N2pci high-speed sync
 	  serial boards (&man.sr.4; driver)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Stallion Technologies multiport serial boards
       <itemizedlist>
         <listitem>
 	  <para>EasyIO (&man.stl.4; driver)</para>
 	</listitem>
         <listitem>
 	  <para>EasyConnection 8/32 (&man.stl.4; driver)</para>
 	</listitem>
 	<listitem>
 	  <para>EasyConnection 8/64 (&man.stli.4; driver)</para>
 	</listitem>
         <listitem>
 	  <para>ONboard 4/16 (&man.stli.4; driver)</para>
 	</listitem>
         <listitem>
 	  <para>Brumby (&man.stli.4; driver)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386">Specialix SI/XIO/SX multiport serial cards, with both the
     older SIHOST2.x and the new <quote>enhanced</quote> (transputer
     based, aka JET) host cards (ISA, EISA and PCI are supported)
     (&man.si.4; driver)</para>
 
   </sect2>
   <sect2>
     <title>Audio Devices</title>
     <para arch="i386">Advance (&man.sbc.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Asound 100 and 110</para>
 	</listitem>
         <listitem>
 	  <para>Logic ALS120 and ALS4000</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">CMedia sound chips
       <itemizedlist>
         <listitem>
 	  <para>CMI8338/CMI8738</para>
         </listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Crystal Semiconductor (&man.csa.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>CS461x/462x Audio Accelerator</para>
 	</listitem>
 	<listitem>
 	  <para>CS428x Audio Controller</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">ENSONIQ (&man.pcm.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>AudioPCI ES1370/1371</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386,alpha">ESS
       <itemizedlist>
         <listitem>
 	  <para>ES1868, ES1869, ES1879 and ES1888 (&man.sbc.4; driver)</para>
 	</listitem>
         <listitem>
 	  <para>Maestro-1, Maestro-2, and Maestro-2E</para>
 	</listitem>
         <listitem>
 	  <para>Maestro-3/Allegro</para>
 	  <note>
 	    <para>The Maestro-3/Allegro cannot be compiled into the
 	    &os; kernel due to licensing restrictions.  To use this
 	    driver, add the following line to
 	    <filename>/boot/loader.conf</filename>:</para>
 
             <screen><userinput>snd_maestro3_load="YES"</userinput></screen>
 	  </note>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">ForteMedia fm801</para>
     <para arch="i386">Gravis (&man.gusc.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>UltraSound MAX</para>
 	</listitem>
         <listitem>
 	  <para>UltraSound PnP</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Intel 443MX, 810, 815, and 815E integrated sound
     devices (&man.pcm.4; driver)</para>
     <para arch="i386,alpha">MSS/WSS Compatible DSPs (&man.pcm.4; driver)</para>
     <para arch="i386">NeoMagic 256AV/ZX (&man.pcm.4; driver)</para>
     <para arch="i386">OPTi 931/82C931 (&man.pcm.4; driver)</para>
     <para arch="i386">S3 Sonicvibes</para>
     <para arch="i386,alpha">Creative Technologies SoundBlaster series (&man.sbc.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>SoundBlaster</para>
 	</listitem>
         <listitem>
 	  <para>SoundBlaster Pro</para>
 	</listitem>
         <listitem>
 	  <para>SoundBlaster AWE-32</para>
 	</listitem>
         <listitem>
 	  <para>SoundBlaster AWE-64</para>
 	</listitem>
         <listitem>
 	  <para>SoundBlaster AWE-64 GOLD</para>
 	</listitem>
         <listitem>
 	  <para>SoundBlaster ViBRA-16</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Trident 4DWave DX/NX (&man.pcm.4; driver)</para>
     <para arch="i386">VIA Technologies VT82C686A</para>
     <para arch="i386">Yamaha
       <itemizedlist>
         <listitem>
 	  <para>DS1</para>
 	</listitem>
         <listitem>
 	  <para>DS1e</para>
 	</listitem>
       </itemizedlist>
     </para>
   </sect2>
   <sect2>
     <title>Camera and Video Capture Devices</title>
     <para arch="i386">Brooktree Bt848/849/878/879-based frame grabbers (&man.bktr.4;
     driver)
       <itemizedlist>
         <listitem>
           <para>AverMedia cards</para>
         </listitem>
         <listitem>
           <para>Hauppauge Wincast TV and WinTV boards (PCI)</para>
 	</listitem>
         <listitem>
           <para>Intel Smart Video Recorder III</para>
 	</listitem>
         <listitem>
           <para>Miro PC TV</para>
 	</listitem>
         <listitem>
           <para>STB TV PCI</para>
         </listitem>
         <listitem>
           <para>Video Highway XTreme</para>
         </listitem>
         <listitem>
           <para>VideoLogic Captivator PCI</para>
         </listitem>
       </itemizedlist>
     </para>      
     <para arch="i386">Connectix QuickCam</para>
     <para arch="i386">Cortex1 frame grabber (ctx driver)</para>
     <para arch="i386">Creative Labs Video Spigot frame grabber (spigot driver)</para>
     <para arch="i386">Matrox Meteor Video frame grabber (&man.meteor.4; driver)</para>
   </sect2>
 
   <sect2 id="usb">
     <title>USB Devices</title>
 
     <para>A range of USB peripherals are supported; devices known to
     work are listed in this section.  Owing to the
     generic nature of most USB devices, with some exceptions any
     device of a given class will be supported, even if not explicitly
     listed here.</para>
 
     <note>
       <para>USB Ethernet adapters can be found in the section listing <link
       linkend="ethernet">Ethernet interfaces</link>.</para>
     </note>
 
     <para arch="i386,alpha">Host Controllers (&man.ohci.4; and &man.uhci.4; drivers)
       <itemizedlist>
         <listitem>
 	  <para>ALi Aladdin-V</para>
 	</listitem>
         <listitem>
 	  <para>AMD-756</para>
 	</listitem>
         <listitem>
 	  <para>CMD Tech 670 & 673</para>
 	</listitem>
         <listitem>
 	  <para>Intel 82371SB (PIIX3)</para>
 	</listitem>
         <listitem>
 	  <para>Intel 82371AB and EB (PIIX4)</para>
 	</listitem>
         <listitem>
 	  <para>Intel 82801AA (ICH)</para>
 	</listitem>
         <listitem>
 	  <para>Intel 82801AB (ICH0)</para>
 	</listitem>
         <listitem>
 	  <para>Intel 82801BA/BAM (ICH2)</para>
 	</listitem>
         <listitem>
 	  <para>Intel 82443MX</para>
 	</listitem>
         <listitem>
 	  <para>NEC uPD 9210</para>
 	</listitem>
         <listitem>
 	  <para>OPTi 82C861 (FireLink)</para>
 	</listitem>
         <listitem>
 	  <para>SiS 5571</para>
 	</listitem>
         <listitem>
 	  <para>VIA 83C572 USB</para>
 	</listitem>
         <listitem>
 	  <para>UHCI or OHCI compliant motherboard chipsets (no
 	  exceptions known)</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">USB host controllers (PCI)
       <itemizedlist>
         <listitem>
 	  <para>ADS Electronics PCI plug-in card (2 ports)</para>
 	</listitem>
         <listitem>
 	  <para>Entrega PCI plug-in card (4 ports)</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para>Hubs
       <itemizedlist>
         <listitem>
 	  <para>Andromeda hub</para>
 	</listitem>
         <listitem>
 	  <para>MacAlly self powered hub (4 ports)</para>
 	</listitem>
         <listitem>
 	  <para>NEC hub</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386,alpha">Keyboards (&man.ukbd.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Apple iMac keyboard</para>
 	</listitem>
         <listitem>
 	  <para>BTC BTC7935 keyboard with PS/2 mouse port</para>
 	</listitem>
         <listitem>
 	  <para>Cherry G81-3504 keyboard</para>
 	</listitem>
         <listitem>
 	  <para>Logitech M2452 keyboard</para>
 	</listitem>
         <listitem>
 	  <para>MacAlly iKey keyboard</para>
 	</listitem>
         <listitem>
 	  <para>Microsoft keyboard</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Miscellaneous
       <itemizedlist>
         <listitem>
 	  <para>ActiveWire I/O Board</para>
 	</listitem>
         <listitem>
 	  <para>Diamond Rio 500, 600, and 800 MP3 players (&man.urio.4; driver)</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Modems (umodem driver)
       <itemizedlist>
         <listitem>
 	  <para>3Com 5605</para>
 	</listitem>
         <listitem>
 	  <para>Metricom Ricochet GS USB wireless modem</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386,alpha">Mice (&man.ums.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Agiler Mouse 29UO</para>
 	</listitem>
         <listitem>
 	  <para>Apple iMac Mouse</para>
 	</listitem>
         <listitem>
 	  <para>Belkin Mouse</para>
 	</listitem>
         <listitem>
 	  <para>Chic mouse</para>
 	</listitem>
         <listitem>
 	  <para>Cypress mouse</para>
 	</listitem>
         <listitem>
 	  <para>Genius Niche mouse</para>
 	</listitem>
         <listitem>
 	  <para>Kensington Mouse-in-a-Box</para>
 	</listitem>
         <listitem>
 	  <para>Logitech wheel mouse (3 buttons)</para>
 	</listitem>
         <listitem>
 	  <para>Logitech PS/2 / USB mouse (3 buttons)</para>
 	</listitem>
         <listitem>
 	  <para>MacAlly mouse (3 buttons)</para>
 	</listitem>
         <listitem>
 	  <para>Microsoft IntelliMouse (3 buttons)</para>
 	</listitem>
         <listitem>
 	  <para>Trust Ami Mouse (3 buttons)</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386,alpha">Printers and parallel printer conversion cables (ulpt driver)
       <itemizedlist>
         <listitem>
 	  <para>ATen parallel printer adapter</para>
 	</listitem>
         <listitem>
 	  <para>Belkin F5U002 parallel printer adapter</para>
 	</listitem>
         <listitem>
 	  <para>Entrega USB-to-parallel printer adapter</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Scanners (through SANE) (&man.uscanner.4; driver)
       <itemizedlist>
         <listitem>
 	  <para>Perfection 636U</para>
 	</listitem>
         <listitem>
 	  <para>HP ScanJet 4100C, 5200C, 6300C</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386,alpha">Storage (&man.umass.4; driver)
       <itemizedlist>
         <listitem arch="i386">
 	  <para>Iomega USB Zip 100Mb (primitive support still)</para>
 	</listitem>
         <listitem>
 	  <para>Matshita CF-VFDU03 floppy drive</para>
 	</listitem>
         <listitem>
 	  <para>Microtech USB-SCSI-HD 50 USB to SCSI cable</para>
 	</listitem>
         <listitem>
 	  <para>Panasonic floppy drive</para>
 	</listitem>
         <listitem>
 	  <para>Y-E Data floppy drive (720/1.44/2.88Mb)</para>
 	</listitem>
       </itemizedlist>
     </para>
   </sect2>
 
   <sect2>
     <title>Miscellaneous</title>
 
     <para arch="i386">FAX-Modem/PCCARD
       <itemizedlist>
         <listitem>
 	  <para>Melco IGM-PCM56K/IGM-PCM56KH</para>
 	</listitem>
         <listitem>
 	  <para>Nokia Card Phone 2.0 (gsm900/dcs1800 HSCSD terminal)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Floppy drives (&man.fd.4; driver)</para>
     <para arch="i386">Genius and Mustek hand scanners</para>
     <para arch="i386">GPB and Transputer drivers</para>
     <para>Keyboards including:
       <itemizedlist>
         <listitem arch="i386,alpha">
 	  <para>AT-style keyboards</para>
 	</listitem>
         <listitem arch="i386,alpha,ia64">
 	  <para>PS/2 keyboards</para>
 	</listitem>
         <listitem arch="i386,alpha">
 	  <para>USB keyboards (specific instances are listed in the
 	  section describing <link linkend="usb">USB devices</link>)</para>
 	</listitem>
       </itemizedlist>
     </para>
     <para arch="i386">Loran-C receiver (Dave Mills experimental hardware, loran driver).</para>
     <para>Mice including:
       <itemizedlist>
         <listitem arch="i386">
 	  <para>Bus mice (&man.mse.4; driver)</para>
 	</listitem>
         <listitem arch="i386,alpha,ia64">
 	  <para>PS/2 mice (&man.psm.4; driver)</para>
 	</listitem>
         <listitem>
 	  <para>Serial mice</para>
 	</listitem>
         <listitem arch="i386,alpha">
 	  <para>USB mice (specific instances are listed in the
 	  section describing <link linkend="usb">USB devices</link>)</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Parallel ports (&man.ppc.4; driver)</para>
 
     <para arch="i386">PC-compatible joysticks (&man.joy.4; driver)</para>
 
     <para arch="i386">PHS Data Communication Card/PCCARD
       <itemizedlist>
         <listitem>
 	  <para>NTT DoCoMo P-in Comp@ct</para>
 	</listitem>
         <listitem>
 	  <para>Panasonic KX-PH405</para>
 	</listitem>
         <listitem>
 	  <para>SII MC-P200</para>
 	</listitem>
       </itemizedlist>
     </para>
 
     <para arch="i386,alpha">Serial ports (&man.sio.4; driver)</para>
 
     <para arch="i386">X-10 power controllers (&man.tw.4; driver)</para>
 
     <para arch="i386">Xilinx XC6200-based reconfigurable hardware cards compatible
     with the HOT1 from <ulink url="http://www.vcc.com/">Virtual
     Computers</ulink> (xrpu driver).</para>
   </sect2>
 </sect1>
Index: stable/4/share/man/man4/bge.4
===================================================================
--- stable/4/share/man/man4/bge.4	(revision 90007)
+++ stable/4/share/man/man4/bge.4	(revision 90008)
@@ -1,206 +1,208 @@
 .\" Copyright (c) 2001 Wind River Systems
 .\" Copyright (c) 1997, 1998, 1999, 2000, 2001
 .\"	Bill Paul <wpaul@windriver.com>. All rights reserved.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
 .\" modification, are permitted provided that the following conditions
 .\" are met:
 .\" 1. Redistributions of source code must retain the above copyright
 .\"    notice, this list of conditions and the following disclaimer.
 .\" 2. Redistributions in binary form must reproduce the above copyright
 .\"    notice, this list of conditions and the following disclaimer in the
 .\"    documentation and/or other materials provided with the distribution.
 .\" 3. All advertising materials mentioning features or use of this software
 .\"    must display the following acknowledgement:
 .\"	This product includes software developed by Bill Paul.
 .\" 4. Neither the name of the author nor the names of any co-contributors
 .\"    may be used to endorse or promote products derived from this software
 .\"   without specific prior written permission.
 .\"
 .\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
 .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 .\" ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
 .\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 .\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 .\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 .\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 .\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 .\" THE POSSIBILITY OF SUCH DAMAGE.
 .\"
 .\" $FreeBSD$
 .\"
 .Dd September 27, 2001
 .Dt BGE 4
 .Os
 .Sh NAME
 .Nm bge
 .Nd "Broadcom BCM570x PCI gigabit ethernet adapter driver"
 .Sh SYNOPSIS
 .Cd "device miibus"
 .Cd "device bge"
 .Sh DESCRIPTION
 The
 .Nm
 driver provides support for various NICs based on the Broadcom BCM570x
 family of gigabit ethernet controller chips, including the
 following:
 .Pp
 .Bl -bullet -compact
 .It
 3Com 3c996-T (10/100/1000baseTX)
 .It
 Dell PowerEdge 2550 integrated BCM5700 NIC (10/100/1000baseTX)
 .It
+Netgear GA302T (10/100/1000baseTX)
+.It
 SysKonnect SK-9D21 (10/100/1000baseTX)
 .It
 SysKonnect SK-9D41 (1000baseSX)
 .El
 .Pp
 All of these NICs are capable of 10, 100 and 1000Mbps speeds over CAT5
 copper cable, except for the SysKonnect SK-9D41 which supports only
 1000Mbps over multimode fiber.
 The BCM570x builds upon the technology of the Alteon Tigon II.
 It has two R4000 CPU cores and is PCI v2.2 and PCI-X v1.0 compliant.
 It supports IP, TCP
 and UDP checksum checksum offload for both receive and transmit,
 multiple RX and TX DMA rings for QoS applications, rules-based
 receive filtering, and VLAN tag stripping/insertion as well as
 a 256-bit multicast hash filter.
 Additional features may be
 provided via value-add firmware updates.
 The BCM570x supports TBI (ten bit interface) and GMII
 transceivers, which means it can be used with either copper of 1000baseX
 fiber applications.
 Note however the device only supports a single
 speed in TBI mode.
 .Pp
 Most cards also use the Broadcom BCM5401 or BCM5411 10/100/1000
 copper gigabit tranceivers,
 which support autonegotiation of 10, 100 and 1000mbps modes in
 full or half duplex.
 .Pp
 The BCM5700 also supports jumbo frames, which can be configured
 via the interface MTU setting.
 Selecting an MTU larger than 1500 bytes with the
 .Xr ifconfig 8
 utility configures the adapter to receive and transmit jumbo frames.
 Using jumbo frames can greatly improve performance for certain tasks,
 such as file transfers and data streaming.
 .Pp
 The
 .Nm
 driver supports the following media types:
 .Bl -tag -width ".Cm 10baseT/UTP"
 .It Cm autoselect
 Enable autoselection of the media type and options.
 The user can manually override
 the autoselected mode by adding media options to
 .Xr rc.conf 5 .
 .It Cm 10baseT/UTP
 Set 10Mbps operation.
 The
 .Xr ifconfig 8
 .Ic mediaopt
 option can also be used to select either
 .Cm full-duplex
 or
 .Cm half-duplex
 modes.
 .It Cm 100baseTX
 Set 100Mbps (fast ethernet) operation.
 The
 .Xr ifconfig 8
 .Ic mediaopt
 option can also be used to select either
 .Cm full-duplex
 or
 .Cm half-duplex
 modes.
 .It Cm 1000baseTX
 Set 1000baseTX operation over twisted pair.
 .Cm full-duplex
 and
 .Cm half-duplex
 modes are supported.
 .It Cm 1000baseSX
 Set 1000Mbps (gigabit ethernet) operation.
 Both
 .Cm full-duplex
 and
 .Cm half-duplex
 modes are supported.
 .El
 .Pp
 The
 .Nm
 driver supports the following media options:
 .Bl -tag -width ".Cm full-duplex"
 .It Cm full-duplex
 Force full duplex operation.
 .It Cm half-duplex
 Force half duplex operation.
 .El
 .Pp
 The
 .Nm
 driver also supports one special link option for 1000baseTX cards:
 .Bl -tag -width ".Cm link0"
 .It Cm link0
 With 1000baseTX cards, establishing a link between two ports requires
 that one port be configured as a master and the other a slave.
 With autonegotiation,
 the master/slave settings will be chosen automatically.
 However when manually selecting the link state, it is necessary to
 force one side of the link to be a master and the other a slave.
 The
 .Nm
 driver configures the ports as slaves by default.
 Setting the
 .Cm link0
 flag with
 .Xr ifconfig 8
 will set a port as a master instead.
 .El
 .Pp
 For more information on configuring this device, see
 .Xr ifconfig 8 .
 .Sh DIAGNOSTICS
 .Bl -diag
 .It "bge%d: couldn't map memory"
 A fatal initialization error has occurred.
 .It "bge%d: couldn't map ports"
 A fatal initialization error has occurred.
 .It "bge%d: couldn't map interrupt"
 A fatal initialization error has occurred.
 .It "bge%d: no memory for softc struct!"
 The driver failed to allocate memory for per-device instance information
 during initialization.
 .It "bge%d: failed to enable memory mapping!"
 The driver failed to initialize PCI shared memory mapping.
 This might
 happen if the card is not in a bus-master slot.
 .It "bge%d: no memory for jumbo buffers!"
 The driver failed to allocate memory for jumbo frames during
 initialization.
 .It "bge%d: watchdog timeout"
 The device has stopped responding to the network, or there is a problem with
 the network connection (cable).
 .El
 .Sh SEE ALSO
 .Xr arp 4 ,
 .Xr netintro 4 ,
 .Xr ng_ether 4 ,
 .Xr vlan 4 ,
 .Xr ifconfig 8
 .Sh HISTORY
 The
 .Nm
 device driver first appeared in
 .Fx 4.5 .
 .Sh AUTHORS
 The
 .Nm
 driver was written by
 .An Bill Paul Aq wpaul@windriver.com .
Index: stable/4/sys/dev/bge/if_bge.c
===================================================================
--- stable/4/sys/dev/bge/if_bge.c	(revision 90007)
+++ stable/4/sys/dev/bge/if_bge.c	(revision 90008)
@@ -1,2765 +1,2767 @@
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  *
  * $FreeBSD$
  */
 
 /*
  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  * 
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Engineer, Wind River Systems
  */
 
 /*
  * The Broadcom BCM5700 is based on technology originally developed by
  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  * frames, highly configurable RX filtering, and 16 RX and TX queues
  * (which, along with RX filter rules, can be used for QOS applications).
  * Other features, such as TCP segmentation, may be available as part
  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  * firmware images can be stored in hardware and need not be compiled
  * into the driver.
  *
  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  * 
  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700
  * does not support external SSRAM.
  *
  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  * brand name, which is functionally similar but lacks PCI-X support.
  *
  * Without external SSRAM, you can only have at most 4 TX rings,
  * and the use of the mini RX ring is disabled. This seems to imply
  * that these features are simply not available on the BCM5701. As a
  * result, this driver does not implement any support for the mini RX
  * ring.
  */
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/queue.h>
 
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/ethernet.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 
 #include <net/bpf.h>
 
 #include <net/if_types.h>
 #include <net/if_vlan_var.h>
 
 #include <netinet/in_systm.h>
 #include <netinet/in.h>
 #include <netinet/ip.h>
 
 #include <vm/vm.h>              /* for vtophys */
 #include <vm/pmap.h>            /* for vtophys */
 #include <machine/clock.h>      /* for DELAY */
 #include <machine/bus_memio.h>
 #include <machine/bus.h>
 #include <machine/resource.h>
 #include <sys/bus.h>
 #include <sys/rman.h>
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/brgphyreg.h>
 
 #include <pci/pcireg.h>
 #include <pci/pcivar.h>
 
 #include <dev/bge/if_bgereg.h>
 
 #define BGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
 
 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 #include "miibus_if.h"
 
 #if !defined(lint)
 static const char rcsid[] =
   "$FreeBSD$";
 #endif
 
 /*
  * Various supported device vendors/types and their names. Note: the
  * spec seems to indicate that the hardware still has Alteon's vendor
  * ID burned into it, though it will always be overriden by the vendor
  * ID in the EEPROM. Just to be safe, we cover all possibilities.
  */
 
 static struct bge_type bge_devs[] = {
 	{ ALT_VENDORID,	ALT_DEVICEID_BCM5700,
 		"Broadcom BCM5700 Gigabit Ethernet" },
 	{ ALT_VENDORID,	ALT_DEVICEID_BCM5701,
 		"Broadcom BCM5701 Gigabit Ethernet" },
 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5700,
 		"Broadcom BCM5700 Gigabit Ethernet" },
 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5701,
 		"Broadcom BCM5701 Gigabit Ethernet" },
 	{ SK_VENDORID, SK_DEVICEID_ALTIMA,
 		"SysKonnect Gigabit Ethernet" },
+	{ ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000,
+		"Altima AC1000 Gigabit Ethernet" },
 	{ 0, 0, NULL }
 };
 
 static int bge_probe		__P((device_t));
 static int bge_attach		__P((device_t));
 static int bge_detach		__P((device_t));
 static void bge_release_resources
 				__P((struct bge_softc *));
 static void bge_txeof		__P((struct bge_softc *));
 static void bge_rxeof		__P((struct bge_softc *));
 
 static void bge_tick		__P((void *));
 static void bge_stats_update	__P((struct bge_softc *));
 static int bge_encap		__P((struct bge_softc *, struct mbuf *,
 					u_int32_t *));
 
 static void bge_intr		__P((void *));
 static void bge_start		__P((struct ifnet *));
 static int bge_ioctl		__P((struct ifnet *, u_long, caddr_t));
 static void bge_init		__P((void *));
 static void bge_stop		__P((struct bge_softc *));
 static void bge_watchdog		__P((struct ifnet *));
 static void bge_shutdown		__P((device_t));
 static int bge_ifmedia_upd	__P((struct ifnet *));
 static void bge_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
 
 static u_int8_t	bge_eeprom_getbyte	__P((struct bge_softc *,
 						int, u_int8_t *));
 static int bge_read_eeprom	__P((struct bge_softc *, caddr_t, int, int));
 
 static u_int32_t bge_crc	__P((caddr_t));
 static void bge_setmulti	__P((struct bge_softc *));
 
 static void bge_handle_events	__P((struct bge_softc *));
 static int bge_alloc_jumbo_mem	__P((struct bge_softc *));
 static void bge_free_jumbo_mem	__P((struct bge_softc *));
 static void *bge_jalloc		__P((struct bge_softc *));
 static void bge_jfree		__P((caddr_t, u_int));
 static void bge_jref		__P((caddr_t, u_int));
 static int bge_newbuf_std	__P((struct bge_softc *, int, struct mbuf *));
 static int bge_newbuf_jumbo	__P((struct bge_softc *, int, struct mbuf *));
 static int bge_init_rx_ring_std	__P((struct bge_softc *));
 static void bge_free_rx_ring_std	__P((struct bge_softc *));
 static int bge_init_rx_ring_jumbo	__P((struct bge_softc *));
 static void bge_free_rx_ring_jumbo	__P((struct bge_softc *));
 static void bge_free_tx_ring	__P((struct bge_softc *));
 static int bge_init_tx_ring	__P((struct bge_softc *));
 
 static int bge_chipinit		__P((struct bge_softc *));
 static int bge_blockinit	__P((struct bge_softc *));
 
 #ifdef notdef
 static u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int));
 static void bge_vpd_read_res	__P((struct bge_softc *,
                                         struct vpd_res *, int));
 static void bge_vpd_read	__P((struct bge_softc *));
 #endif
 
 static u_int32_t bge_readmem_ind
 				__P((struct bge_softc *, int));
 static void bge_writemem_ind	__P((struct bge_softc *, int, int));
 #ifdef notdef
 static u_int32_t bge_readreg_ind
 				__P((struct bge_softc *, int));
 #endif
 static void bge_writereg_ind	__P((struct bge_softc *, int, int));
 
 static int bge_miibus_readreg	__P((device_t, int, int));
 static int bge_miibus_writereg	__P((device_t, int, int, int));
 static void bge_miibus_statchg	__P((device_t));
 
 static void bge_reset		__P((struct bge_softc *));
 static void bge_phy_hack	__P((struct bge_softc *));
 
 static device_method_t bge_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		bge_probe),
 	DEVMETHOD(device_attach,	bge_attach),
 	DEVMETHOD(device_detach,	bge_detach),
 	DEVMETHOD(device_shutdown,	bge_shutdown),
 
 	/* bus interface */
 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 
 	/* MII interface */
 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
 
 	{ 0, 0 }
 };
 
 static driver_t bge_driver = {
 	"bge",
 	bge_methods,
 	sizeof(struct bge_softc)
 };
 
 static devclass_t bge_devclass;
 
 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 
 static u_int32_t
 bge_readmem_ind(sc, off)
 	struct bge_softc *sc;
 	int off;
 {
 	device_t dev;
 
 	dev = sc->bge_dev;
 
 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 	return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 }
 
 static void
 bge_writemem_ind(sc, off, val)
 	struct bge_softc *sc;
 	int off, val;
 {
 	device_t dev;
 
 	dev = sc->bge_dev;
 
 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 	pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 
 	return;
 }
 
 #ifdef notdef
 static u_int32_t
 bge_readreg_ind(sc, off)
 	struct bge_softc *sc;
 	int off;
 {
 	device_t dev;
 
 	dev = sc->bge_dev;
 
 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 	return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 }
 #endif
 
 static void
 bge_writereg_ind(sc, off, val)
 	struct bge_softc *sc;
 	int off, val;
 {
 	device_t dev;
 
 	dev = sc->bge_dev;
 
 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 	pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 
 	return;
 }
 
 #ifdef notdef
 static u_int8_t
 bge_vpd_readbyte(sc, addr)
 	struct bge_softc *sc;
 	int addr;
 {
 	int i;
 	device_t dev;
 	u_int32_t val;
 
 	dev = sc->bge_dev;
 	pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 		DELAY(10);
 		if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 			break;
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: VPD read timed out\n", sc->bge_unit);
 		return(0);
 	}
 
 	val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 
 	return((val >> ((addr % 4) * 8)) & 0xFF);
 }
 
 static void
 bge_vpd_read_res(sc, res, addr)
 	struct bge_softc *sc;
 	struct vpd_res *res;
 	int addr;
 {
 	int i;
 	u_int8_t *ptr;
 
 	ptr = (u_int8_t *)res;
 	for (i = 0; i < sizeof(struct vpd_res); i++)
 		ptr[i] = bge_vpd_readbyte(sc, i + addr);
 
 	return;
 }
 
 static void
 bge_vpd_read(sc)
 	struct bge_softc *sc;
 {
 	int pos = 0, i;
 	struct vpd_res res;
 
 	if (sc->bge_vpd_prodname != NULL)
 		free(sc->bge_vpd_prodname, M_DEVBUF);
 	if (sc->bge_vpd_readonly != NULL)
 		free(sc->bge_vpd_readonly, M_DEVBUF);
 	sc->bge_vpd_prodname = NULL;
 	sc->bge_vpd_readonly = NULL;
 
 	bge_vpd_read_res(sc, &res, pos);
 
 	if (res.vr_id != VPD_RES_ID) {
 		printf("bge%d: bad VPD resource id: expected %x got %x\n",
 			sc->bge_unit, VPD_RES_ID, res.vr_id);
                 return;
         }
 
 	pos += sizeof(res);
 	sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
 	for (i = 0; i < res.vr_len; i++)
 		sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 	sc->bge_vpd_prodname[i] = '\0';
 	pos += i;
 
 	bge_vpd_read_res(sc, &res, pos);
 
 	if (res.vr_id != VPD_RES_READ) {
 		printf("bge%d: bad VPD resource id: expected %x got %x\n",
 		    sc->bge_unit, VPD_RES_READ, res.vr_id);
 		return;
 	}
 
 	pos += sizeof(res);
 	sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
 	for (i = 0; i < res.vr_len + 1; i++)
 		sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 
 	return;
 }
 #endif
 
 /*
  * Read a byte of data stored in the EEPROM at address 'addr.' The
  * BCM570x supports both the traditional bitbang interface and an
  * auto access interface for reading the EEPROM. We use the auto
  * access method.
  */
 static u_int8_t
 bge_eeprom_getbyte(sc, addr, dest)
 	struct bge_softc *sc;
 	int addr;
 	u_int8_t *dest;
 {
 	int i;
 	u_int32_t byte = 0;
 
 	/*
 	 * Enable use of auto EEPROM access so we can avoid
 	 * having to use the bitbang method.
 	 */
 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 
 	/* Reset the EEPROM, load the clock period. */
 	CSR_WRITE_4(sc, BGE_EE_ADDR,
 	    BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 	DELAY(20);
 
 	/* Issue the read EEPROM command. */
 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 
 	/* Wait for completion */
 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 		DELAY(10);
 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 			break;
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: eeprom read timed out\n", sc->bge_unit);
 		return(0);
 	}
 
 	/* Get result. */
 	byte = CSR_READ_4(sc, BGE_EE_DATA);
 
         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 
 	return(0);
 }
 
 /*
  * Read a sequence of bytes from the EEPROM.
  */
 static int
 bge_read_eeprom(sc, dest, off, cnt)
 	struct bge_softc *sc;
 	caddr_t dest;
 	int off;
 	int cnt;
 {
 	int err = 0, i;
 	u_int8_t byte = 0;
 
 	for (i = 0; i < cnt; i++) {
 		err = bge_eeprom_getbyte(sc, off + i, &byte);
 		if (err)
 			break;
 		*(dest + i) = byte;
 	}
 
 	return(err ? 1 : 0);
 }
 
 static int
 bge_miibus_readreg(dev, phy, reg)
 	device_t dev;
 	int phy, reg;
 {
 	struct bge_softc *sc;
 	struct ifnet *ifp;
 	u_int32_t val;
 	int i;
 
 	sc = device_get_softc(dev);
 	ifp = &sc->arpcom.ac_if;
 
 	if (ifp->if_flags & IFF_RUNNING)
 		BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 
 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 	    BGE_MIPHY(phy)|BGE_MIREG(reg));
 
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		val = CSR_READ_4(sc, BGE_MI_COMM);
 		if (!(val & BGE_MICOMM_BUSY))
 			break;
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: PHY read timed out\n", sc->bge_unit);
 		return(0);
 	}
 
 	val = CSR_READ_4(sc, BGE_MI_COMM);
 
 	if (ifp->if_flags & IFF_RUNNING)
 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 
 	if (val & BGE_MICOMM_READFAIL)
 		return(0);
 
 	return(val & 0xFFFF);
 }
 
 static int
 bge_miibus_writereg(dev, phy, reg, val)
 	device_t dev;
 	int phy, reg, val;
 {
 	struct bge_softc *sc;
 	int i;
 
 	sc = device_get_softc(dev);
 
 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 	    BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 			break;
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: PHY read timed out\n", sc->bge_unit);
 		return(0);
 	}
 
 	return(0);
 }
 
 static void
 bge_miibus_statchg(dev)
 	device_t dev;
 {
 	struct bge_softc *sc;
 	struct mii_data *mii;
 
 	sc = device_get_softc(dev);
 	mii = device_get_softc(sc->bge_miibus);
 
 	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 	} else {
 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 	}
 
 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 	} else {
 		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 	}
 
 	bge_phy_hack(sc);
 
 	return;
 }
 
 /*
  * Handle events that have triggered interrupts.
  */
 static void
 bge_handle_events(sc)
 	struct bge_softc		*sc;
 {
 
 	return;
 }
 
 /*
  * Memory management for jumbo frames.
  */
 
 static int
 bge_alloc_jumbo_mem(sc)
 	struct bge_softc		*sc;
 {
 	caddr_t			ptr;
 	register int		i;
 	struct bge_jpool_entry   *entry;
 
 	/* Grab a big chunk o' storage. */
 	sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 		M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 
 	if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 		printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
 		return(ENOBUFS);
 	}
 
 	SLIST_INIT(&sc->bge_jfree_listhead);
 	SLIST_INIT(&sc->bge_jinuse_listhead);
 
 	/*
 	 * Now divide it up into 9K pieces and save the addresses
 	 * in an array. Note that we play an evil trick here by using
 	 * the first few bytes in the buffer to hold the the address
 	 * of the softc structure for this interface. This is because
 	 * bge_jfree() needs it, but it is called by the mbuf management
 	 * code which will not pass it to us explicitly.
 	 */
 	ptr = sc->bge_cdata.bge_jumbo_buf;
 	for (i = 0; i < BGE_JSLOTS; i++) {
 		u_int64_t		**aptr;
 		aptr = (u_int64_t **)ptr;
 		aptr[0] = (u_int64_t *)sc;
 		ptr += sizeof(u_int64_t);
 		sc->bge_cdata.bge_jslots[i].bge_buf = ptr;
 		sc->bge_cdata.bge_jslots[i].bge_inuse = 0;
 		ptr += (BGE_JLEN - sizeof(u_int64_t));
 		entry = malloc(sizeof(struct bge_jpool_entry), 
 			       M_DEVBUF, M_NOWAIT);
 		if (entry == NULL) {
 			contigfree(sc->bge_cdata.bge_jumbo_buf,
 			    BGE_JMEM, M_DEVBUF);
 			sc->bge_cdata.bge_jumbo_buf = NULL;
 			printf("bge%d: no memory for jumbo "
 			    "buffer queue!\n", sc->bge_unit);
 			return(ENOBUFS);
 		}
 		entry->slot = i;
 		SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 		    entry, jpool_entries);
 	}
 
 	return(0);
 }
 
 static void
 bge_free_jumbo_mem(sc)
         struct bge_softc *sc;
 {
         int i;
         struct bge_jpool_entry *entry;
  
 	for (i = 0; i < BGE_JSLOTS; i++) {
 		entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 		SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
 		free(entry, M_DEVBUF);
 	}
 
 	contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 
         return;
 }
 
 /*
  * Allocate a jumbo buffer.
  */
 static void *
 bge_jalloc(sc)
 	struct bge_softc		*sc;
 {
 	struct bge_jpool_entry   *entry;
 	
 	entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 	
 	if (entry == NULL) {
 		printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
 		return(NULL);
 	}
 
 	SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
 	SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
 	sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1;
 	return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf);
 }
 
 /*
  * Adjust usage count on a jumbo buffer.
  */
 static void
 bge_jref(buf, size)
 	caddr_t			buf;
 	u_int			size;
 {
 	struct bge_softc		*sc;
 	u_int64_t		**aptr;
 	register int		i;
 
 	/* Extract the softc struct pointer. */
 	aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
 	sc = (struct bge_softc *)(aptr[0]);
 
 	if (sc == NULL)
 		panic("bge_jref: can't find softc pointer!");
 
 	if (size != BGE_JUMBO_FRAMELEN)
 		panic("bge_jref: adjusting refcount of buf of wrong size!");
 
 	/* calculate the slot this buffer belongs to */
 
 	i = ((vm_offset_t)aptr 
 	     - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
 
 	if ((i < 0) || (i >= BGE_JSLOTS))
 		panic("bge_jref: asked to reference buffer "
 		    "that we don't manage!");
 	else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
 		panic("bge_jref: buffer already free!");
 	else
 		sc->bge_cdata.bge_jslots[i].bge_inuse++;
 
 	return;
 }
 
 /*
  * Release a jumbo buffer.
  */
 static void
 bge_jfree(buf, size)
 	caddr_t			buf;
 	u_int			size;
 {
 	struct bge_softc		*sc;
 	u_int64_t		**aptr;
 	int		        i;
 	struct bge_jpool_entry   *entry;
 
 	/* Extract the softc struct pointer. */
 	aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
 	sc = (struct bge_softc *)(aptr[0]);
 
 	if (sc == NULL)
 		panic("bge_jfree: can't find softc pointer!");
 
 	if (size != BGE_JUMBO_FRAMELEN)
 		panic("bge_jfree: freeing buffer of wrong size!");
 
 	/* calculate the slot this buffer belongs to */
 
 	i = ((vm_offset_t)aptr 
 	     - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
 
 	if ((i < 0) || (i >= BGE_JSLOTS))
 		panic("bge_jfree: asked to free buffer that we don't manage!");
 	else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
 		panic("bge_jfree: buffer already free!");
 	else {
 		sc->bge_cdata.bge_jslots[i].bge_inuse--;
 		if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) {
 			entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
 			if (entry == NULL)
 				panic("bge_jfree: buffer not in use!");
 			entry->slot = i;
 			SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, 
 					  jpool_entries);
 			SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
 					  entry, jpool_entries);
 		}
 	}
 
 	return;
 }
 
 
 /*
  * Intialize a standard receive ring descriptor.
  */
 static int
 bge_newbuf_std(sc, i, m)
 	struct bge_softc	*sc;
 	int			i;
 	struct mbuf		*m;
 {
 	struct mbuf		*m_new = NULL;
 	struct bge_rx_bd	*r;
 
 	if (m == NULL) {
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
 			printf("bge%d: mbuf allocation failed "
 			    "-- packet dropped!\n", sc->bge_unit);
 			return(ENOBUFS);
 		}
 
 		MCLGET(m_new, M_DONTWAIT);
 		if (!(m_new->m_flags & M_EXT)) {
 			printf("bge%d: cluster allocation failed "
 			    "-- packet dropped!\n", sc->bge_unit);
 			m_freem(m_new);
 			return(ENOBUFS);
 		}
 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 	} else {
 		m_new = m;
 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 		m_new->m_data = m_new->m_ext.ext_buf;
 	}
 
 	m_adj(m_new, ETHER_ALIGN);
 	sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 	r = &sc->bge_rdata->bge_rx_std_ring[i];
 	BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
 	r->bge_flags = BGE_RXBDFLAG_END;
 	r->bge_len = m_new->m_len;
 	r->bge_idx = i;
 
 	return(0);
 }
 
 /*
  * Initialize a jumbo receive ring descriptor. This allocates
  * a jumbo buffer from the pool managed internally by the driver.
  */
 static int
 bge_newbuf_jumbo(sc, i, m)
 	struct bge_softc *sc;
 	int i;
 	struct mbuf *m;
 {
 	struct mbuf *m_new = NULL;
 	struct bge_rx_bd *r;
 
 	if (m == NULL) {
 		caddr_t			*buf = NULL;
 
 		/* Allocate the mbuf. */
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
 			printf("bge%d: mbuf allocation failed "
 			    "-- packet dropped!\n", sc->bge_unit);
 			return(ENOBUFS);
 		}
 
 		/* Allocate the jumbo buffer */
 		buf = bge_jalloc(sc);
 		if (buf == NULL) {
 			m_freem(m_new);
 			printf("bge%d: jumbo allocation failed "
 			    "-- packet dropped!\n", sc->bge_unit);
 			return(ENOBUFS);
 		}
 
 		/* Attach the buffer to the mbuf. */
 		m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
 		m_new->m_flags |= M_EXT;
 		m_new->m_len = m_new->m_pkthdr.len =
 		    m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 		m_new->m_ext.ext_free = bge_jfree;
 		m_new->m_ext.ext_ref = bge_jref;
 	} else {
 		m_new = m;
 		m_new->m_data = m_new->m_ext.ext_buf;
 		m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 	}
 
 	m_adj(m_new, ETHER_ALIGN);
 	/* Set up the descriptor. */
 	r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 	BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
 	r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 	r->bge_len = m_new->m_len;
 	r->bge_idx = i;
 
 	return(0);
 }
 
 /*
  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
  * that's 1MB or memory, which is a lot. For now, we fill only the first
  * 256 ring entries and hope that our CPU is fast enough to keep up with
  * the NIC.
  */
 static int
 bge_init_rx_ring_std(sc)
 	struct bge_softc *sc;
 {
 	int i;
 
 	for (i = 0; i < BGE_SSLOTS; i++) {
 		if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 			return(ENOBUFS);
 	};
 
 	sc->bge_std = i - 1;
 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 
 	return(0);
 }
 
 static void
 bge_free_rx_ring_std(sc)
 	struct bge_softc *sc;
 {
 	int i;
 
 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 		}
 		bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
 		    sizeof(struct bge_rx_bd));
 	}
 
 	return;
 }
 
 static int
 bge_init_rx_ring_jumbo(sc)
 	struct bge_softc *sc;
 {
 	int i;
 	struct bge_rcb *rcb;
 	struct bge_rcb_opaque *rcbo;
 
 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 		if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 			return(ENOBUFS);
 	};
 
 	sc->bge_jumbo = i - 1;
 
 	rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 	rcbo = (struct bge_rcb_opaque *)rcb;
 	rcb->bge_flags = 0;
 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
 
 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 
 	return(0);
 }
 
 static void
 bge_free_rx_ring_jumbo(sc)
 	struct bge_softc *sc;
 {
 	int i;
 
 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 		}
 		bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
 		    sizeof(struct bge_rx_bd));
 	}
 
 	return;
 }
 
 static void
 bge_free_tx_ring(sc)
 	struct bge_softc *sc;
 {
 	int i;
 
 	if (sc->bge_rdata->bge_tx_ring == NULL)
 		return;
 
 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
 			sc->bge_cdata.bge_tx_chain[i] = NULL;
 		}
 		bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
 		    sizeof(struct bge_tx_bd));
 	}
 
 	return;
 }
 
 static int
 bge_init_tx_ring(sc)
 	struct bge_softc *sc;
 {
 	sc->bge_txcnt = 0;
 	sc->bge_tx_saved_considx = 0;
 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 	CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 
 	return(0);
 }
 
 #define BGE_POLY	0xEDB88320
 
 static u_int32_t
 bge_crc(addr)
 	caddr_t addr;
 {
 	u_int32_t idx, bit, data, crc;
 
 	/* Compute CRC for the address value. */
 	crc = 0xFFFFFFFF; /* initial value */
 
 	for (idx = 0; idx < 6; idx++) {
 		for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
 			crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
 	}
 
 	return(crc & 0x7F);
 }
 
 static void
 bge_setmulti(sc)
 	struct bge_softc *sc;
 {
 	struct ifnet *ifp;
 	struct ifmultiaddr *ifma;
 	u_int32_t hashes[4] = { 0, 0, 0, 0 };
 	int h, i;
 
 	ifp = &sc->arpcom.ac_if;
 
 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 		for (i = 0; i < 4; i++)
 			CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 		return;
 	}
 
 	/* First, zot all the existing filters. */
 	for (i = 0; i < 4; i++)
 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 
 	/* Now program new ones. */
 	for (ifma = ifp->if_multiaddrs.lh_first;
 	    ifma != NULL; ifma = ifma->ifma_link.le_next) {
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 		hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 	}
 
 	for (i = 0; i < 4; i++)
 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 
 	return;
 }
 
 /*
  * Do endian, PCI and DMA initialization. Also check the on-board ROM
  * self-test results.
  */
 static int
 bge_chipinit(sc)
 	struct bge_softc *sc;
 {
 	u_int32_t		cachesize;
 	int			i;
 
 	/* Set endianness before we access any non-PCI registers. */
 #if BYTE_ORDER == BIG_ENDIAN
 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 	    BGE_BIGENDIAN_INIT, 4);
 #else
 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 	    BGE_LITTLEENDIAN_INIT, 4);
 #endif
 
 	/*
 	 * Check the 'ROM failed' bit on the RX CPU to see if
 	 * self-tests passed.
 	 */
 	if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 		printf("bge%d: RX CPU self-diagnostics failed!\n",
 		    sc->bge_unit);
 		return(ENODEV);
 	}
 
 	/* Clear the MAC control register */
 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 
 	/*
 	 * Clear the MAC statistics block in the NIC's
 	 * internal memory.
 	 */
 	for (i = BGE_STATS_BLOCK;
 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
 		BGE_MEMWIN_WRITE(sc, i, 0);
 
 	for (i = BGE_STATUS_BLOCK;
 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
 		BGE_MEMWIN_WRITE(sc, i, 0);
 
 	/* Set up the PCI DMA control register. */
 	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 	    BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4);
 
 	/*
 	 * Set up general mode register.
 	 */
 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
 	    BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
 	    BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
 	    BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
 	    BGE_MODECTL_RX_NO_PHDR_CSUM);
 
 	/* Get cache line size. */
 	cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1);
 
 	/*
 	 * Avoid violating PCI spec on certain chip revs.
 	 */
 	if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) {
 		switch(cachesize) {
 		case 1:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_16BYTES, 4);
 			break;
 		case 2:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_32BYTES, 4);
 			break;
 		case 4:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_64BYTES, 4);
 			break;
 		case 8:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_128BYTES, 4);
 			break;
 		case 16:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_256BYTES, 4);
 			break;
 		case 32:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_512BYTES, 4);
 			break;
 		case 64:
 			PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
 			    BGE_PCI_WRITE_BNDRY_1024BYTES, 4);
 			break;
 		default:
 		/* Disable PCI memory write and invalidate. */
 			if (bootverbose)
 				printf("bge%d: cache line size %d not "
 				    "supported; disabling PCI MWI\n",
 				    sc->bge_unit, cachesize);
 			PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
 			    PCIM_CMD_MWIEN, 4);
 			break;
 		}
 	}
 
 #ifdef __brokenalpha__
 	/*
 	 * Must insure that we do not cross an 8K (bytes) boundary
 	 * for DMA reads.  Our highest limit is 1K bytes.  This is a 
 	 * restriction on some ALPHA platforms with early revision 
 	 * 21174 PCI chipsets, such as the AlphaPC 164lx 
 	 */
 	PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
 #endif
 
 	/* Set the timer prescaler (always 66Mhz) */
 	CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
 
 	return(0);
 }
 
 static int
 bge_blockinit(sc)
 	struct bge_softc *sc;
 {
 	struct bge_rcb *rcb;
 	struct bge_rcb_opaque *rcbo;
 	int i;
 
 	/*
 	 * Initialize the memory window pointer register so that
 	 * we can access the first 32K of internal NIC RAM. This will
 	 * allow us to set up the TX send ring RCBs and the RX return
 	 * ring RCBs, plus other things which live in NIC memory.
 	 */
 	CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
 
 	/* Configure mbuf memory pool */
 	if (sc->bge_extram) {
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM);
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
 	} else {
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
 	}
 
 	/* Configure DMA resource pool */
 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS);
 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
 
 	/* Configure mbuf pool watermarks */
 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
 	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
 
 	/* Configure DMA resource watermarks */
 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
 
 	/* Enable buffer manager */
 	CSR_WRITE_4(sc, BGE_BMAN_MODE,
 	    BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
 
 	/* Poll for buffer manager start indication */
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
 			break;
 		DELAY(10);
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: buffer manager failed to start\n",
 		    sc->bge_unit);
 		return(ENXIO);
 	}
 
 	/* Enable flow-through queues */
 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 
 	/* Wait until queue initialization is complete */
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
 			break;
 		DELAY(10);
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: flow-through queue init failed\n",
 		    sc->bge_unit);
 		return(ENXIO);
 	}
 
 	/* Initialize the standard RX ring control block */
 	rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
 	BGE_HOSTADDR(rcb->bge_hostaddr) =
 	    vtophys(&sc->bge_rdata->bge_rx_std_ring);
 	rcb->bge_max_len = BGE_MAX_FRAMELEN;
 	if (sc->bge_extram)
 		rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
 	else
 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
 	rcb->bge_flags = 0;
 	rcbo = (struct bge_rcb_opaque *)rcb;
 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0);
 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1);
 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3);
 
 	/*
 	 * Initialize the jumbo RX ring control block
 	 * We set the 'ring disabled' bit in the flags
 	 * field until we're actually ready to start
 	 * using this ring (i.e. once we set the MTU
 	 * high enough to require it).
 	 */
 	rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 	BGE_HOSTADDR(rcb->bge_hostaddr) =
 	    vtophys(&sc->bge_rdata->bge_rx_jumbo_ring);
 	rcb->bge_max_len = BGE_MAX_FRAMELEN;
 	if (sc->bge_extram)
 		rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
 	else
 		rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
 	rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
 
 	rcbo = (struct bge_rcb_opaque *)rcb;
 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0);
 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1);
 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3);
 
 	/* Set up dummy disabled mini ring RCB */
 	rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
 	rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
 	rcbo = (struct bge_rcb_opaque *)rcb;
 	CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
 
 	/*
 	 * Set the BD ring replentish thresholds. The recommended
 	 * values are 1/8th the number of descriptors allocated to
 	 * each ring.
 	 */
 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
 	CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
 
 	/*
 	 * Disable all unused send rings by setting the 'ring disabled'
 	 * bit in the flags field of all the TX send ring control blocks.
 	 * These are located in NIC memory.
 	 */
 	rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
 	    BGE_SEND_RING_RCB);
 	for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
 		rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
 		rcb->bge_max_len = 0;
 		rcb->bge_nicaddr = 0;
 		rcb++;
 	}
 
 	/* Configure TX RCB 0 (we use only the first ring) */
 	rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
 	    BGE_SEND_RING_RCB);
 	rcb->bge_hostaddr.bge_addr_hi = 0;
 	BGE_HOSTADDR(rcb->bge_hostaddr) =
 	    vtophys(&sc->bge_rdata->bge_tx_ring);
 	rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
 	rcb->bge_max_len = BGE_TX_RING_CNT;
 	rcb->bge_flags = 0;
 
 	/* Disable all unused RX return rings */
 	rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
 	    BGE_RX_RETURN_RING_RCB);
 	for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
 		rcb->bge_hostaddr.bge_addr_hi = 0;
 		rcb->bge_hostaddr.bge_addr_lo = 0;
 		rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
 		rcb->bge_max_len = BGE_RETURN_RING_CNT;
 		rcb->bge_nicaddr = 0;
 		CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
 		    (i * (sizeof(u_int64_t))), 0);
 		rcb++;
 	}
 
 	/* Initialize RX ring indexes */
 	CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
 	CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
 	CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
 
 	/*
 	 * Set up RX return ring 0
 	 * Note that the NIC address for RX return rings is 0x00000000.
 	 * The return rings live entirely within the host, so the
 	 * nicaddr field in the RCB isn't used.
 	 */
 	rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
 	    BGE_RX_RETURN_RING_RCB);
 	rcb->bge_hostaddr.bge_addr_hi = 0;
 	BGE_HOSTADDR(rcb->bge_hostaddr) =
 	    vtophys(&sc->bge_rdata->bge_rx_return_ring);
 	rcb->bge_nicaddr = 0x00000000;
 	rcb->bge_max_len = BGE_RETURN_RING_CNT;
 	rcb->bge_flags = 0;
 
 	/* Set random backoff seed for TX */
 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
 	    sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 	    sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
 	    sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
 	    BGE_TX_BACKOFF_SEED_MASK);
 
 	/* Set inter-packet gap */
 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
 
 	/*
 	 * Specify which ring to use for packets that don't match
 	 * any RX rules.
 	 */
 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
 
 	/*
 	 * Configure number of RX lists. One interrupt distribution
 	 * list, sixteen active lists, one bad frames class.
 	 */
 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
 
 	/* Inialize RX list placement stats mask. */
 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
 
 	/* Disable host coalescing until we get it set up */
 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
 
 	/* Poll to make sure it's shut down. */
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
 			break;
 		DELAY(10);
 	}
 
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: host coalescing engine failed to idle\n",
 		    sc->bge_unit);
 		return(ENXIO);
 	}
 
 	/* Set up host coalescing defaults */
 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
 	CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
 
 	/* Set up address of statistics block */
 	CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
 	CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
 	CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
 	    vtophys(&sc->bge_rdata->bge_info.bge_stats));
 
 	/* Set up address of status block */
 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
 	    vtophys(&sc->bge_rdata->bge_status_block));
 	sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
 	sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
 
 	/* Turn on host coalescing state machine */
 	CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
 
 	/* Turn on RX BD completion state machine and enable attentions */
 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
 	    BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
 
 	/* Turn on RX list placement state machine */
 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 
 	/* Turn on RX list selector state machine. */
 	CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 
 	/* Turn on DMA, clear stats */
 	CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
 	    BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
 	    BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
 	    BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
 	    (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
 
 	/* Set misc. local control, enable interrupts on attentions */
 	CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
 
 #ifdef notdef
 	/* Assert GPIO pins for PHY reset */
 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
 	    BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
 	    BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
 #endif
 
 	/* Turn on DMA completion state machine */
 	CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 
 	/* Turn on write DMA state machine */
 	CSR_WRITE_4(sc, BGE_WDMA_MODE,
 	    BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
 	
 	/* Turn on read DMA state machine */
 	CSR_WRITE_4(sc, BGE_RDMA_MODE,
 	    BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
 
 	/* Turn on RX data completion state machine */
 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 
 	/* Turn on RX BD initiator state machine */
 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 
 	/* Turn on RX data and RX BD initiator state machine */
 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
 
 	/* Turn on Mbuf cluster free state machine */
 	CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 
 	/* Turn on send BD completion state machine */
 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 
 	/* Turn on send data completion state machine */
 	CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
 
 	/* Turn on send data initiator state machine */
 	CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 
 	/* Turn on send BD initiator state machine */
 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 
 	/* Turn on send BD selector state machine */
 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
 
 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
 	    BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
 
 	/* init LED register */
 	CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000);
 
 	/* ack/clear link change events */
 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
 	    BGE_MACSTAT_CFG_CHANGED);
 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
 
 	/* Enable PHY auto polling (for MII/GMII only) */
 	if (sc->bge_tbi) {
 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
 	} else
 		BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
 
 	/* Enable link state change attentions. */
 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
 
 	return(0);
 }
 
 /*
  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
  * against our list and return its name if we find a match. Note
  * that since the Broadcom controller contains VPD support, we
  * can get the device name string from the controller itself instead
  * of the compiled-in string. This is a little slow, but it guarantees
  * we'll always announce the right product name.
  */
 static int
 bge_probe(dev)
 	device_t dev;
 {
 	struct bge_type *t;
 	struct bge_softc *sc;
 
 	t = bge_devs;
 
 	sc = device_get_softc(dev);
 	bzero(sc, sizeof(struct bge_softc));
 	sc->bge_unit = device_get_unit(dev);
 	sc->bge_dev = dev;
 
 	while(t->bge_name != NULL) {
 		if ((pci_get_vendor(dev) == t->bge_vid) &&
 		    (pci_get_device(dev) == t->bge_did)) {
 #ifdef notdef
 			bge_vpd_read(sc);
 			device_set_desc(dev, sc->bge_vpd_prodname);
 #endif
 			device_set_desc(dev, t->bge_name);
 			return(0);
 		}
 		t++;
 	}
 
 	return(ENXIO);
 }
 
 static int
 bge_attach(dev)
 	device_t dev;
 {
 	int s;
 	u_int32_t command;
 	struct ifnet *ifp;
 	struct bge_softc *sc;
 	int unit, error = 0, rid;
 
 	s = splimp();
 
 	sc = device_get_softc(dev);
 	unit = device_get_unit(dev);
 	sc->bge_dev = dev;
 	sc->bge_unit = unit;
 
 	/*
 	 * Map control/status registers.
 	 */
 	command = pci_read_config(dev, PCIR_COMMAND, 4);
 	command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
 	pci_write_config(dev, PCIR_COMMAND, command, 4);
 	command = pci_read_config(dev, PCIR_COMMAND, 4);
 
 	if (!(command & PCIM_CMD_MEMEN)) {
 		printf("bge%d: failed to enable memory mapping!\n", unit);
 		error = ENXIO;
 		goto fail;
 	}
 
 	rid = BGE_PCI_BAR0;
 	sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 	    0, ~0, 1, RF_ACTIVE);
 
 	if (sc->bge_res == NULL) {
 		printf ("bge%d: couldn't map memory\n", unit);
 		error = ENXIO;
 		goto fail;
 	}
 
 	sc->bge_btag = rman_get_bustag(sc->bge_res);
 	sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
 	sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
 
 	/*
 	 * XXX FIXME: rman_get_virtual() on the alpha is currently
 	 * broken and returns a physical address instead of a kernel
 	 * virtual address. Consequently, we need to do a little
 	 * extra mangling of the vhandle on the alpha. This should
 	 * eventually be fixed! The whole idea here is to get rid
 	 * of platform dependencies.
 	 */
 #ifdef __alpha__
 	if (pci_cvt_to_bwx(sc->bge_vhandle))
 		sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
 	else
 		sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
 	sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
 #endif
 
 	/* Allocate interrupt */
 	rid = 0;
 	
 	sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
 	    RF_SHAREABLE | RF_ACTIVE);
 
 	if (sc->bge_irq == NULL) {
 		printf("bge%d: couldn't map interrupt\n", unit);
 		error = ENXIO;
 		goto fail;
 	}
 
 	error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
 	   bge_intr, sc, &sc->bge_intrhand);
 
 	if (error) {
 		bge_release_resources(sc);
 		printf("bge%d: couldn't set up irq\n", unit);
 		goto fail;
 	}
 
 	sc->bge_unit = unit;
 
 	/* Try to reset the chip. */
 	bge_reset(sc);
 
 	if (bge_chipinit(sc)) {
 		printf("bge%d: chip initialization failed\n", sc->bge_unit);
 		bge_release_resources(sc);
 		error = ENXIO;
 		goto fail;
 	}
 
 	/*
 	 * Get station address from the EEPROM.
 	 */
 	if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
 	    BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
 		printf("bge%d: failed to read station address\n", unit);
 		bge_release_resources(sc);
 		error = ENXIO;
 		goto fail;
 	}
 
 	/*
 	 * A Broadcom chip was detected. Inform the world.
 	 */
 	printf("bge%d: Ethernet address: %6D\n", unit,
 	    sc->arpcom.ac_enaddr, ":");
 
 	/* Allocate the general information block and ring buffers. */
 	sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
 	    M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 
 	if (sc->bge_rdata == NULL) {
 		bge_release_resources(sc);
 		error = ENXIO;
 		printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
 		goto fail;
 	}
 
 	bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
 
 	/* Try to allocate memory for jumbo buffers. */
 	if (bge_alloc_jumbo_mem(sc)) {
 		printf("bge%d: jumbo buffer allocation "
 		    "failed\n", sc->bge_unit);
 		bge_release_resources(sc);
 		error = ENXIO;
 		goto fail;
 	}
 
 	/* Set default tuneable values. */
 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
 	sc->bge_rx_coal_ticks = 150;
 	sc->bge_tx_coal_ticks = 150;
 	sc->bge_rx_max_coal_bds = 64;
 	sc->bge_tx_max_coal_bds = 128;
 
 	/* Set up ifnet structure */
 	ifp = &sc->arpcom.ac_if;
 	ifp->if_softc = sc;
 	ifp->if_unit = sc->bge_unit;
 	ifp->if_name = "bge";
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = bge_ioctl;
 	ifp->if_output = ether_output;
 	ifp->if_start = bge_start;
 	ifp->if_watchdog = bge_watchdog;
 	ifp->if_init = bge_init;
 	ifp->if_mtu = ETHERMTU;
 	ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
 	ifp->if_hwassist = BGE_CSUM_FEATURES;
 	ifp->if_capabilities = IFCAP_HWCSUM;
 	ifp->if_capenable = ifp->if_capabilities;
 
 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
 	if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
 		sc->bge_tbi = 1;
 
 	if (sc->bge_tbi) {
 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
 		    bge_ifmedia_upd, bge_ifmedia_sts);
 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
 		ifmedia_add(&sc->bge_ifmedia,
 		    IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
 	} else {
 		/*
 		 * Do transceiver setup.
 		 */
 		if (mii_phy_probe(dev, &sc->bge_miibus,
 		    bge_ifmedia_upd, bge_ifmedia_sts)) {
 			printf("bge%d: MII without any PHY!\n", sc->bge_unit);
 			bge_release_resources(sc);
 			bge_free_jumbo_mem(sc);
 			error = ENXIO;
 			goto fail;
 		}
 	}
 
 	/*
 	 * Call MI attach routine.
 	 */
 	ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
 	callout_handle_init(&sc->bge_stat_ch);
 
 fail:
 	splx(s);
 
 	return(error);
 }
 
 static int
 bge_detach(dev)
 	device_t dev;
 {
 	struct bge_softc *sc;
 	struct ifnet *ifp;
 	int s;
 
 	s = splimp();
 
 	sc = device_get_softc(dev);
 	ifp = &sc->arpcom.ac_if;
 
 	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
 	bge_stop(sc);
 	bge_reset(sc);
 
 	if (sc->bge_tbi) {
 		ifmedia_removeall(&sc->bge_ifmedia);
 	} else {
 		bus_generic_detach(dev);
 		device_delete_child(dev, sc->bge_miibus);
 	}
 
 	bge_release_resources(sc);
 	bge_free_jumbo_mem(sc);
 
 	splx(s);
 
 	return(0);
 }
 
 static void
 bge_release_resources(sc)
 	struct bge_softc *sc;
 {
         device_t dev;
 
         dev = sc->bge_dev;
 
 	if (sc->bge_vpd_prodname != NULL)
 		free(sc->bge_vpd_prodname, M_DEVBUF);
 
 	if (sc->bge_vpd_readonly != NULL)
 		free(sc->bge_vpd_readonly, M_DEVBUF);
 
         if (sc->bge_intrhand != NULL)
                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
 
         if (sc->bge_irq != NULL)
 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
 
         if (sc->bge_res != NULL)
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    BGE_PCI_BAR0, sc->bge_res);
 
         if (sc->bge_rdata != NULL)
 		contigfree(sc->bge_rdata,
 		    sizeof(struct bge_ring_data), M_DEVBUF);
 
         return;
 }
 
 static void
 bge_reset(sc)
 	struct bge_softc *sc;
 {
 	device_t dev;
 	u_int32_t cachesize, command, pcistate;
 	int i, val = 0;
 
 	dev = sc->bge_dev;
 
 	/* Save some important PCI state. */
 	cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
 	command = pci_read_config(dev, BGE_PCI_CMD, 4);
 	pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
 
 	pci_write_config(dev, BGE_PCI_MISC_CTL,
 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
 	    BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
 
 	/* Issue global reset */
 	bge_writereg_ind(sc, BGE_MISC_CFG,
 	    BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
 
 	DELAY(1000);
 
 	/* Reset some of the PCI state that got zapped by reset */
 	pci_write_config(dev, BGE_PCI_MISC_CTL,
 	    BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
 	    BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
 	pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
 	pci_write_config(dev, BGE_PCI_CMD, command, 4);
 	bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
 
 	/*
 	 * Prevent PXE restart: write a magic number to the
 	 * general communications memory at 0xB50.
 	 */
 	bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
 	/*
 	 * Poll the value location we just wrote until
 	 * we see the 1's complement of the magic number.
 	 * This indicates that the firmware initialization
 	 * is complete.
 	 */
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
 		if (val == ~BGE_MAGIC_NUMBER)
 			break;
 		DELAY(10);
 	}
 	
 	if (i == BGE_TIMEOUT) {
 		printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
 		return;
 	}
 
 	/*
 	 * XXX Wait for the value of the PCISTATE register to
 	 * return to its original pre-reset state. This is a
 	 * fairly good indicator of reset completion. If we don't
 	 * wait for the reset to fully complete, trying to read
 	 * from the device's non-PCI registers may yield garbage
 	 * results.
 	 */
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
 			break;
 		DELAY(10);
 	}
 
 	/* Enable memory arbiter. */
 	CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 
 	/* Fix up byte swapping */
 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
 	    BGE_MODECTL_BYTESWAP_DATA);
 
 	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 
 	DELAY(10000);
 
 	return;
 }
 
 /*
  * Frame reception handling. This is called if there's a frame
  * on the receive return list.
  *
  * Note: we have to be able to handle two possibilities here:
  * 1) the frame is from the jumbo recieve ring
  * 2) the frame is from the standard receive ring
  */
 
 static void
 bge_rxeof(sc)
 	struct bge_softc *sc;
 {
 	struct ifnet *ifp;
 	int stdcnt = 0, jumbocnt = 0;
 
 	ifp = &sc->arpcom.ac_if;
 
 	while(sc->bge_rx_saved_considx !=
 	    sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
 		struct bge_rx_bd	*cur_rx;
 		u_int32_t		rxidx;
 		struct ether_header	*eh;
 		struct mbuf		*m = NULL;
 		u_int16_t		vlan_tag = 0;
 		int			have_tag = 0;
 
 		cur_rx =
 	    &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
 
 		rxidx = cur_rx->bge_idx;
 		BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT);
 
 		if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
 			have_tag = 1;
 			vlan_tag = cur_rx->bge_vlan_tag;
 		}
 
 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
 			sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
 			jumbocnt++;
 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
 				ifp->if_ierrors++;
 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
 				continue;
 			}
 			if (bge_newbuf_jumbo(sc,
 			    sc->bge_jumbo, NULL) == ENOBUFS) {
 				ifp->if_ierrors++;
 				bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
 				continue;
 			}
 		} else {
 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
 			sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
 			stdcnt++;
 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
 				ifp->if_ierrors++;
 				bge_newbuf_std(sc, sc->bge_std, m);
 				continue;
 			}
 			if (bge_newbuf_std(sc, sc->bge_std,
 			    NULL) == ENOBUFS) {
 				ifp->if_ierrors++;
 				bge_newbuf_std(sc, sc->bge_std, m);
 				continue;
 			}
 		}
 
 		ifp->if_ipackets++;
 		eh = mtod(m, struct ether_header *);
 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len;
 		m->m_pkthdr.rcvif = ifp;
 
 		/* Remove header from mbuf and pass it on. */
 		m_adj(m, sizeof(struct ether_header));
 
 #if 0 /* currently broken for some packets, possibly related to TCP options */
 		if (ifp->if_hwassist) {
 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
 			if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
 				m->m_pkthdr.csum_data =
 				    cur_rx->bge_tcp_udp_csum;
 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
 			}
 		}
 #endif
 
 		/*
 		 * If we received a packet with a vlan tag, pass it
 		 * to vlan_input() instead of ether_input().
 		 */
 		if (have_tag) {
 			VLAN_INPUT_TAG(eh, m, vlan_tag);
 			have_tag = vlan_tag = 0;
 			continue;
 		}
 
 		ether_input(ifp, eh, m);
 	}
 
 	CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
 	if (stdcnt)
 		CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 	if (jumbocnt)
 		CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 
 	return;
 }
 
 static void
 bge_txeof(sc)
 	struct bge_softc *sc;
 {
 	struct bge_tx_bd *cur_tx = NULL;
 	struct ifnet *ifp;
 
 	ifp = &sc->arpcom.ac_if;
 
 	/*
 	 * Go through our tx ring and free mbufs for those
 	 * frames that have been sent.
 	 */
 	while (sc->bge_tx_saved_considx !=
 	    sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
 		u_int32_t		idx = 0;
 
 		idx = sc->bge_tx_saved_considx;
 		cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
 			ifp->if_opackets++;
 		if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
 			m_freem(sc->bge_cdata.bge_tx_chain[idx]);
 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
 		}
 		sc->bge_txcnt--;
 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
 		ifp->if_timer = 0;
 	}
 
 	if (cur_tx != NULL)
 		ifp->if_flags &= ~IFF_OACTIVE;
 
 	return;
 }
 
 static void
 bge_intr(xsc)
 	void *xsc;
 {
 	struct bge_softc *sc;
 	struct ifnet *ifp;
 
 	sc = xsc;
 	ifp = &sc->arpcom.ac_if;
 
 #ifdef notdef
 	/* Avoid this for now -- checking this register is expensive. */
 	/* Make sure this is really our interrupt. */
 	if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
 		return;
 #endif
 	/* Ack interrupt and stop others from occuring. */
 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
 
 	/* Process link state changes. */
 	if (sc->bge_rdata->bge_status_block.bge_status &
 	    BGE_STATFLAG_LINKSTATE_CHANGED) {
 		sc->bge_link = 0;
 		untimeout(bge_tick, sc, sc->bge_stat_ch);
 		bge_tick(sc);
 		/* ack the event to clear/reset it */
 		CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
 		    BGE_MACSTAT_CFG_CHANGED);
 		CSR_WRITE_4(sc, BGE_MI_STS, 0);
 	}
 
 	if (ifp->if_flags & IFF_RUNNING) {
 		/* Check RX return ring producer/consumer */
 		bge_rxeof(sc);
 
 		/* Check TX ring producer/consumer */
 		bge_txeof(sc);
 	}
 
 	bge_handle_events(sc);
 
 	/* Re-enable interrupts. */
 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
 
 	if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
 		bge_start(ifp);
 
 	return;
 }
 
 static void
 bge_tick(xsc)
 	void *xsc;
 {
 	struct bge_softc *sc;
 	struct mii_data *mii = NULL;
 	struct ifmedia *ifm = NULL;
 	struct ifnet *ifp;
 	int s;
 
 	sc = xsc;
 	ifp = &sc->arpcom.ac_if;
 
 	s = splimp();
 
 	bge_stats_update(sc);
 	sc->bge_stat_ch = timeout(bge_tick, sc, hz);
 	if (sc->bge_link)
 		return;
 
 	if (sc->bge_tbi) {
 		ifm = &sc->bge_ifmedia;
 		if (CSR_READ_4(sc, BGE_MAC_STS) &
 		    BGE_MACSTAT_TBI_PCS_SYNCHED) {
 			sc->bge_link++;
 			CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
 			printf("bge%d: gigabit link up\n", sc->bge_unit);
 			if (ifp->if_snd.ifq_head != NULL)
 				bge_start(ifp);
 		}
 		return;
 	}
 
 	mii = device_get_softc(sc->bge_miibus);
 	mii_tick(mii);
  
 	if (!sc->bge_link) {
 		mii_pollstat(mii);
 		if (mii->mii_media_status & IFM_ACTIVE &&
 		    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 			sc->bge_link++;
 			if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 				printf("bge%d: gigabit link up\n",
 				   sc->bge_unit);
 			if (ifp->if_snd.ifq_head != NULL)
 				bge_start(ifp);
 		}
 	}
 
 	splx(s);
 
 	return;
 }
 
 static void
 bge_stats_update(sc)
 	struct bge_softc *sc;
 {
 	struct ifnet *ifp;
 	struct bge_stats *stats;
 
 	ifp = &sc->arpcom.ac_if;
 
 	stats = (struct bge_stats *)(sc->bge_vhandle +
 	    BGE_MEMWIN_START + BGE_STATS_BLOCK);
 
 	ifp->if_collisions +=
 	   (stats->dot3StatsSingleCollisionFrames.bge_addr_lo +
 	   stats->dot3StatsMultipleCollisionFrames.bge_addr_lo +
 	   stats->dot3StatsExcessiveCollisions.bge_addr_lo +
 	   stats->dot3StatsLateCollisions.bge_addr_lo) -
 	   ifp->if_collisions;
 
 #ifdef notdef
 	ifp->if_collisions +=
 	   (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
 	   sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
 	   ifp->if_collisions;
 #endif
 
 	return;
 }
 
 /*
  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
  * pointers to descriptors.
  */
 static int
 bge_encap(sc, m_head, txidx)
 	struct bge_softc *sc;
 	struct mbuf *m_head;
 	u_int32_t *txidx;
 {
 	struct bge_tx_bd	*f = NULL;
 	struct mbuf		*m;
 	u_int32_t		frag, cur, cnt = 0;
 	u_int16_t		csum_flags = 0;
 	struct ifvlan		*ifv = NULL;
 
 	if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
 	    m_head->m_pkthdr.rcvif != NULL &&
 	    m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
 		ifv = m_head->m_pkthdr.rcvif->if_softc;
 
 	m = m_head;
 	cur = frag = *txidx;
 
 	if (m_head->m_pkthdr.csum_flags) {
 		if (m_head->m_pkthdr.csum_flags & CSUM_IP)
 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
 		if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
 		if (m_head->m_flags & M_LASTFRAG)
 			csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
 		else if (m_head->m_flags & M_FRAG)
 			csum_flags |= BGE_TXBDFLAG_IP_FRAG;
 	}
 	/*
  	 * Start packing the mbufs in this chain into
 	 * the fragment pointers. Stop when we run out
  	 * of fragments or hit the end of the mbuf chain.
 	 */
 	for (m = m_head; m != NULL; m = m->m_next) {
 		if (m->m_len != 0) {
 			f = &sc->bge_rdata->bge_tx_ring[frag];
 			if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
 				break;
 			BGE_HOSTADDR(f->bge_addr) =
 			   vtophys(mtod(m, vm_offset_t));
 			f->bge_len = m->m_len;
 			f->bge_flags = csum_flags;
 			if (ifv != NULL) {
 				f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
 				f->bge_vlan_tag = ifv->ifv_tag;
 			} else {
 				f->bge_vlan_tag = 0;
 			}
 			/*
 			 * Sanity check: avoid coming within 16 descriptors
 			 * of the end of the ring.
 			 */
 			if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
 				return(ENOBUFS);
 			cur = frag;
 			BGE_INC(frag, BGE_TX_RING_CNT);
 			cnt++;
 		}
 	}
 
 	if (m != NULL)
 		return(ENOBUFS);
 
 	if (frag == sc->bge_tx_saved_considx)
 		return(ENOBUFS);
 
 	sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
 	sc->bge_cdata.bge_tx_chain[cur] = m_head;
 	sc->bge_txcnt += cnt;
 
 	*txidx = frag;
 
 	return(0);
 }
 
 /*
  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
  * to the mbuf data regions directly in the transmit descriptors.
  */
 static void
 bge_start(ifp)
 	struct ifnet *ifp;
 {
 	struct bge_softc *sc;
 	struct mbuf *m_head = NULL;
 	u_int32_t prodidx = 0;
 
 	sc = ifp->if_softc;
 
 	if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
 		return;
 
 	prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
 
 	while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
 		IF_DEQUEUE(&ifp->if_snd, m_head);
 		if (m_head == NULL)
 			break;
 
 		/*
 		 * XXX
 		 * safety overkill.  If this is a fragmented packet chain
 		 * with delayed TCP/UDP checksums, then only encapsulate
 		 * it if we have enough descriptors to handle the entire
 		 * chain at once.
 		 * (paranoia -- may not actually be needed)
 		 */
 		if (m_head->m_flags & M_FIRSTFRAG &&
 		    m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
 			if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
 			    m_head->m_pkthdr.csum_data + 16) {
 				IF_PREPEND(&ifp->if_snd, m_head);
 				ifp->if_flags |= IFF_OACTIVE;
 				break;
 			}
 		}
 
 		/*
 		 * Pack the data into the transmit ring. If we
 		 * don't have room, set the OACTIVE flag and wait
 		 * for the NIC to drain the ring.
 		 */
 		if (bge_encap(sc, m_head, &prodidx)) {
 			IF_PREPEND(&ifp->if_snd, m_head);
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
 		}
 
 		/*
 		 * If there's a BPF listener, bounce a copy of this frame
 		 * to him.
 		 */
 		if (ifp->if_bpf)
 			bpf_mtap(ifp, m_head);
 	}
 
 	/* Transmit */
 	CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
 
 	/*
 	 * Set a timeout in case the chip goes out to lunch.
 	 */
 	ifp->if_timer = 5;
 
 	return;
 }
 
 /*
  * If we have a BCM5400 or BCM5401 PHY, we need to properly
  * program its internal DSP. Failing to do this can result in
  * massive packet loss at 1Gb speeds.
  */
 static void
 bge_phy_hack(sc)
 	struct bge_softc *sc;
 {
 	struct bge_bcom_hack bhack[] = {
 	{ BRGPHY_MII_AUXCTL, 0x4C20 },
 	{ BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
 	{ BRGPHY_MII_DSP_RW_PORT, 0x1804 },
 	{ BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
 	{ BRGPHY_MII_DSP_RW_PORT, 0x1204 },
 	{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
 	{ BRGPHY_MII_DSP_RW_PORT, 0x0132 },
 	{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
 	{ BRGPHY_MII_DSP_RW_PORT, 0x0232 },
 	{ BRGPHY_MII_DSP_ADDR_REG, 0x201F },
 	{ BRGPHY_MII_DSP_RW_PORT, 0x0A20 },
 	{ 0, 0 } };
 	u_int16_t vid, did;
 	int i;
 
 	vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1);
 	did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2);
 
 	if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM &&
 	    (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 ||
 	    MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) {
 		i = 0;
 		while(bhack[i].reg) {
 			bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg,
 			    bhack[i].val);
 			i++;
 		}
 	}
 
 	return;
 }
 
 static void
 bge_init(xsc)
 	void *xsc;
 {
 	struct bge_softc *sc = xsc;
 	struct ifnet *ifp;
 	u_int16_t *m;
         int s;
 
 	s = splimp();
 
 	ifp = &sc->arpcom.ac_if;
 
 	if (ifp->if_flags & IFF_RUNNING)
 		return;
 
 	/* Cancel pending I/O and flush buffers. */
 	bge_stop(sc);
 	bge_reset(sc);
 	bge_chipinit(sc);
 
 	/*
 	 * Init the various state machines, ring
 	 * control blocks and firmware.
 	 */
 	if (bge_blockinit(sc)) {
 		printf("bge%d: initialization failure\n", sc->bge_unit);
 		splx(s);
 		return;
 	}
 
 	ifp = &sc->arpcom.ac_if;
 
 	/* Specify MTU. */
 	CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
 	    ETHER_HDR_LEN + ETHER_CRC_LEN);
 
 	/* Load our MAC address. */
 	m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
 
 	/* Enable or disable promiscuous mode as needed. */
 	if (ifp->if_flags & IFF_PROMISC) {
 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
 	} else {
 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
 	}
 
 	/* Program multicast filter. */
 	bge_setmulti(sc);
 
 	/* Init RX ring. */
 	bge_init_rx_ring_std(sc);
 
 	/* Init jumbo RX ring. */
 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 		bge_init_rx_ring_jumbo(sc);
 
 	/* Init our RX return ring index */
 	sc->bge_rx_saved_considx = 0;
 
 	/* Init TX ring. */
 	bge_init_tx_ring(sc);
 
 	/* Turn on transmitter */
 	BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
 
 	/* Turn on receiver */
 	BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 
 	/* Tell firmware we're alive. */
 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 
 	/* Enable host interrupts. */
 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
 
 	bge_ifmedia_upd(ifp);
 
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 
 	splx(s);
 
 	sc->bge_stat_ch = timeout(bge_tick, sc, hz);
 
 	return;
 }
 
 /*
  * Set media options.
  */
 static int
 bge_ifmedia_upd(ifp)
 	struct ifnet *ifp;
 {
 	struct bge_softc *sc;
 	struct mii_data *mii;
 	struct ifmedia *ifm;
 
 	sc = ifp->if_softc;
 	ifm = &sc->bge_ifmedia;
 
 	/* If this is a 1000baseX NIC, enable the TBI port. */
 	if (sc->bge_tbi) {
 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 			return(EINVAL);
 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
 		case IFM_AUTO:
 			break;
 		case IFM_1000_SX:
 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 				BGE_CLRBIT(sc, BGE_MAC_MODE,
 				    BGE_MACMODE_HALF_DUPLEX);
 			} else {
 				BGE_SETBIT(sc, BGE_MAC_MODE,
 				    BGE_MACMODE_HALF_DUPLEX);
 			}
 			break;
 		default:
 			return(EINVAL);
 		}
 		return(0);
 	}
 
 	mii = device_get_softc(sc->bge_miibus);
 	sc->bge_link = 0;
 	if (mii->mii_instance) {
 		struct mii_softc *miisc;
 		for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
 		    miisc = LIST_NEXT(miisc, mii_list))
 			mii_phy_reset(miisc);
 	}
 	bge_phy_hack(sc);
 	mii_mediachg(mii);
 
 	return(0);
 }
 
 /*
  * Report current media status.
  */
 static void
 bge_ifmedia_sts(ifp, ifmr)
 	struct ifnet *ifp;
 	struct ifmediareq *ifmr;
 {
 	struct bge_softc *sc;
 	struct mii_data *mii;
 
 	sc = ifp->if_softc;
 
 	if (sc->bge_tbi) {
 		ifmr->ifm_status = IFM_AVALID;
 		ifmr->ifm_active = IFM_ETHER;
 		if (CSR_READ_4(sc, BGE_MAC_STS) &
 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
 			ifmr->ifm_status |= IFM_ACTIVE;
 		ifmr->ifm_active |= IFM_1000_SX;
 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
 			ifmr->ifm_active |= IFM_HDX;	
 		else
 			ifmr->ifm_active |= IFM_FDX;
 		return;
 	}
 
 	mii = device_get_softc(sc->bge_miibus);
 	mii_pollstat(mii);
 	ifmr->ifm_active = mii->mii_media_active;
 	ifmr->ifm_status = mii->mii_media_status;
 
 	return;
 }
 
 static int
 bge_ioctl(ifp, command, data)
 	struct ifnet *ifp;
 	u_long command;
 	caddr_t data;
 {
 	struct bge_softc *sc = ifp->if_softc;
 	struct ifreq *ifr = (struct ifreq *) data;
 	int s, mask, error = 0;
 	struct mii_data *mii;
 
 	s = splimp();
 
 	switch(command) {
 	case SIOCSIFADDR:
 	case SIOCGIFADDR:
 		error = ether_ioctl(ifp, command, data);
 		break;
 	case SIOCSIFMTU:
 		if (ifr->ifr_mtu > BGE_JUMBO_MTU)
 			error = EINVAL;
 		else {
 			ifp->if_mtu = ifr->ifr_mtu;
 			ifp->if_flags &= ~IFF_RUNNING;
 			bge_init(sc);
 		}
 		break;
 	case SIOCSIFFLAGS:
 		if (ifp->if_flags & IFF_UP) {
 			/*
 			 * If only the state of the PROMISC flag changed,
 			 * then just use the 'set promisc mode' command
 			 * instead of reinitializing the entire NIC. Doing
 			 * a full re-init means reloading the firmware and
 			 * waiting for it to start up, which may take a
 			 * second or two.
 			 */
 			if (ifp->if_flags & IFF_RUNNING &&
 			    ifp->if_flags & IFF_PROMISC &&
 			    !(sc->bge_if_flags & IFF_PROMISC)) {
 				BGE_SETBIT(sc, BGE_RX_MODE,
 				    BGE_RXMODE_RX_PROMISC);
 			} else if (ifp->if_flags & IFF_RUNNING &&
 			    !(ifp->if_flags & IFF_PROMISC) &&
 			    sc->bge_if_flags & IFF_PROMISC) {
 				BGE_CLRBIT(sc, BGE_RX_MODE,
 				    BGE_RXMODE_RX_PROMISC);
 			} else
 				bge_init(sc);
 		} else {
 			if (ifp->if_flags & IFF_RUNNING) {
 				bge_stop(sc);
 			}
 		}
 		sc->bge_if_flags = ifp->if_flags;
 		error = 0;
 		break;
 	case SIOCADDMULTI:
 	case SIOCDELMULTI:
 		if (ifp->if_flags & IFF_RUNNING) {
 			bge_setmulti(sc);
 			error = 0;
 		}
 		break;
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
 		if (sc->bge_tbi) {
 			error = ifmedia_ioctl(ifp, ifr,
 			    &sc->bge_ifmedia, command);
 		} else {
 			mii = device_get_softc(sc->bge_miibus);
 			error = ifmedia_ioctl(ifp, ifr,
 			    &mii->mii_media, command);
 		}
 		break;
         case SIOCSIFCAP:
 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 		if (mask & IFCAP_HWCSUM) {
 			if (IFCAP_HWCSUM & ifp->if_capenable)
 				ifp->if_capenable &= ~IFCAP_HWCSUM;
 			else
 				ifp->if_capenable |= IFCAP_HWCSUM;
 		}
 		error = 0;
 		break;
 	default:
 		error = EINVAL;
 		break;
 	}
 
 	(void)splx(s);
 
 	return(error);
 }
 
 static void
 bge_watchdog(ifp)
 	struct ifnet *ifp;
 {
 	struct bge_softc *sc;
 
 	sc = ifp->if_softc;
 
 	printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
 
 	ifp->if_flags &= ~IFF_RUNNING;
 	bge_init(sc);
 
 	ifp->if_oerrors++;
 
 	return;
 }
 
 /*
  * Stop the adapter and free any mbufs allocated to the
  * RX and TX lists.
  */
 static void
 bge_stop(sc)
 	struct bge_softc *sc;
 {
 	struct ifnet *ifp;
 	struct ifmedia_entry *ifm;
 	struct mii_data *mii = NULL;
 	int mtmp, itmp;
 
 	ifp = &sc->arpcom.ac_if;
 
 	if (!sc->bge_tbi)
 		mii = device_get_softc(sc->bge_miibus);
 
 	untimeout(bge_tick, sc, sc->bge_stat_ch);
 
 	/*
 	 * Disable all of the receiver blocks
 	 */
 	BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
 
 	/*
 	 * Disable all of the transmit blocks
 	 */
 	BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 
 	/*
 	 * Shut down all of the memory managers and related
 	 * state machines.
 	 */
 	BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 	BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
 	BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 
 	/* Disable host interrupts. */
 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
 	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
 
 	/*
 	 * Tell firmware we're shutting down.
 	 */
 	BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 
 	/* Free the RX lists. */
 	bge_free_rx_ring_std(sc);
 
 	/* Free jumbo RX list. */
 	bge_free_rx_ring_jumbo(sc);
 
 	/* Free TX buffers. */
 	bge_free_tx_ring(sc);
 
 	/*
 	 * Isolate/power down the PHY, but leave the media selection
 	 * unchanged so that things will be put back to normal when
 	 * we bring the interface back up.
 	 */
 	if (!sc->bge_tbi) {
 		itmp = ifp->if_flags;
 		ifp->if_flags |= IFF_UP;
 		ifm = mii->mii_media.ifm_cur;
 		mtmp = ifm->ifm_media;
 		ifm->ifm_media = IFM_ETHER|IFM_NONE;
 		mii_mediachg(mii);
 		ifm->ifm_media = mtmp;
 		ifp->if_flags = itmp;
 	}
 
 	sc->bge_link = 0;
 
 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
 
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 
 	return;
 }
 
 /*
  * Stop all chip I/O so that the kernel's probe routines don't
  * get confused by errant DMAs when rebooting.
  */
 static void
 bge_shutdown(dev)
 	device_t dev;
 {
 	struct bge_softc *sc;
 
 	sc = device_get_softc(dev);
 
 	bge_stop(sc); 
 	bge_reset(sc);
 
 	return;
 }
Index: stable/4/sys/dev/bge/if_bgereg.h
===================================================================
--- stable/4/sys/dev/bge/if_bgereg.h	(revision 90007)
+++ stable/4/sys/dev/bge/if_bgereg.h	(revision 90008)
@@ -1,2137 +1,2143 @@
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  *
  * $FreeBSD$
  */
 
 /*
  * BCM570x memory map. The internal memory layout varies somewhat
  * depending on whether or not we have external SSRAM attached.
  * The BCM5700 can have up to 16MB of external memory. The BCM5701
  * is apparently not designed to use external SSRAM. The mappings
  * up to the first 4 send rings are the same for both internal and
  * external memory configurations. Note that mini RX ring space is
  * only available with external SSRAM configurations, which means
  * the mini RX ring is not supported on the BCM5701.
  *
  * The NIC's memory can be accessed by the host in one of 3 ways:
  *
  * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
  *    registers in PCI config space can be used to read any 32-bit
  *    address within the NIC's memory.
  *
  * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
  *    space can be used in conjunction with the memory window in the
  *    device register space at offset 0x8000 to read any 32K chunk
  *    of NIC memory.
  *
  * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
  *    set, the device I/O mapping consumes 32MB of host address space,
  *    allowing all of the registers and internal NIC memory to be
  *    accessed directly. NIC memory addresses are offset by 0x01000000.
  *    Flat mode consumes so much host address space that it is not
  *    recommended.
  */
 #define BGE_PAGE_ZERO			0x00000000
 #define BGE_PAGE_ZERO_END		0x000000FF
 #define BGE_SEND_RING_RCB		0x00000100
 #define BGE_SEND_RING_RCB_END		0x000001FF
 #define BGE_RX_RETURN_RING_RCB		0x00000200
 #define BGE_RX_RETURN_RING_RCB_END	0x000002FF
 #define BGE_STATS_BLOCK			0x00000300
 #define BGE_STATS_BLOCK_END		0x00000AFF
 #define BGE_STATUS_BLOCK		0x00000B00
 #define BGE_STATUS_BLOCK_END		0x00000B4F
 #define BGE_SOFTWARE_GENCOMM		0x00000B50
 #define BGE_SOFTWARE_GENCOMM_END	0x00000FFF
 #define BGE_UNMAPPED			0x00001000
 #define BGE_UNMAPPED_END		0x00001FFF
 #define BGE_DMA_DESCRIPTORS		0x00002000
 #define BGE_DMA_DESCRIPTORS_END		0x00003FFF
 #define BGE_SEND_RING_1_TO_4		0x00004000
 #define BGE_SEND_RING_1_TO_4_END	0x00005FFF
 
 /* Mappings for internal memory configuration */
 #define BGE_STD_RX_RINGS		0x00006000
 #define BGE_STD_RX_RINGS_END		0x00006FFF
 #define BGE_JUMBO_RX_RINGS		0x00007000
 #define BGE_JUMBO_RX_RINGS_END		0x00007FFF
 #define BGE_BUFFPOOL_1			0x00008000
 #define BGE_BUFFPOOL_1_END		0x0000FFFF
 #define BGE_BUFFPOOL_2			0x00010000 /* or expansion ROM */
 #define BGE_BUFFPOOL_2_END		0x00017FFF
 #define BGE_BUFFPOOL_3			0x00018000 /* or expansion ROM */
 #define BGE_BUFFPOOL_3_END		0x0001FFFF
 
 /* Mappings for external SSRAM configurations */
 #define BGE_SEND_RING_5_TO_6		0x00006000
 #define BGE_SEND_RING_5_TO_6_END	0x00006FFF
 #define BGE_SEND_RING_7_TO_8		0x00007000
 #define BGE_SEND_RING_7_TO_8_END	0x00007FFF
 #define BGE_SEND_RING_9_TO_16		0x00008000
 #define BGE_SEND_RING_9_TO_16_END	0x0000BFFF
 #define BGE_EXT_STD_RX_RINGS		0x0000C000
 #define BGE_EXT_STD_RX_RINGS_END	0x0000CFFF
 #define BGE_EXT_JUMBO_RX_RINGS		0x0000D000
 #define BGE_EXT_JUMBO_RX_RINGS_END	0x0000DFFF
 #define BGE_MINI_RX_RINGS		0x0000E000
 #define BGE_MINI_RX_RINGS_END		0x0000FFFF
 #define BGE_AVAIL_REGION1		0x00010000 /* or expansion ROM */
 #define BGE_AVAIL_REGION1_END		0x00017FFF
 #define BGE_AVAIL_REGION2		0x00018000 /* or expansion ROM */
 #define BGE_AVAIL_REGION2_END		0x0001FFFF
 #define BGE_EXT_SSRAM			0x00020000
 #define BGE_EXT_SSRAM_END		0x000FFFFF
 
 
 /*
  * BCM570x register offsets. These are memory mapped registers
  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
  * Each register must be accessed using 32 bit operations.
  *
  * All registers are accessed through a 32K shared memory block.
  * The first group of registers are actually copies of the PCI
  * configuration space registers.
  */
 
 /*
  * PCI registers defined in the PCI 2.2 spec.
  */
 #define BGE_PCI_VID			0x00
 #define BGE_PCI_DID			0x02
 #define BGE_PCI_CMD			0x04
 #define BGE_PCI_STS			0x06
 #define BGE_PCI_REV			0x08
 #define BGE_PCI_CLASS			0x09
 #define BGE_PCI_CACHESZ			0x0C
 #define BGE_PCI_LATTIMER		0x0D
 #define BGE_PCI_HDRTYPE			0x0E
 #define BGE_PCI_BIST			0x0F
 #define BGE_PCI_BAR0			0x10
 #define BGE_PCI_BAR1			0x14
 #define BGE_PCI_SUBSYS			0x2C
 #define BGE_PCI_SUBVID			0x2E
 #define BGE_PCI_ROMBASE			0x30
 #define BGE_PCI_CAPPTR			0x34
 #define BGE_PCI_INTLINE			0x3C
 #define BGE_PCI_INTPIN			0x3D
 #define BGE_PCI_MINGNT			0x3E
 #define BGE_PCI_MAXLAT			0x3F
 #define BGE_PCI_PCIXCAP			0x40
 #define BGE_PCI_NEXTPTR_PM		0x41
 #define BGE_PCI_PCIX_CMD		0x42
 #define BGE_PCI_PCIX_STS		0x44
 #define BGE_PCI_PWRMGMT_CAPID		0x48
 #define BGE_PCI_NEXTPTR_VPD		0x49
 #define BGE_PCI_PWRMGMT_CAPS		0x4A
 #define BGE_PCI_PWRMGMT_CMD		0x4C
 #define BGE_PCI_PWRMGMT_STS		0x4D
 #define BGE_PCI_PWRMGMT_DATA		0x4F
 #define BGE_PCI_VPD_CAPID		0x50
 #define BGE_PCI_NEXTPTR_MSI		0x51
 #define BGE_PCI_VPD_ADDR		0x52
 #define BGE_PCI_VPD_DATA		0x54
 #define BGE_PCI_MSI_CAPID		0x58
 #define BGE_PCI_NEXTPTR_NONE		0x59
 #define BGE_PCI_MSI_CTL			0x5A
 #define BGE_PCI_MSI_ADDR_HI		0x5C
 #define BGE_PCI_MSI_ADDR_LO		0x60
 #define BGE_PCI_MSI_DATA		0x64
 
 /*
  * PCI registers specific to the BCM570x family.
  */
 #define BGE_PCI_MISC_CTL		0x68
 #define BGE_PCI_DMA_RW_CTL		0x6C
 #define BGE_PCI_PCISTATE		0x70
 #define BGE_PCI_CLKCTL			0x74
 #define BGE_PCI_REG_BASEADDR		0x78
 #define BGE_PCI_MEMWIN_BASEADDR		0x7C
 #define BGE_PCI_REG_DATA		0x80
 #define BGE_PCI_MEMWIN_DATA		0x84
 #define BGE_PCI_MODECTL			0x88
 #define BGE_PCI_MISC_CFG		0x8C
 #define BGE_PCI_MISC_LOCALCTL		0x90
 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI	0x98
 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO	0x9C
 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI	0xA0
 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO	0xA4
 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI	0xA8
 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO	0xAC
 #define BGE_PCI_ISR_MBX_HI		0xB0
 #define BGE_PCI_ISR_MBX_LO		0xB4
 
 /* PCI Misc. Host control register */
 #define BGE_PCIMISCCTL_CLEAR_INTA	0x00000001
 #define BGE_PCIMISCCTL_MASK_PCI_INTR	0x00000002
 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP	0x00000004
 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP	0x00000008
 #define BGE_PCIMISCCTL_PCISTATE_RW	0x00000010
 #define BGE_PCIMISCCTL_CLOCKCTL_RW	0x00000020
 #define BGE_PCIMISCCTL_REG_WORDSWAP	0x00000040
 #define BGE_PCIMISCCTL_INDIRECT_ACCESS	0x00000080
 #define BGE_PCIMISCCTL_ASICREV		0xFFFF0000
 
 #define BGE_BIGENDIAN_INIT						\
 	(BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP|				\
 	BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA|	\
 	BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR)
 
 #define BGE_LITTLEENDIAN_INIT						\
 	(BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR|	\
 	BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS)
 
 #define BGE_ASICREV_TIGON_I		0x40000000
 #define BGE_ASICREV_TIGON_II		0x60000000
 #define BGE_ASICREV_BCM5700_B0		0x71000000
 #define BGE_ASICREV_BCM5700_B1		0x71020000
 #define BGE_ASICREV_BCM5700_B2		0x71030000
 #define BGE_ASICREV_BCM5700_ALTIMA	0x71040000
 #define BGE_ASICREV_BCM5700_C0		0x72000000
 
 /* PCI DMA Read/Write Control register */
 #define BGE_PCIDMARWCTL_MINDMA		0x000000FF
 #define BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
 #define BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x00004000
 #define BGE_PCIDMARWCTL_RD_WAT		0x00070000
 #define BGE_PCIDMARWCTL_WR_WAT		0x00380000
 #define BGE_PCIDMARWCTL_USE_MRM		0x00400000
 #define BGE_PCIDMARWCTL_ASRT_ALL_BE	0x00800000
 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD	0x0F000000
 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD	0xF0000000
 
 #define BGE_PCI_READ_BNDRY_DISABLE	0x00000000
 #define BGE_PCI_READ_BNDRY_16BYTES	0x00000100
 #define BGE_PCI_READ_BNDRY_32BYTES	0x00000200
 #define BGE_PCI_READ_BNDRY_64BYTES	0x00000300
 #define BGE_PCI_READ_BNDRY_128BYTES	0x00000400
 #define BGE_PCI_READ_BNDRY_256BYTES	0x00000500
 #define BGE_PCI_READ_BNDRY_512BYTES	0x00000600
 #define BGE_PCI_READ_BNDRY_1024BYTES	0x00000700
 
 #define BGE_PCI_WRITE_BNDRY_DISABLE	0x00000000
 #define BGE_PCI_WRITE_BNDRY_16BYTES	0x00000800
 #define BGE_PCI_WRITE_BNDRY_32BYTES	0x00001000
 #define BGE_PCI_WRITE_BNDRY_64BYTES	0x00001800
 #define BGE_PCI_WRITE_BNDRY_128BYTES	0x00002000
 #define BGE_PCI_WRITE_BNDRY_256BYTES	0x00002800
 #define BGE_PCI_WRITE_BNDRY_512BYTES	0x00003000
 #define BGE_PCI_WRITE_BNDRY_1024BYTES	0x00003800
 
 /*
  * PCI state register -- note, this register is read only
  * unless the PCISTATE_WR bit of the PCI Misc. Host Control
  * register is set.
  */
 #define BGE_PCISTATE_FORCE_RESET	0x00000001
 #define BGE_PCISTATE_INTR_STATE		0x00000002
 #define BGE_PCISTATE_PCI_BUSMODE	0x00000004 /* 1 = PCI, 0 = PCI-X */
 #define BGE_PCISTATE_PCI_BUSSPEED	0x00000008 /* 1 = 33/66, 0 = 66/133 */
 #define BGE_PCISTATE_32BIT_BUS		0x00000010 /* 1 = 32bit, 0 = 64bit */
 #define BGE_PCISTATE_WANT_EXPROM	0x00000020
 #define BGE_PCISTATE_EXPROM_RETRY	0x00000040
 #define BGE_PCISTATE_FLATVIEW_MODE	0x00000100
 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
 
 /*
  * PCI Clock Control register -- note, this register is read only
  * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
  * register is set.
  */
 #define BGE_PCICLOCKCTL_DETECTED_SPEED	0x0000000F
 #define BGE_PCICLOCKCTL_M66EN		0x00000080
 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE	0x00000200
 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS	0x00000400
 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS	0x00000800
 #define BGE_PCICLOCKCTL_ALTCLK		0x00001000
 #define BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000
 #define BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
 
 
 #ifndef PCIM_CMD_MWIEN
 #define PCIM_CMD_MWIEN			0x0010
 #endif
 
 /*
  * High priority mailbox registers
  * Each mailbox is 64-bits wide, though we only use the
  * lower 32 bits. To write a 64-bit value, write the upper 32 bits
  * first. The NIC will load the mailbox after the lower 32 bit word
  * has been updated.
  */
 #define BGE_MBX_IRQ0_HI			0x0200
 #define BGE_MBX_IRQ0_LO			0x0204
 #define BGE_MBX_IRQ1_HI			0x0208
 #define BGE_MBX_IRQ1_LO			0x020C
 #define BGE_MBX_IRQ2_HI			0x0210
 #define BGE_MBX_IRQ2_LO			0x0214
 #define BGE_MBX_IRQ3_HI			0x0218
 #define BGE_MBX_IRQ3_LO			0x021C
 #define BGE_MBX_GEN0_HI			0x0220
 #define BGE_MBX_GEN0_LO			0x0224
 #define BGE_MBX_GEN1_HI			0x0228
 #define BGE_MBX_GEN1_LO			0x022C
 #define BGE_MBX_GEN2_HI			0x0230
 #define BGE_MBX_GEN2_LO			0x0234
 #define BGE_MBX_GEN3_HI			0x0228
 #define BGE_MBX_GEN3_LO			0x022C
 #define BGE_MBX_GEN4_HI			0x0240
 #define BGE_MBX_GEN4_LO			0x0244
 #define BGE_MBX_GEN5_HI			0x0248
 #define BGE_MBX_GEN5_LO			0x024C
 #define BGE_MBX_GEN6_HI			0x0250
 #define BGE_MBX_GEN6_LO			0x0254
 #define BGE_MBX_GEN7_HI			0x0258
 #define BGE_MBX_GEN7_LO			0x025C
 #define BGE_MBX_RELOAD_STATS_HI		0x0260
 #define BGE_MBX_RELOAD_STATS_LO		0x0264
 #define BGE_MBX_RX_STD_PROD_HI		0x0268
 #define BGE_MBX_RX_STD_PROD_LO		0x026C
 #define BGE_MBX_RX_JUMBO_PROD_HI	0x0270
 #define BGE_MBX_RX_JUMBO_PROD_LO	0x0274
 #define BGE_MBX_RX_MINI_PROD_HI		0x0278
 #define BGE_MBX_RX_MINI_PROD_LO		0x027C
 #define BGE_MBX_RX_CONS0_HI		0x0280
 #define BGE_MBX_RX_CONS0_LO		0x0284
 #define BGE_MBX_RX_CONS1_HI		0x0288
 #define BGE_MBX_RX_CONS1_LO		0x028C
 #define BGE_MBX_RX_CONS2_HI		0x0290
 #define BGE_MBX_RX_CONS2_LO		0x0294
 #define BGE_MBX_RX_CONS3_HI		0x0298
 #define BGE_MBX_RX_CONS3_LO		0x029C
 #define BGE_MBX_RX_CONS4_HI		0x02A0
 #define BGE_MBX_RX_CONS4_LO		0x02A4
 #define BGE_MBX_RX_CONS5_HI		0x02A8
 #define BGE_MBX_RX_CONS5_LO		0x02AC
 #define BGE_MBX_RX_CONS6_HI		0x02B0
 #define BGE_MBX_RX_CONS6_LO		0x02B4
 #define BGE_MBX_RX_CONS7_HI		0x02B8
 #define BGE_MBX_RX_CONS7_LO		0x02BC
 #define BGE_MBX_RX_CONS8_HI		0x02C0
 #define BGE_MBX_RX_CONS8_LO		0x02C4
 #define BGE_MBX_RX_CONS9_HI		0x02C8
 #define BGE_MBX_RX_CONS9_LO		0x02CC
 #define BGE_MBX_RX_CONS10_HI		0x02D0
 #define BGE_MBX_RX_CONS10_LO		0x02D4
 #define BGE_MBX_RX_CONS11_HI		0x02D8
 #define BGE_MBX_RX_CONS11_LO		0x02DC
 #define BGE_MBX_RX_CONS12_HI		0x02E0
 #define BGE_MBX_RX_CONS12_LO		0x02E4
 #define BGE_MBX_RX_CONS13_HI		0x02E8
 #define BGE_MBX_RX_CONS13_LO		0x02EC
 #define BGE_MBX_RX_CONS14_HI		0x02F0
 #define BGE_MBX_RX_CONS14_LO		0x02F4
 #define BGE_MBX_RX_CONS15_HI		0x02F8
 #define BGE_MBX_RX_CONS15_LO		0x02FC
 #define BGE_MBX_TX_HOST_PROD0_HI	0x0300
 #define BGE_MBX_TX_HOST_PROD0_LO	0x0304
 #define BGE_MBX_TX_HOST_PROD1_HI	0x0308
 #define BGE_MBX_TX_HOST_PROD1_LO	0x030C
 #define BGE_MBX_TX_HOST_PROD2_HI	0x0310
 #define BGE_MBX_TX_HOST_PROD2_LO	0x0314
 #define BGE_MBX_TX_HOST_PROD3_HI	0x0318
 #define BGE_MBX_TX_HOST_PROD3_LO	0x031C
 #define BGE_MBX_TX_HOST_PROD4_HI	0x0320
 #define BGE_MBX_TX_HOST_PROD4_LO	0x0324
 #define BGE_MBX_TX_HOST_PROD5_HI	0x0328
 #define BGE_MBX_TX_HOST_PROD5_LO	0x032C
 #define BGE_MBX_TX_HOST_PROD6_HI	0x0330
 #define BGE_MBX_TX_HOST_PROD6_LO	0x0334
 #define BGE_MBX_TX_HOST_PROD7_HI	0x0338
 #define BGE_MBX_TX_HOST_PROD7_LO	0x033C
 #define BGE_MBX_TX_HOST_PROD8_HI	0x0340
 #define BGE_MBX_TX_HOST_PROD8_LO	0x0344
 #define BGE_MBX_TX_HOST_PROD9_HI	0x0348
 #define BGE_MBX_TX_HOST_PROD9_LO	0x034C
 #define BGE_MBX_TX_HOST_PROD10_HI	0x0350
 #define BGE_MBX_TX_HOST_PROD10_LO	0x0354
 #define BGE_MBX_TX_HOST_PROD11_HI	0x0358
 #define BGE_MBX_TX_HOST_PROD11_LO	0x035C
 #define BGE_MBX_TX_HOST_PROD12_HI	0x0360
 #define BGE_MBX_TX_HOST_PROD12_LO	0x0364
 #define BGE_MBX_TX_HOST_PROD13_HI	0x0368
 #define BGE_MBX_TX_HOST_PROD13_LO	0x036C
 #define BGE_MBX_TX_HOST_PROD14_HI	0x0370
 #define BGE_MBX_TX_HOST_PROD14_LO	0x0374
 #define BGE_MBX_TX_HOST_PROD15_HI	0x0378
 #define BGE_MBX_TX_HOST_PROD15_LO	0x037C
 #define BGE_MBX_TX_NIC_PROD0_HI		0x0380
 #define BGE_MBX_TX_NIC_PROD0_LO		0x0384
 #define BGE_MBX_TX_NIC_PROD1_HI		0x0388
 #define BGE_MBX_TX_NIC_PROD1_LO		0x038C
 #define BGE_MBX_TX_NIC_PROD2_HI		0x0390
 #define BGE_MBX_TX_NIC_PROD2_LO		0x0394
 #define BGE_MBX_TX_NIC_PROD3_HI		0x0398
 #define BGE_MBX_TX_NIC_PROD3_LO		0x039C
 #define BGE_MBX_TX_NIC_PROD4_HI		0x03A0
 #define BGE_MBX_TX_NIC_PROD4_LO		0x03A4
 #define BGE_MBX_TX_NIC_PROD5_HI		0x03A8
 #define BGE_MBX_TX_NIC_PROD5_LO		0x03AC
 #define BGE_MBX_TX_NIC_PROD6_HI		0x03B0
 #define BGE_MBX_TX_NIC_PROD6_LO		0x03B4
 #define BGE_MBX_TX_NIC_PROD7_HI		0x03B8
 #define BGE_MBX_TX_NIC_PROD7_LO		0x03BC
 #define BGE_MBX_TX_NIC_PROD8_HI		0x03C0
 #define BGE_MBX_TX_NIC_PROD8_LO		0x03C4
 #define BGE_MBX_TX_NIC_PROD9_HI		0x03C8
 #define BGE_MBX_TX_NIC_PROD9_LO		0x03CC
 #define BGE_MBX_TX_NIC_PROD10_HI	0x03D0
 #define BGE_MBX_TX_NIC_PROD10_LO	0x03D4
 #define BGE_MBX_TX_NIC_PROD11_HI	0x03D8
 #define BGE_MBX_TX_NIC_PROD11_LO	0x03DC
 #define BGE_MBX_TX_NIC_PROD12_HI	0x03E0
 #define BGE_MBX_TX_NIC_PROD12_LO	0x03E4
 #define BGE_MBX_TX_NIC_PROD13_HI	0x03E8
 #define BGE_MBX_TX_NIC_PROD13_LO	0x03EC
 #define BGE_MBX_TX_NIC_PROD14_HI	0x03F0
 #define BGE_MBX_TX_NIC_PROD14_LO	0x03F4
 #define BGE_MBX_TX_NIC_PROD15_HI	0x03F8
 #define BGE_MBX_TX_NIC_PROD15_LO	0x03FC
 
 #define BGE_TX_RINGS_MAX		4
 #define BGE_TX_RINGS_EXTSSRAM_MAX	16
 #define BGE_RX_RINGS_MAX		16
 
 /* Ethernet MAC control registers */
 #define BGE_MAC_MODE			0x0400
 #define BGE_MAC_STS			0x0404
 #define BGE_MAC_EVT_ENB			0x0408
 #define BGE_MAC_LED_CTL			0x040C
 #define BGE_MAC_ADDR1_LO		0x0410
 #define BGE_MAC_ADDR1_HI		0x0414
 #define BGE_MAC_ADDR2_LO		0x0418
 #define BGE_MAC_ADDR2_HI		0x041C
 #define BGE_MAC_ADDR3_LO		0x0420
 #define BGE_MAC_ADDR3_HI		0x0424
 #define BGE_MAC_ADDR4_LO		0x0428
 #define BGE_MAC_ADDR4_HI		0x042C
 #define BGE_WOL_PATPTR			0x0430
 #define BGE_WOL_PATCFG			0x0434
 #define BGE_TX_RANDOM_BACKOFF		0x0438
 #define BGE_RX_MTU			0x043C
 #define BGE_GBIT_PCS_TEST		0x0440
 #define BGE_TX_TBI_AUTONEG		0x0444
 #define BGE_RX_TBI_AUTONEG		0x0448
 #define BGE_MI_COMM			0x044C
 #define BGE_MI_STS			0x0450
 #define BGE_MI_MODE			0x0454
 #define BGE_AUTOPOLL_STS		0x0458
 #define BGE_TX_MODE			0x045C
 #define BGE_TX_STS			0x0460
 #define BGE_TX_LENGTHS			0x0464
 #define BGE_RX_MODE			0x0468
 #define BGE_RX_STS			0x046C
 #define BGE_MAR0			0x0470
 #define BGE_MAR1			0x0474
 #define BGE_MAR2			0x0478
 #define BGE_MAR3			0x047C
 #define BGE_RX_BD_RULES_CTL0		0x0480
 #define BGE_RX_BD_RULES_MASKVAL0	0x0484
 #define BGE_RX_BD_RULES_CTL1		0x0488
 #define BGE_RX_BD_RULES_MASKVAL1	0x048C
 #define BGE_RX_BD_RULES_CTL2		0x0490
 #define BGE_RX_BD_RULES_MASKVAL2	0x0494
 #define BGE_RX_BD_RULES_CTL3		0x0498
 #define BGE_RX_BD_RULES_MASKVAL3	0x049C
 #define BGE_RX_BD_RULES_CTL4		0x04A0
 #define BGE_RX_BD_RULES_MASKVAL4	0x04A4
 #define BGE_RX_BD_RULES_CTL5		0x04A8
 #define BGE_RX_BD_RULES_MASKVAL5	0x04AC
 #define BGE_RX_BD_RULES_CTL6		0x04B0
 #define BGE_RX_BD_RULES_MASKVAL6	0x04B4
 #define BGE_RX_BD_RULES_CTL7		0x04B8
 #define BGE_RX_BD_RULES_MASKVAL7	0x04BC
 #define BGE_RX_BD_RULES_CTL8		0x04C0
 #define BGE_RX_BD_RULES_MASKVAL8	0x04C4
 #define BGE_RX_BD_RULES_CTL9		0x04C8
 #define BGE_RX_BD_RULES_MASKVAL9	0x04CC
 #define BGE_RX_BD_RULES_CTL10		0x04D0
 #define BGE_RX_BD_RULES_MASKVAL10	0x04D4
 #define BGE_RX_BD_RULES_CTL11		0x04D8
 #define BGE_RX_BD_RULES_MASKVAL11	0x04DC
 #define BGE_RX_BD_RULES_CTL12		0x04E0
 #define BGE_RX_BD_RULES_MASKVAL12	0x04E4
 #define BGE_RX_BD_RULES_CTL13		0x04E8
 #define BGE_RX_BD_RULES_MASKVAL13	0x04EC
 #define BGE_RX_BD_RULES_CTL14		0x04F0
 #define BGE_RX_BD_RULES_MASKVAL14	0x04F4
 #define BGE_RX_BD_RULES_CTL15		0x04F8
 #define BGE_RX_BD_RULES_MASKVAL15	0x04FC
 #define BGE_RX_RULES_CFG		0x0500
 #define BGE_RX_STATS			0x0800
 #define BGE_TX_STATS			0x0880
 
 /* Ethernet MAC Mode register */
 #define BGE_MACMODE_RESET		0x00000001
 #define BGE_MACMODE_HALF_DUPLEX		0x00000002
 #define BGE_MACMODE_PORTMODE		0x0000000C
 #define BGE_MACMODE_LOOPBACK		0x00000010
 #define BGE_MACMODE_RX_TAGGEDPKT	0x00000080
 #define BGE_MACMODE_TX_BURST_ENB	0x00000100
 #define BGE_MACMODE_MAX_DEFER		0x00000200
 #define BGE_MACMODE_LINK_POLARITY	0x00000400
 #define BGE_MACMODE_RX_STATS_ENB	0x00000800
 #define BGE_MACMODE_RX_STATS_CLEAR	0x00001000
 #define BGE_MACMODE_RX_STATS_FLUSH	0x00002000
 #define BGE_MACMODE_TX_STATS_ENB	0x00004000
 #define BGE_MACMODE_TX_STATS_CLEAR	0x00008000
 #define BGE_MACMODE_TX_STATS_FLUSH	0x00010000
 #define BGE_MACMODE_TBI_SEND_CFGS	0x00020000
 #define BGE_MACMODE_MAGIC_PKT_ENB	0x00040000
 #define BGE_MACMODE_ACPI_PWRON_ENB	0x00080000
 #define BGE_MACMODE_MIP_ENB		0x00100000
 #define BGE_MACMODE_TXDMA_ENB		0x00200000
 #define BGE_MACMODE_RXDMA_ENB		0x00400000
 #define BGE_MACMODE_FRMHDR_DMA_ENB	0x00800000
 
 #define BGE_PORTMODE_NONE		0x00000000
 #define BGE_PORTMODE_MII		0x00000004
 #define BGE_PORTMODE_GMII		0x00000008
 #define BGE_PORTMODE_TBI		0x0000000C
 
 /* MAC Status register */
 #define BGE_MACSTAT_TBI_PCS_SYNCHED	0x00000001
 #define BGE_MACSTAT_TBI_SIGNAL_DETECT	0x00000002
 #define BGE_MACSTAT_RX_CFG		0x00000004
 #define BGE_MACSTAT_CFG_CHANGED		0x00000008
 #define BGE_MACSTAT_SYNC_CHANGED	0x00000010
 #define BGE_MACSTAT_PORT_DECODE_ERROR	0x00000400
 #define BGE_MACSTAT_LINK_CHANGED	0x00001000
 #define BGE_MACSTAT_MI_COMPLETE		0x00400000
 #define BGE_MACSTAT_MI_INTERRUPT	0x00800000
 #define BGE_MACSTAT_AUTOPOLL_ERROR	0x01000000
 #define BGE_MACSTAT_ODI_ERROR		0x02000000
 #define BGE_MACSTAT_RXSTAT_OFLOW	0x04000000
 #define BGE_MACSTAT_TXSTAT_OFLOW	0x08000000
 
 /* MAC Event Enable Register */
 #define BGE_EVTENB_PORT_DECODE_ERROR	0x00000400
 #define BGE_EVTENB_LINK_CHANGED		0x00001000
 #define BGE_EVTENB_MI_COMPLETE		0x00400000
 #define BGE_EVTENB_MI_INTERRUPT		0x00800000
 #define BGE_EVTENB_AUTOPOLL_ERROR	0x01000000
 #define BGE_EVTENB_ODI_ERROR		0x02000000
 #define BGE_EVTENB_RXSTAT_OFLOW		0x04000000
 #define BGE_EVTENB_TXSTAT_OFLOW		0x08000000
 
 /* LED Control Register */
 #define BGE_LEDCTL_LINKLED_OVERRIDE	0x00000001
 #define BGE_LEDCTL_1000MBPS_LED		0x00000002
 #define BGE_LEDCTL_100MBPS_LED		0x00000004
 #define BGE_LEDCTL_10MBPS_LED		0x00000008
 #define BGE_LEDCTL_TRAFLED_OVERRIDE	0x00000010
 #define BGE_LEDCTL_TRAFLED_BLINK	0x00000020
 #define BGE_LEDCTL_TREFLED_BLINK_2	0x00000040
 #define BGE_LEDCTL_1000MBPS_STS		0x00000080
 #define BGE_LEDCTL_100MBPS_STS		0x00000100
 #define BGE_LEDCTL_10MBPS_STS		0x00000200
 #define BGE_LEDCTL_TRADLED_STS		0x00000400
 #define BGE_LEDCTL_BLINKPERIOD		0x7FF80000
 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE	0x80000000
 
 /* TX backoff seed register */
 #define BGE_TX_BACKOFF_SEED_MASK	0x3F
 
 /* Autopoll status register */
 #define BGE_AUTOPOLLSTS_ERROR		0x00000001
 
 /* Transmit MAC mode register */
 #define BGE_TXMODE_RESET		0x00000001
 #define BGE_TXMODE_ENABLE		0x00000002
 #define BGE_TXMODE_FLOWCTL_ENABLE	0x00000010
 #define BGE_TXMODE_BIGBACKOFF_ENABLE	0x00000020
 #define BGE_TXMODE_LONGPAUSE_ENABLE	0x00000040
 
 /* Transmit MAC status register */
 #define BGE_TXSTAT_RX_XOFFED		0x00000001
 #define BGE_TXSTAT_SENT_XOFF		0x00000002
 #define BGE_TXSTAT_SENT_XON		0x00000004
 #define BGE_TXSTAT_LINK_UP		0x00000008
 #define BGE_TXSTAT_ODI_UFLOW		0x00000010
 #define BGE_TXSTAT_ODI_OFLOW		0x00000020
 
 /* Transmit MAC lengths register */
 #define BGE_TXLEN_SLOTTIME		0x000000FF
 #define BGE_TXLEN_IPG			0x00000F00
 #define BGE_TXLEN_CRS			0x00003000
 
 /* Receive MAC mode register */
 #define BGE_RXMODE_RESET		0x00000001
 #define BGE_RXMODE_ENABLE		0x00000002
 #define BGE_RXMODE_FLOWCTL_ENABLE	0x00000004
 #define BGE_RXMODE_RX_GIANTS		0x00000020
 #define BGE_RXMODE_RX_RUNTS		0x00000040
 #define BGE_RXMODE_8022_LENCHECK	0x00000080
 #define BGE_RXMODE_RX_PROMISC		0x00000100
 #define BGE_RXMODE_RX_NO_CRC_CHECK	0x00000200
 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG	0x00000400
 
 /* Receive MAC status register */
 #define BGE_RXSTAT_REMOTE_XOFFED	0x00000001
 #define BGE_RXSTAT_RCVD_XOFF		0x00000002
 #define BGE_RXSTAT_RCVD_XON		0x00000004
 
 /* Receive Rules Control register */
 #define BGE_RXRULECTL_OFFSET		0x000000FF
 #define BGE_RXRULECTL_CLASS		0x00001F00
 #define BGE_RXRULECTL_HDRTYPE		0x0000E000
 #define BGE_RXRULECTL_COMPARE_OP	0x00030000
 #define BGE_RXRULECTL_MAP		0x01000000
 #define BGE_RXRULECTL_DISCARD		0x02000000
 #define BGE_RXRULECTL_MASK		0x04000000
 #define BGE_RXRULECTL_ACTIVATE_PROC3	0x08000000
 #define BGE_RXRULECTL_ACTIVATE_PROC2	0x10000000
 #define BGE_RXRULECTL_ACTIVATE_PROC1	0x20000000
 #define BGE_RXRULECTL_ANDWITHNEXT	0x40000000
 
 /* Receive Rules Mask register */
 #define BGE_RXRULEMASK_VALUE		0x0000FFFF
 #define BGE_RXRULEMASK_MASKVAL		0xFFFF0000
 
 /* MI communication register */
 #define BGE_MICOMM_DATA			0x0000FFFF
 #define BGE_MICOMM_REG			0x001F0000
 #define BGE_MICOMM_PHY			0x03E00000
 #define BGE_MICOMM_CMD			0x0C000000
 #define BGE_MICOMM_READFAIL		0x10000000
 #define BGE_MICOMM_BUSY			0x20000000
 
 #define BGE_MIREG(x)	((x & 0x1F) << 16)
 #define BGE_MIPHY(x)	((x & 0x1F) << 21)
 #define BGE_MICMD_WRITE			0x04000000
 #define BGE_MICMD_READ			0x08000000
 
 /* MI status register */
 #define BGE_MISTS_LINK			0x00000001
 #define BGE_MISTS_10MBPS		0x00000002
 
 #define BGE_MIMODE_SHORTPREAMBLE	0x00000002
 #define BGE_MIMODE_AUTOPOLL		0x00000010
 #define BGE_MIMODE_CLKCNT		0x001F0000
 
 
 /*
  * Send data initiator control registers.
  */
 #define BGE_SDI_MODE			0x0C00
 #define BGE_SDI_STATUS			0x0C04
 #define BGE_SDI_STATS_CTL		0x0C08
 #define BGE_SDI_STATS_ENABLE_MASK	0x0C0C
 #define BGE_SDI_STATS_INCREMENT_MASK	0x0C10
 #define BGE_LOCSTATS_COS0		0x0C80
 #define BGE_LOCSTATS_COS1		0x0C84
 #define BGE_LOCSTATS_COS2		0x0C88
 #define BGE_LOCSTATS_COS3		0x0C8C
 #define BGE_LOCSTATS_COS4		0x0C90
 #define BGE_LOCSTATS_COS5		0x0C84
 #define BGE_LOCSTATS_COS6		0x0C98
 #define BGE_LOCSTATS_COS7		0x0C9C
 #define BGE_LOCSTATS_COS8		0x0CA0
 #define BGE_LOCSTATS_COS9		0x0CA4
 #define BGE_LOCSTATS_COS10		0x0CA8
 #define BGE_LOCSTATS_COS11		0x0CAC
 #define BGE_LOCSTATS_COS12		0x0CB0
 #define BGE_LOCSTATS_COS13		0x0CB4
 #define BGE_LOCSTATS_COS14		0x0CB8
 #define BGE_LOCSTATS_COS15		0x0CBC
 #define BGE_LOCSTATS_DMA_RQ_FULL	0x0CC0
 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL	0x0CC4
 #define BGE_LOCSTATS_SDC_QUEUE_FULL	0x0CC8
 #define BGE_LOCSTATS_NIC_SENDPROD_SET	0x0CCC
 #define BGE_LOCSTATS_STATS_UPDATED	0x0CD0
 #define BGE_LOCSTATS_IRQS		0x0CD4
 #define BGE_LOCSTATS_AVOIDED_IRQS	0x0CD8
 #define BGE_LOCSTATS_TX_THRESH_HIT	0x0CDC
 
 /* Send Data Initiator mode register */
 #define BGE_SDIMODE_RESET		0x00000001
 #define BGE_SDIMODE_ENABLE		0x00000002
 #define BGE_SDIMODE_STATS_OFLOW_ATTN	0x00000004
 
 /* Send Data Initiator stats register */
 #define BGE_SDISTAT_STATS_OFLOW_ATTN	0x00000004
 
 /* Send Data Initiator stats control register */
 #define BGE_SDISTATSCTL_ENABLE		0x00000001
 #define BGE_SDISTATSCTL_FASTER		0x00000002
 #define BGE_SDISTATSCTL_CLEAR		0x00000004
 #define BGE_SDISTATSCTL_FORCEFLUSH	0x00000008
 #define BGE_SDISTATSCTL_FORCEZERO	0x00000010
 
 /*
  * Send Data Completion Control registers
  */
 #define BGE_SDC_MODE			0x1000
 #define BGE_SDC_STATUS			0x1004
 
 /* Send Data completion mode register */
 #define BGE_SDCMODE_RESET		0x00000001
 #define BGE_SDCMODE_ENABLE		0x00000002
 #define BGE_SDCMODE_ATTN		0x00000004
 
 /* Send Data completion status register */
 #define BGE_SDCSTAT_ATTN		0x00000004
 
 /*
  * Send BD Ring Selector Control registers
  */
 #define BGE_SRS_MODE			0x1400
 #define BGE_SRS_STATUS			0x1404
 #define BGE_SRS_HWDIAG			0x1408
 #define BGE_SRS_LOC_NIC_CONS0		0x1440
 #define BGE_SRS_LOC_NIC_CONS1		0x1444
 #define BGE_SRS_LOC_NIC_CONS2		0x1448
 #define BGE_SRS_LOC_NIC_CONS3		0x144C
 #define BGE_SRS_LOC_NIC_CONS4		0x1450
 #define BGE_SRS_LOC_NIC_CONS5		0x1454
 #define BGE_SRS_LOC_NIC_CONS6		0x1458
 #define BGE_SRS_LOC_NIC_CONS7		0x145C
 #define BGE_SRS_LOC_NIC_CONS8		0x1460
 #define BGE_SRS_LOC_NIC_CONS9		0x1464
 #define BGE_SRS_LOC_NIC_CONS10		0x1468
 #define BGE_SRS_LOC_NIC_CONS11		0x146C
 #define BGE_SRS_LOC_NIC_CONS12		0x1470
 #define BGE_SRS_LOC_NIC_CONS13		0x1474
 #define BGE_SRS_LOC_NIC_CONS14		0x1478
 #define BGE_SRS_LOC_NIC_CONS15		0x147C
 
 /* Send BD Ring Selector Mode register */
 #define BGE_SRSMODE_RESET		0x00000001
 #define BGE_SRSMODE_ENABLE		0x00000002
 #define BGE_SRSMODE_ATTN		0x00000004
 
 /* Send BD Ring Selector Status register */
 #define BGE_SRSSTAT_ERROR		0x00000004
 
 /* Send BD Ring Selector HW Diagnostics register */
 #define BGE_SRSHWDIAG_STATE		0x0000000F
 #define BGE_SRSHWDIAG_CURRINGNUM	0x000000F0
 #define BGE_SRSHWDIAG_STAGEDRINGNUM	0x00000F00
 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX	0x0000F000
 
 /*
  * Send BD Initiator Selector Control registers
  */
 #define BGE_SBDI_MODE			0x1800
 #define BGE_SBDI_STATUS			0x1804
 #define BGE_SBDI_LOC_NIC_PROD0		0x1808
 #define BGE_SBDI_LOC_NIC_PROD1		0x180C
 #define BGE_SBDI_LOC_NIC_PROD2		0x1810
 #define BGE_SBDI_LOC_NIC_PROD3		0x1814
 #define BGE_SBDI_LOC_NIC_PROD4		0x1818
 #define BGE_SBDI_LOC_NIC_PROD5		0x181C
 #define BGE_SBDI_LOC_NIC_PROD6		0x1820
 #define BGE_SBDI_LOC_NIC_PROD7		0x1824
 #define BGE_SBDI_LOC_NIC_PROD8		0x1828
 #define BGE_SBDI_LOC_NIC_PROD9		0x182C
 #define BGE_SBDI_LOC_NIC_PROD10		0x1830
 #define BGE_SBDI_LOC_NIC_PROD11		0x1834
 #define BGE_SBDI_LOC_NIC_PROD12		0x1838
 #define BGE_SBDI_LOC_NIC_PROD13		0x183C
 #define BGE_SBDI_LOC_NIC_PROD14		0x1840
 #define BGE_SBDI_LOC_NIC_PROD15		0x1844
 
 /* Send BD Initiator Mode register */
 #define BGE_SBDIMODE_RESET		0x00000001
 #define BGE_SBDIMODE_ENABLE		0x00000002
 #define BGE_SBDIMODE_ATTN		0x00000004
 
 /* Send BD Initiator Status register */
 #define BGE_SBDISTAT_ERROR		0x00000004
 
 /*
  * Send BD Completion Control registers
  */
 #define BGE_SBDC_MODE			0x1C00
 #define BGE_SBDC_STATUS			0x1C04
 
 /* Send BD Completion Control Mode register */
 #define BGE_SBDCMODE_RESET		0x00000001
 #define BGE_SBDCMODE_ENABLE		0x00000002
 #define BGE_SBDCMODE_ATTN		0x00000004
 
 /* Send BD Completion Control Status register */
 #define BGE_SBDCSTAT_ATTN		0x00000004
 
 /*
  * Receive List Placement Control registers
  */
 #define BGE_RXLP_MODE			0x2000
 #define BGE_RXLP_STATUS			0x2004
 #define BGE_RXLP_SEL_LIST_LOCK		0x2008
 #define BGE_RXLP_SEL_NON_EMPTY_BITS	0x200C
 #define BGE_RXLP_CFG			0x2010
 #define BGE_RXLP_STATS_CTL		0x2014
 #define BGE_RXLP_STATS_ENABLE_MASK	0x2018
 #define BGE_RXLP_STATS_INCREMENT_MASK	0x201C
 #define BGE_RXLP_HEAD0			0x2100
 #define BGE_RXLP_TAIL0			0x2104
 #define BGE_RXLP_COUNT0			0x2108
 #define BGE_RXLP_HEAD1			0x2110
 #define BGE_RXLP_TAIL1			0x2114
 #define BGE_RXLP_COUNT1			0x2118
 #define BGE_RXLP_HEAD2			0x2120
 #define BGE_RXLP_TAIL2			0x2124
 #define BGE_RXLP_COUNT2			0x2128
 #define BGE_RXLP_HEAD3			0x2130
 #define BGE_RXLP_TAIL3			0x2134
 #define BGE_RXLP_COUNT3			0x2138
 #define BGE_RXLP_HEAD4			0x2140
 #define BGE_RXLP_TAIL4			0x2144
 #define BGE_RXLP_COUNT4			0x2148
 #define BGE_RXLP_HEAD5			0x2150
 #define BGE_RXLP_TAIL5			0x2154
 #define BGE_RXLP_COUNT5			0x2158
 #define BGE_RXLP_HEAD6			0x2160
 #define BGE_RXLP_TAIL6			0x2164
 #define BGE_RXLP_COUNT6			0x2168
 #define BGE_RXLP_HEAD7			0x2170
 #define BGE_RXLP_TAIL7			0x2174
 #define BGE_RXLP_COUNT7			0x2178
 #define BGE_RXLP_HEAD8			0x2180
 #define BGE_RXLP_TAIL8			0x2184
 #define BGE_RXLP_COUNT8			0x2188
 #define BGE_RXLP_HEAD9			0x2190
 #define BGE_RXLP_TAIL9			0x2194
 #define BGE_RXLP_COUNT9			0x2198
 #define BGE_RXLP_HEAD10			0x21A0
 #define BGE_RXLP_TAIL10			0x21A4
 #define BGE_RXLP_COUNT10		0x21A8
 #define BGE_RXLP_HEAD11			0x21B0
 #define BGE_RXLP_TAIL11			0x21B4
 #define BGE_RXLP_COUNT11		0x21B8
 #define BGE_RXLP_HEAD12			0x21C0
 #define BGE_RXLP_TAIL12			0x21C4
 #define BGE_RXLP_COUNT12		0x21C8
 #define BGE_RXLP_HEAD13			0x21D0
 #define BGE_RXLP_TAIL13			0x21D4
 #define BGE_RXLP_COUNT13		0x21D8
 #define BGE_RXLP_HEAD14			0x21E0
 #define BGE_RXLP_TAIL14			0x21E4
 #define BGE_RXLP_COUNT14		0x21E8
 #define BGE_RXLP_HEAD15			0x21F0
 #define BGE_RXLP_TAIL15			0x21F4
 #define BGE_RXLP_COUNT15		0x21F8
 #define BGE_RXLP_LOCSTAT_COS0		0x2200
 #define BGE_RXLP_LOCSTAT_COS1		0x2204
 #define BGE_RXLP_LOCSTAT_COS2		0x2208
 #define BGE_RXLP_LOCSTAT_COS3		0x220C
 #define BGE_RXLP_LOCSTAT_COS4		0x2210
 #define BGE_RXLP_LOCSTAT_COS5		0x2214
 #define BGE_RXLP_LOCSTAT_COS6		0x2218
 #define BGE_RXLP_LOCSTAT_COS7		0x221C
 #define BGE_RXLP_LOCSTAT_COS8		0x2220
 #define BGE_RXLP_LOCSTAT_COS9		0x2224
 #define BGE_RXLP_LOCSTAT_COS10		0x2228
 #define BGE_RXLP_LOCSTAT_COS11		0x222C
 #define BGE_RXLP_LOCSTAT_COS12		0x2230
 #define BGE_RXLP_LOCSTAT_COS13		0x2234
 #define BGE_RXLP_LOCSTAT_COS14		0x2238
 #define BGE_RXLP_LOCSTAT_COS15		0x223C
 #define BGE_RXLP_LOCSTAT_FILTDROP	0x2240
 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL	0x2244
 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL	0x2248
 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS	0x224C
 #define BGE_RXLP_LOCSTAT_IFIN_DROPS	0x2250
 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS	0x2254
 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT	0x2258
 
 
 /* Receive List Placement mode register */
 #define BGE_RXLPMODE_RESET		0x00000001
 #define BGE_RXLPMODE_ENABLE		0x00000002
 #define BGE_RXLPMODE_CLASS0_ATTN	0x00000004
 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN	0x00000008
 #define BGE_RXLPMODE_STATSOFLOW_ATTN	0x00000010
 
 /* Receive List Placement Status register */
 #define BGE_RXLPSTAT_CLASS0_ATTN	0x00000004
 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN	0x00000008
 #define BGE_RXLPSTAT_STATSOFLOW_ATTN	0x00000010
 
 /*
  * Receive Data and Receive BD Initiator Control Registers
  */
 #define BGE_RDBDI_MODE			0x2400
 #define BGE_RDBDI_STATUS		0x2404
 #define BGE_RX_JUMBO_RCB_HADDR_HI	0x2440
 #define BGE_RX_JUMBO_RCB_HADDR_LO	0x2444
 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS	0x2448
 #define BGE_RX_JUMBO_RCB_NICADDR	0x244C
 #define BGE_RX_STD_RCB_HADDR_HI		0x2450
 #define BGE_RX_STD_RCB_HADDR_LO		0x2454
 #define BGE_RX_STD_RCB_MAXLEN_FLAGS	0x2458
 #define BGE_RX_STD_RCB_NICADDR		0x245C
 #define BGE_RX_MINI_RCB_HADDR_HI	0x2460
 #define BGE_RX_MINI_RCB_HADDR_LO	0x2464
 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS	0x2468
 #define BGE_RX_MINI_RCB_NICADDR		0x246C
 #define BGE_RDBDI_JUMBO_RX_CONS		0x2470
 #define BGE_RDBDI_STD_RX_CONS		0x2474
 #define BGE_RDBDI_MINI_RX_CONS		0x2478
 #define BGE_RDBDI_RETURN_PROD0		0x2480
 #define BGE_RDBDI_RETURN_PROD1		0x2484
 #define BGE_RDBDI_RETURN_PROD2		0x2488
 #define BGE_RDBDI_RETURN_PROD3		0x248C
 #define BGE_RDBDI_RETURN_PROD4		0x2490
 #define BGE_RDBDI_RETURN_PROD5		0x2494
 #define BGE_RDBDI_RETURN_PROD6		0x2498
 #define BGE_RDBDI_RETURN_PROD7		0x249C
 #define BGE_RDBDI_RETURN_PROD8		0x24A0
 #define BGE_RDBDI_RETURN_PROD9		0x24A4
 #define BGE_RDBDI_RETURN_PROD10		0x24A8
 #define BGE_RDBDI_RETURN_PROD11		0x24AC
 #define BGE_RDBDI_RETURN_PROD12		0x24B0
 #define BGE_RDBDI_RETURN_PROD13		0x24B4
 #define BGE_RDBDI_RETURN_PROD14		0x24B8
 #define BGE_RDBDI_RETURN_PROD15		0x24BC
 #define BGE_RDBDI_HWDIAG		0x24C0
 
 
 /* Receive Data and Receive BD Initiator Mode register */
 #define BGE_RDBDIMODE_RESET		0x00000001
 #define BGE_RDBDIMODE_ENABLE		0x00000002
 #define BGE_RDBDIMODE_JUMBO_ATTN	0x00000004
 #define BGE_RDBDIMODE_GIANT_ATTN	0x00000008
 #define BGE_RDBDIMODE_BADRINGSZ_ATTN	0x00000010
 
 /* Receive Data and Receive BD Initiator Status register */
 #define BGE_RDBDISTAT_JUMBO_ATTN	0x00000004
 #define BGE_RDBDISTAT_GIANT_ATTN	0x00000008
 #define BGE_RDBDISTAT_BADRINGSZ_ATTN	0x00000010
 
 
 /*
  * Receive Data Completion Control registers
  */
 #define BGE_RDC_MODE			0x2800
 
 /* Receive Data Completion Mode register */
 #define BGE_RDCMODE_RESET		0x00000001
 #define BGE_RDCMODE_ENABLE		0x00000002
 #define BGE_RDCMODE_ATTN		0x00000004
 
 /*
  * Receive BD Initiator Control registers
  */
 #define BGE_RBDI_MODE			0x2C00
 #define BGE_RBDI_STATUS			0x2C04
 #define BGE_RBDI_NIC_JUMBO_BD_PROD	0x2C08
 #define BGE_RBDI_NIC_STD_BD_PROD	0x2C0C
 #define BGE_RBDI_NIC_MINI_BD_PROD	0x2C10
 #define BGE_RBDI_MINI_REPL_THRESH	0x2C14
 #define BGE_RBDI_STD_REPL_THRESH	0x2C18
 #define BGE_RBDI_JUMBO_REPL_THRESH	0x2C1C
 
 /* Receive BD Initiator Mode register */
 #define BGE_RBDIMODE_RESET		0x00000001
 #define BGE_RBDIMODE_ENABLE		0x00000002
 #define BGE_RBDIMODE_ATTN		0x00000004
 
 /* Receive BD Initiator Status register */
 #define BGE_RBDISTAT_ATTN		0x00000004
 
 /*
  * Receive BD Completion Control registers
  */
 #define BGE_RBDC_MODE			0x3000
 #define BGE_RBDC_STATUS			0x3004
 #define BGE_RBDC_JUMBO_BD_PROD		0x3008
 #define BGE_RBDC_STD_BD_PROD		0x300C
 #define BGE_RBDC_MINI_BD_PROD		0x3010
 
 /* Receive BD completion mode register */
 #define BGE_RBDCMODE_RESET		0x00000001
 #define BGE_RBDCMODE_ENABLE		0x00000002
 #define BGE_RBDCMODE_ATTN		0x00000004
 
 /* Receive BD completion status register */
 #define BGE_RBDCSTAT_ERROR		0x00000004
 
 /*
  * Receive List Selector Control registers
  */
 #define BGE_RXLS_MODE			0x3400
 #define BGE_RXLS_STATUS			0x3404
 
 /* Receive List Selector Mode register */
 #define BGE_RXLSMODE_RESET		0x00000001
 #define BGE_RXLSMODE_ENABLE		0x00000002
 #define BGE_RXLSMODE_ATTN		0x00000004
 
 /* Receive List Selector Status register */
 #define BGE_RXLSSTAT_ERROR		0x00000004
 
 /*
  * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
  */
 #define BGE_MBCF_MODE			0x3800
 #define BGE_MBCF_STATUS			0x3804
 
 /* Mbuf Cluster Free mode register */
 #define BGE_MBCFMODE_RESET		0x00000001
 #define BGE_MBCFMODE_ENABLE		0x00000002
 #define BGE_MBCFMODE_ATTN		0x00000004
 
 /* Mbuf Cluster Free status register */
 #define BGE_MBCFSTAT_ERROR		0x00000004
 
 /*
  * Host Coalescing Control registers
  */
 #define BGE_HCC_MODE			0x3C00
 #define BGE_HCC_STATUS			0x3C04
 #define BGE_HCC_RX_COAL_TICKS		0x3C08
 #define BGE_HCC_TX_COAL_TICKS		0x3C0C
 #define BGE_HCC_RX_MAX_COAL_BDS		0x3C10
 #define BGE_HCC_TX_MAX_COAL_BDS		0x3C14
 #define BGE_HCC_RX_COAL_TICKS_INT	0x3C18 /* ticks during interrupt */
 #define BGE_HCC_TX_COAL_TICKS_INT	0x3C1C /* ticks during interrupt */
 #define BGE_HCC_RX_MAX_COAL_BDS_INT	0x3C20 /* BDs during interrupt */
 #define BGE_HCC_TX_MAX_COAL_BDS_INT	0x3C34 /* BDs during interrupt */
 #define BGE_HCC_STATS_TICKS		0x3C28
 #define BGE_HCC_STATS_ADDR_HI		0x3C30
 #define BGE_HCC_STATS_ADDR_LO		0x3C34
 #define BGE_HCC_STATUSBLK_ADDR_HI	0x3C38
 #define BGE_HCC_STATUSBLK_ADDR_LO	0x3C3C
 #define BGE_HCC_STATS_BASEADDR		0x3C40 /* address in NIC memory */
 #define BGE_HCC_STATUSBLK_BASEADDR	0x3C44 /* address in NIC memory */
 #define BGE_FLOW_ATTN			0x3C48
 #define BGE_HCC_JUMBO_BD_CONS		0x3C50
 #define BGE_HCC_STD_BD_CONS		0x3C54
 #define BGE_HCC_MINI_BD_CONS		0x3C58
 #define BGE_HCC_RX_RETURN_PROD0		0x3C80
 #define BGE_HCC_RX_RETURN_PROD1		0x3C84
 #define BGE_HCC_RX_RETURN_PROD2		0x3C88
 #define BGE_HCC_RX_RETURN_PROD3		0x3C8C
 #define BGE_HCC_RX_RETURN_PROD4		0x3C90
 #define BGE_HCC_RX_RETURN_PROD5		0x3C94
 #define BGE_HCC_RX_RETURN_PROD6		0x3C98
 #define BGE_HCC_RX_RETURN_PROD7		0x3C9C
 #define BGE_HCC_RX_RETURN_PROD8		0x3CA0
 #define BGE_HCC_RX_RETURN_PROD9		0x3CA4
 #define BGE_HCC_RX_RETURN_PROD10	0x3CA8
 #define BGE_HCC_RX_RETURN_PROD11	0x3CAC
 #define BGE_HCC_RX_RETURN_PROD12	0x3CB0
 #define BGE_HCC_RX_RETURN_PROD13	0x3CB4
 #define BGE_HCC_RX_RETURN_PROD14	0x3CB8
 #define BGE_HCC_RX_RETURN_PROD15	0x3CBC
 #define BGE_HCC_TX_BD_CONS0		0x3CC0
 #define BGE_HCC_TX_BD_CONS1		0x3CC4
 #define BGE_HCC_TX_BD_CONS2		0x3CC8
 #define BGE_HCC_TX_BD_CONS3		0x3CCC
 #define BGE_HCC_TX_BD_CONS4		0x3CD0
 #define BGE_HCC_TX_BD_CONS5		0x3CD4
 #define BGE_HCC_TX_BD_CONS6		0x3CD8
 #define BGE_HCC_TX_BD_CONS7		0x3CDC
 #define BGE_HCC_TX_BD_CONS8		0x3CE0
 #define BGE_HCC_TX_BD_CONS9		0x3CE4
 #define BGE_HCC_TX_BD_CONS10		0x3CE8
 #define BGE_HCC_TX_BD_CONS11		0x3CEC
 #define BGE_HCC_TX_BD_CONS12		0x3CF0
 #define BGE_HCC_TX_BD_CONS13		0x3CF4
 #define BGE_HCC_TX_BD_CONS14		0x3CF8
 #define BGE_HCC_TX_BD_CONS15		0x3CFC
 
 
 /* Host coalescing mode register */
 #define BGE_HCCMODE_RESET		0x00000001
 #define BGE_HCCMODE_ENABLE		0x00000002
 #define BGE_HCCMODE_ATTN		0x00000004
 #define BGE_HCCMODE_COAL_NOW		0x00000008
 #define BGE_HCCMODE_MSI_BITS		0x0x000070
 #define BGE_HCCMODE_STATBLK_SIZE	0x00000180
 
 #define BGE_STATBLKSZ_FULL		0x00000000
 #define BGE_STATBLKSZ_64BYTE		0x00000080
 #define BGE_STATBLKSZ_32BYTE		0x00000100
 
 /* Host coalescing status register */
 #define BGE_HCCSTAT_ERROR		0x00000004
 
 /* Flow attention register */
 #define BGE_FLOWATTN_MB_LOWAT		0x00000040
 #define BGE_FLOWATTN_MEMARB		0x00000080
 #define BGE_FLOWATTN_HOSTCOAL		0x00008000
 #define BGE_FLOWATTN_DMADONE_DISCARD	0x00010000
 #define BGE_FLOWATTN_RCB_INVAL		0x00020000
 #define BGE_FLOWATTN_RXDATA_CORRUPT	0x00040000
 #define BGE_FLOWATTN_RDBDI		0x00080000
 #define BGE_FLOWATTN_RXLS		0x00100000
 #define BGE_FLOWATTN_RXLP		0x00200000
 #define BGE_FLOWATTN_RBDC		0x00400000
 #define BGE_FLOWATTN_RBDI		0x00800000
 #define BGE_FLOWATTN_SDC		0x08000000
 #define BGE_FLOWATTN_SDI		0x10000000
 #define BGE_FLOWATTN_SRS		0x20000000
 #define BGE_FLOWATTN_SBDC		0x40000000
 #define BGE_FLOWATTN_SBDI		0x80000000
 
 /*
  * Memory arbiter registers
  */
 #define BGE_MARB_MODE			0x4000
 #define BGE_MARB_STATUS			0x4004
 #define BGE_MARB_TRAPADDR_HI		0x4008
 #define BGE_MARB_TRAPADDR_LO		0x400C
 
 /* Memory arbiter mode register */
 #define BGE_MARBMODE_RESET		0x00000001
 #define BGE_MARBMODE_ENABLE		0x00000002
 #define BGE_MARBMODE_TX_ADDR_TRAP	0x00000004
 #define BGE_MARBMODE_RX_ADDR_TRAP	0x00000008
 #define BGE_MARBMODE_DMAW1_TRAP		0x00000010
 #define BGE_MARBMODE_DMAR1_TRAP		0x00000020
 #define BGE_MARBMODE_RXRISC_TRAP	0x00000040
 #define BGE_MARBMODE_TXRISC_TRAP	0x00000080
 #define BGE_MARBMODE_PCI_TRAP		0x00000100
 #define BGE_MARBMODE_DMAR2_TRAP		0x00000200
 #define BGE_MARBMODE_RXQ_TRAP		0x00000400
 #define BGE_MARBMODE_RXDI1_TRAP		0x00000800
 #define BGE_MARBMODE_RXDI2_TRAP		0x00001000
 #define BGE_MARBMODE_DC_GRPMEM_TRAP	0x00002000
 #define BGE_MARBMODE_HCOAL_TRAP		0x00004000
 #define BGE_MARBMODE_MBUF_TRAP		0x00008000
 #define BGE_MARBMODE_TXDI_TRAP		0x00010000
 #define BGE_MARBMODE_SDC_DMAC_TRAP	0x00020000
 #define BGE_MARBMODE_TXBD_TRAP		0x00040000
 #define BGE_MARBMODE_BUFFMAN_TRAP	0x00080000
 #define BGE_MARBMODE_DMAW2_TRAP		0x00100000
 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP	0x00200000
 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP	0x00800000
 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP	0x01000000
 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP	0x02000000
 
 /* Memory arbiter status register */
 #define BGE_MARBSTAT_TX_ADDR_TRAP	0x00000004
 #define BGE_MARBSTAT_RX_ADDR_TRAP	0x00000008
 #define BGE_MARBSTAT_DMAW1_TRAP		0x00000010
 #define BGE_MARBSTAT_DMAR1_TRAP		0x00000020
 #define BGE_MARBSTAT_RXRISC_TRAP	0x00000040
 #define BGE_MARBSTAT_TXRISC_TRAP	0x00000080
 #define BGE_MARBSTAT_PCI_TRAP		0x00000100
 #define BGE_MARBSTAT_DMAR2_TRAP		0x00000200
 #define BGE_MARBSTAT_RXQ_TRAP		0x00000400
 #define BGE_MARBSTAT_RXDI1_TRAP		0x00000800
 #define BGE_MARBSTAT_RXDI2_TRAP		0x00001000
 #define BGE_MARBSTAT_DC_GRPMEM_TRAP	0x00002000
 #define BGE_MARBSTAT_HCOAL_TRAP		0x00004000
 #define BGE_MARBSTAT_MBUF_TRAP		0x00008000
 #define BGE_MARBSTAT_TXDI_TRAP		0x00010000
 #define BGE_MARBSTAT_SDC_DMAC_TRAP	0x00020000
 #define BGE_MARBSTAT_TXBD_TRAP		0x00040000
 #define BGE_MARBSTAT_BUFFMAN_TRAP	0x00080000
 #define BGE_MARBSTAT_DMAW2_TRAP		0x00100000
 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP	0x00200000
 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP	0x00800000
 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP	0x01000000
 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP	0x02000000
 
 /*
  * Buffer manager control registers
  */
 #define BGE_BMAN_MODE			0x4400
 #define BGE_BMAN_STATUS			0x4404
 #define BGE_BMAN_MBUFPOOL_BASEADDR	0x4408
 #define BGE_BMAN_MBUFPOOL_LEN		0x440C
 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT	0x4410
 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT	0x4414
 #define BGE_BMAN_MBUFPOOL_HIWAT		0x4418
 #define BGE_BMAN_RXCPU_MBALLOC_REQ	0x441C
 #define BGE_BMAN_RXCPU_MBALLOC_RESP	0x4420
 #define BGE_BMAN_TXCPU_MBALLOC_REQ	0x4424
 #define BGE_BMAN_TXCPU_MBALLOC_RESP	0x4428
 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR	0x442C
 #define BGE_BMAN_DMA_DESCPOOL_LEN	0x4430
 #define BGE_BMAN_DMA_DESCPOOL_LOWAT	0x4434
 #define BGE_BMAN_DMA_DESCPOOL_HIWAT	0x4438
 #define BGE_BMAN_RXCPU_DMAALLOC_REQ	0x443C
 #define BGE_BMAN_RXCPU_DMAALLOC_RESP	0x4440
 #define BGE_BMAN_TXCPU_DMAALLOC_REQ	0x4444
 #define BGE_BMAN_TXCPU_DMALLLOC_RESP	0x4448
 #define BGE_BMAN_HWDIAG_1		0x444C
 #define BGE_BMAN_HWDIAG_2		0x4450
 #define BGE_BMAN_HWDIAG_3		0x4454
 
 /* Buffer manager mode register */
 #define BGE_BMANMODE_RESET		0x00000001
 #define BGE_BMANMODE_ENABLE		0x00000002
 #define BGE_BMANMODE_ATTN		0x00000004
 #define BGE_BMANMODE_TESTMODE		0x00000008
 #define BGE_BMANMODE_LOMBUF_ATTN	0x00000010
 
 /* Buffer manager status register */
 #define BGE_BMANSTAT_ERRO		0x00000004
 #define BGE_BMANSTAT_LOWMBUF_ERROR	0x00000010
 
 
 /*
  * Read DMA Control registers
  */
 #define BGE_RDMA_MODE			0x4800
 #define BGE_RDMA_STATUS			0x4804
 
 /* Read DMA mode register */
 #define BGE_RDMAMODE_RESET		0x00000001
 #define BGE_RDMAMODE_ENABLE		0x00000002
 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_RDMAMODE_PCI_PERR_ATTN	0x00000010
 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_RDMAMODE_LOCWRITE_TOOBIG	0x00000200
 #define BGE_RDMAMODE_ALL_ATTNS		0x000003FC
 
 /* Read DMA status register */
 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_RDMASTAT_PCI_PERR_ATTN	0x00000010
 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_RDMASTAT_LOCWRITE_TOOBIG	0x00000200
 
 /*
  * Write DMA control registers
  */
 #define BGE_WDMA_MODE			0x4C00
 #define BGE_WDMA_STATUS			0x4C04
 
 /* Write DMA mode register */
 #define BGE_WDMAMODE_RESET		0x00000001
 #define BGE_WDMAMODE_ENABLE		0x00000002
 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_WDMAMODE_PCI_PERR_ATTN	0x00000010
 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_WDMAMODE_LOCREAD_TOOBIG	0x00000200
 #define BGE_WDMAMODE_ALL_ATTNS		0x000003FC
 
 /* Write DMA status register */
 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_WDMASTAT_PCI_PERR_ATTN	0x00000010
 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_WDMASTAT_LOCREAD_TOOBIG	0x00000200
 
 
 /*
  * RX CPU registers
  */
 #define BGE_RXCPU_MODE			0x5000
 #define BGE_RXCPU_STATUS		0x5004
 #define BGE_RXCPU_PC			0x501C
 
 /* RX CPU mode register */
 #define BGE_RXCPUMODE_RESET		0x00000001
 #define BGE_RXCPUMODE_SINGLESTEP	0x00000002
 #define BGE_RXCPUMODE_P0_DATAHLT_ENB	0x00000004
 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB	0x00000008
 #define BGE_RXCPUMODE_WR_POSTBUF_ENB	0x00000010
 #define BGE_RXCPUMODE_DATACACHE_ENB	0x00000020
 #define BGE_RXCPUMODE_ROMFAIL		0x00000040
 #define BGE_RXCPUMODE_WATCHDOG_ENB	0x00000080
 #define BGE_RXCPUMODE_INSTRCACHE_PRF	0x00000100
 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH	0x00000200
 #define BGE_RXCPUMODE_HALTCPU		0x00000400
 #define BGE_RXCPUMODE_INVDATAHLT_ENB	0x00000800
 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB	0x00002000
 
 /* RX CPU status register */
 #define BGE_RXCPUSTAT_HW_BREAKPOINT	0x00000001
 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
 #define BGE_RXCPUSTAT_INVALID_INSTR	0x00000004
 #define BGE_RXCPUSTAT_P0_DATAREF	0x00000008
 #define BGE_RXCPUSTAT_P0_INSTRREF	0x00000010
 #define BGE_RXCPUSTAT_INVALID_DATAACC	0x00000020
 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH	0x00000040
 #define BGE_RXCPUSTAT_BAD_MEMALIGN	0x00000080
 #define BGE_RXCPUSTAT_MADDR_TRAP	0x00000100
 #define BGE_RXCPUSTAT_REGADDR_TRAP	0x00000200
 #define BGE_RXCPUSTAT_DATAACC_STALL	0x00001000
 #define BGE_RXCPUSTAT_INSTRFETCH_STALL	0x00002000
 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
 #define BGE_RXCPUSTAT_BLOCKING_READ	0x80000000
 
 
 /*
  * TX CPU registers
  */
 #define BGE_TXCPU_MODE			0x5400
 #define BGE_TXCPU_STATUS		0x5404
 #define BGE_TXCPU_PC			0x541C
 
 /* TX CPU mode register */
 #define BGE_TXCPUMODE_RESET		0x00000001
 #define BGE_TXCPUMODE_SINGLESTEP	0x00000002
 #define BGE_TXCPUMODE_P0_DATAHLT_ENB	0x00000004
 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB	0x00000008
 #define BGE_TXCPUMODE_WR_POSTBUF_ENB	0x00000010
 #define BGE_TXCPUMODE_DATACACHE_ENB	0x00000020
 #define BGE_TXCPUMODE_ROMFAIL		0x00000040
 #define BGE_TXCPUMODE_WATCHDOG_ENB	0x00000080
 #define BGE_TXCPUMODE_INSTRCACHE_PRF	0x00000100
 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH	0x00000200
 #define BGE_TXCPUMODE_HALTCPU		0x00000400
 #define BGE_TXCPUMODE_INVDATAHLT_ENB	0x00000800
 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
 
 /* TX CPU status register */
 #define BGE_TXCPUSTAT_HW_BREAKPOINT	0x00000001
 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
 #define BGE_TXCPUSTAT_INVALID_INSTR	0x00000004
 #define BGE_TXCPUSTAT_P0_DATAREF	0x00000008
 #define BGE_TXCPUSTAT_P0_INSTRREF	0x00000010
 #define BGE_TXCPUSTAT_INVALID_DATAACC	0x00000020
 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH	0x00000040
 #define BGE_TXCPUSTAT_BAD_MEMALIGN	0x00000080
 #define BGE_TXCPUSTAT_MADDR_TRAP	0x00000100
 #define BGE_TXCPUSTAT_REGADDR_TRAP	0x00000200
 #define BGE_TXCPUSTAT_DATAACC_STALL	0x00001000
 #define BGE_TXCPUSTAT_INSTRFETCH_STALL	0x00002000
 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
 #define BGE_TXCPUSTAT_BLOCKING_READ	0x80000000
 
 
 /*
  * Low priority mailbox registers
  */
 #define BGE_LPMBX_IRQ0_HI		0x5800
 #define BGE_LPMBX_IRQ0_LO		0x5804
 #define BGE_LPMBX_IRQ1_HI		0x5808
 #define BGE_LPMBX_IRQ1_LO		0x580C
 #define BGE_LPMBX_IRQ2_HI		0x5810
 #define BGE_LPMBX_IRQ2_LO		0x5814
 #define BGE_LPMBX_IRQ3_HI		0x5818
 #define BGE_LPMBX_IRQ3_LO		0x581C
 #define BGE_LPMBX_GEN0_HI		0x5820
 #define BGE_LPMBX_GEN0_LO		0x5824
 #define BGE_LPMBX_GEN1_HI		0x5828
 #define BGE_LPMBX_GEN1_LO		0x582C
 #define BGE_LPMBX_GEN2_HI		0x5830
 #define BGE_LPMBX_GEN2_LO		0x5834
 #define BGE_LPMBX_GEN3_HI		0x5828
 #define BGE_LPMBX_GEN3_LO		0x582C
 #define BGE_LPMBX_GEN4_HI		0x5840
 #define BGE_LPMBX_GEN4_LO		0x5844
 #define BGE_LPMBX_GEN5_HI		0x5848
 #define BGE_LPMBX_GEN5_LO		0x584C
 #define BGE_LPMBX_GEN6_HI		0x5850
 #define BGE_LPMBX_GEN6_LO		0x5854
 #define BGE_LPMBX_GEN7_HI		0x5858
 #define BGE_LPMBX_GEN7_LO		0x585C
 #define BGE_LPMBX_RELOAD_STATS_HI	0x5860
 #define BGE_LPMBX_RELOAD_STATS_LO	0x5864
 #define BGE_LPMBX_RX_STD_PROD_HI	0x5868
 #define BGE_LPMBX_RX_STD_PROD_LO	0x586C
 #define BGE_LPMBX_RX_JUMBO_PROD_HI	0x5870
 #define BGE_LPMBX_RX_JUMBO_PROD_LO	0x5874
 #define BGE_LPMBX_RX_MINI_PROD_HI	0x5878
 #define BGE_LPMBX_RX_MINI_PROD_LO	0x587C
 #define BGE_LPMBX_RX_CONS0_HI		0x5880
 #define BGE_LPMBX_RX_CONS0_LO		0x5884
 #define BGE_LPMBX_RX_CONS1_HI		0x5888
 #define BGE_LPMBX_RX_CONS1_LO		0x588C
 #define BGE_LPMBX_RX_CONS2_HI		0x5890
 #define BGE_LPMBX_RX_CONS2_LO		0x5894
 #define BGE_LPMBX_RX_CONS3_HI		0x5898
 #define BGE_LPMBX_RX_CONS3_LO		0x589C
 #define BGE_LPMBX_RX_CONS4_HI		0x58A0
 #define BGE_LPMBX_RX_CONS4_LO		0x58A4
 #define BGE_LPMBX_RX_CONS5_HI		0x58A8
 #define BGE_LPMBX_RX_CONS5_LO		0x58AC
 #define BGE_LPMBX_RX_CONS6_HI		0x58B0
 #define BGE_LPMBX_RX_CONS6_LO		0x58B4
 #define BGE_LPMBX_RX_CONS7_HI		0x58B8
 #define BGE_LPMBX_RX_CONS7_LO		0x58BC
 #define BGE_LPMBX_RX_CONS8_HI		0x58C0
 #define BGE_LPMBX_RX_CONS8_LO		0x58C4
 #define BGE_LPMBX_RX_CONS9_HI		0x58C8
 #define BGE_LPMBX_RX_CONS9_LO		0x58CC
 #define BGE_LPMBX_RX_CONS10_HI		0x58D0
 #define BGE_LPMBX_RX_CONS10_LO		0x58D4
 #define BGE_LPMBX_RX_CONS11_HI		0x58D8
 #define BGE_LPMBX_RX_CONS11_LO		0x58DC
 #define BGE_LPMBX_RX_CONS12_HI		0x58E0
 #define BGE_LPMBX_RX_CONS12_LO		0x58E4
 #define BGE_LPMBX_RX_CONS13_HI		0x58E8
 #define BGE_LPMBX_RX_CONS13_LO		0x58EC
 #define BGE_LPMBX_RX_CONS14_HI		0x58F0
 #define BGE_LPMBX_RX_CONS14_LO		0x58F4
 #define BGE_LPMBX_RX_CONS15_HI		0x58F8
 #define BGE_LPMBX_RX_CONS15_LO		0x58FC
 #define BGE_LPMBX_TX_HOST_PROD0_HI	0x5900
 #define BGE_LPMBX_TX_HOST_PROD0_LO	0x5904
 #define BGE_LPMBX_TX_HOST_PROD1_HI	0x5908
 #define BGE_LPMBX_TX_HOST_PROD1_LO	0x590C
 #define BGE_LPMBX_TX_HOST_PROD2_HI	0x5910
 #define BGE_LPMBX_TX_HOST_PROD2_LO	0x5914
 #define BGE_LPMBX_TX_HOST_PROD3_HI	0x5918
 #define BGE_LPMBX_TX_HOST_PROD3_LO	0x591C
 #define BGE_LPMBX_TX_HOST_PROD4_HI	0x5920
 #define BGE_LPMBX_TX_HOST_PROD4_LO	0x5924
 #define BGE_LPMBX_TX_HOST_PROD5_HI	0x5928
 #define BGE_LPMBX_TX_HOST_PROD5_LO	0x592C
 #define BGE_LPMBX_TX_HOST_PROD6_HI	0x5930
 #define BGE_LPMBX_TX_HOST_PROD6_LO	0x5934
 #define BGE_LPMBX_TX_HOST_PROD7_HI	0x5938
 #define BGE_LPMBX_TX_HOST_PROD7_LO	0x593C
 #define BGE_LPMBX_TX_HOST_PROD8_HI	0x5940
 #define BGE_LPMBX_TX_HOST_PROD8_LO	0x5944
 #define BGE_LPMBX_TX_HOST_PROD9_HI	0x5948
 #define BGE_LPMBX_TX_HOST_PROD9_LO	0x594C
 #define BGE_LPMBX_TX_HOST_PROD10_HI	0x5950
 #define BGE_LPMBX_TX_HOST_PROD10_LO	0x5954
 #define BGE_LPMBX_TX_HOST_PROD11_HI	0x5958
 #define BGE_LPMBX_TX_HOST_PROD11_LO	0x595C
 #define BGE_LPMBX_TX_HOST_PROD12_HI	0x5960
 #define BGE_LPMBX_TX_HOST_PROD12_LO	0x5964
 #define BGE_LPMBX_TX_HOST_PROD13_HI	0x5968
 #define BGE_LPMBX_TX_HOST_PROD13_LO	0x596C
 #define BGE_LPMBX_TX_HOST_PROD14_HI	0x5970
 #define BGE_LPMBX_TX_HOST_PROD14_LO	0x5974
 #define BGE_LPMBX_TX_HOST_PROD15_HI	0x5978
 #define BGE_LPMBX_TX_HOST_PROD15_LO	0x597C
 #define BGE_LPMBX_TX_NIC_PROD0_HI	0x5980
 #define BGE_LPMBX_TX_NIC_PROD0_LO	0x5984
 #define BGE_LPMBX_TX_NIC_PROD1_HI	0x5988
 #define BGE_LPMBX_TX_NIC_PROD1_LO	0x598C
 #define BGE_LPMBX_TX_NIC_PROD2_HI	0x5990
 #define BGE_LPMBX_TX_NIC_PROD2_LO	0x5994
 #define BGE_LPMBX_TX_NIC_PROD3_HI	0x5998
 #define BGE_LPMBX_TX_NIC_PROD3_LO	0x599C
 #define BGE_LPMBX_TX_NIC_PROD4_HI	0x59A0
 #define BGE_LPMBX_TX_NIC_PROD4_LO	0x59A4
 #define BGE_LPMBX_TX_NIC_PROD5_HI	0x59A8
 #define BGE_LPMBX_TX_NIC_PROD5_LO	0x59AC
 #define BGE_LPMBX_TX_NIC_PROD6_HI	0x59B0
 #define BGE_LPMBX_TX_NIC_PROD6_LO	0x59B4
 #define BGE_LPMBX_TX_NIC_PROD7_HI	0x59B8
 #define BGE_LPMBX_TX_NIC_PROD7_LO	0x59BC
 #define BGE_LPMBX_TX_NIC_PROD8_HI	0x59C0
 #define BGE_LPMBX_TX_NIC_PROD8_LO	0x59C4
 #define BGE_LPMBX_TX_NIC_PROD9_HI	0x59C8
 #define BGE_LPMBX_TX_NIC_PROD9_LO	0x59CC
 #define BGE_LPMBX_TX_NIC_PROD10_HI	0x59D0
 #define BGE_LPMBX_TX_NIC_PROD10_LO	0x59D4
 #define BGE_LPMBX_TX_NIC_PROD11_HI	0x59D8
 #define BGE_LPMBX_TX_NIC_PROD11_LO	0x59DC
 #define BGE_LPMBX_TX_NIC_PROD12_HI	0x59E0
 #define BGE_LPMBX_TX_NIC_PROD12_LO	0x59E4
 #define BGE_LPMBX_TX_NIC_PROD13_HI	0x59E8
 #define BGE_LPMBX_TX_NIC_PROD13_LO	0x59EC
 #define BGE_LPMBX_TX_NIC_PROD14_HI	0x59F0
 #define BGE_LPMBX_TX_NIC_PROD14_LO	0x59F4
 #define BGE_LPMBX_TX_NIC_PROD15_HI	0x59F8
 #define BGE_LPMBX_TX_NIC_PROD15_LO	0x59FC
 
 /*
  * Flow throw Queue reset register
  */
 #define BGE_FTQ_RESET			0x5C00
 
 #define BGE_FTQRESET_DMAREAD		0x00000002
 #define BGE_FTQRESET_DMAHIPRIO_RD	0x00000004
 #define BGE_FTQRESET_DMADONE		0x00000010
 #define BGE_FTQRESET_SBDC		0x00000020
 #define BGE_FTQRESET_SDI		0x00000040
 #define BGE_FTQRESET_WDMA		0x00000080
 #define BGE_FTQRESET_DMAHIPRIO_WR	0x00000100
 #define BGE_FTQRESET_TYPE1_SOFTWARE	0x00000200
 #define BGE_FTQRESET_SDC		0x00000400
 #define BGE_FTQRESET_HCC		0x00000800
 #define BGE_FTQRESET_TXFIFO		0x00001000
 #define BGE_FTQRESET_MBC		0x00002000
 #define BGE_FTQRESET_RBDC		0x00004000
 #define BGE_FTQRESET_RXLP		0x00008000
 #define BGE_FTQRESET_RDBDI		0x00010000
 #define BGE_FTQRESET_RDC		0x00020000
 #define BGE_FTQRESET_TYPE2_SOFTWARE	0x00040000
 
 /*
  * Message Signaled Interrupt registers
  */
 #define BGE_MSI_MODE			0x6000
 #define BGE_MSI_STATUS			0x6004
 #define BGE_MSI_FIFOACCESS		0x6008
 
 /* MSI mode register */
 #define BGE_MSIMODE_RESET		0x00000001
 #define BGE_MSIMODE_ENABLE		0x00000002
 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_MSIMODE_PCI_PERR_ATTN	0x00000010
 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN	0x00000020
 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN	0x00000040
 
 /* MSI status register */
 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_MSISTAT_PCI_PERR_ATTN	0x00000010
 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN	0x00000020
 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN	0x00000040
 
 
 /*
  * DMA Completion registers
  */
 #define BGE_DMAC_MODE			0x6400
 
 /* DMA Completion mode register */
 #define BGE_DMACMODE_RESET		0x00000001
 #define BGE_DMACMODE_ENABLE		0x00000002
 
 
 /*
  * General control registers.
  */
 #define BGE_MODE_CTL			0x6800
 #define BGE_MISC_CFG			0x6804
 #define BGE_MISC_LOCAL_CTL		0x6808
 #define BGE_EE_ADDR			0x6838
 #define BGE_EE_DATA			0x683C
 #define BGE_EE_CTL			0x6840
 #define BGE_MDI_CTL			0x6844
 #define BGE_EE_DELAY			0x6848
 
 /* Mode control register */
 #define BGE_MODECTL_INT_SNDCOAL_ONLY	0x00000001
 #define BGE_MODECTL_BYTESWAP_NONFRAME	0x00000002
 #define BGE_MODECTL_WORDSWAP_NONFRAME	0x00000004
 #define BGE_MODECTL_BYTESWAP_DATA	0x00000010
 #define BGE_MODECTL_WORDSWAP_DATA	0x00000020
 #define BGE_MODECTL_NO_FRAME_CRACKING	0x00000200
 #define BGE_MODECTL_NO_RX_CRC		0x00000400
 #define BGE_MODECTL_RX_BADFRAMES	0x00000800
 #define BGE_MODECTL_NO_TX_INTR		0x00002000
 #define BGE_MODECTL_NO_RX_INTR		0x00004000
 #define BGE_MODECTL_FORCE_PCI32		0x00008000
 #define BGE_MODECTL_STACKUP		0x00010000
 #define BGE_MODECTL_HOST_SEND_BDS	0x00020000
 #define BGE_MODECTL_TX_NO_PHDR_CSUM	0x00100000
 #define BGE_MODECTL_RX_NO_PHDR_CSUM	0x00800000
 #define BGE_MODECTL_TX_ATTN_INTR	0x01000000
 #define BGE_MODECTL_RX_ATTN_INTR	0x02000000
 #define BGE_MODECTL_MAC_ATTN_INTR	0x04000000
 #define BGE_MODECTL_DMA_ATTN_INTR	0x08000000
 #define BGE_MODECTL_FLOWCTL_ATTN_INTR	0x10000000
 #define BGE_MODECTL_4X_SENDRING_SZ	0x20000000
 #define BGE_MODECTL_FW_PROCESS_MCASTS	0x40000000
 
 /* Misc. config register */
 #define BGE_MISCCFG_RESET_CORE_CLOCKS	0x00000001
 #define BGE_MISCCFG_TIMER_PRESCALER	0x000000FE
 
 #define BGE_32BITTIME_66MHZ		(0x41 << 1)
 
 /* Misc. Local Control */
 #define BGE_MLC_INTR_STATE		0x00000001
 #define BGE_MLC_INTR_CLR		0x00000002
 #define BGE_MLC_INTR_SET		0x00000004
 #define BGE_MLC_INTR_ONATTN		0x00000008
 #define BGE_MLC_MISCIO_IN0		0x00000100
 #define BGE_MLC_MISCIO_IN1		0x00000200
 #define BGE_MLC_MISCIO_IN2		0x00000400
 #define BGE_MLC_MISCIO_OUTEN0		0x00000800
 #define BGE_MLC_MISCIO_OUTEN1		0x00001000
 #define BGE_MLC_MISCIO_OUTEN2		0x00002000
 #define BGE_MLC_MISCIO_OUT0		0x00004000
 #define BGE_MLC_MISCIO_OUT1		0x00008000
 #define BGE_MLC_MISCIO_OUT2		0x00010000
 #define BGE_MLC_EXTRAM_ENB		0x00020000
 #define BGE_MLC_SRAM_SIZE		0x001C0000
 #define BGE_MLC_BANK_SEL		0x00200000 /* 0 = 2 banks, 1 == 1 */
 #define BGE_MLC_SSRAM_TYPE		0x00400000 /* 1 = ZBT, 0 = standard */
 #define BGE_MLC_SSRAM_CYC_DESEL		0x00800000
 #define BGE_MLC_AUTO_EEPROM		0x01000000
 
 #define BGE_SSRAMSIZE_256KB		0x00000000
 #define BGE_SSRAMSIZE_512KB		0x00040000
 #define BGE_SSRAMSIZE_1MB		0x00080000
 #define BGE_SSRAMSIZE_2MB		0x000C0000
 #define BGE_SSRAMSIZE_4MB		0x00100000
 #define BGE_SSRAMSIZE_8MB		0x00140000
 #define BGE_SSRAMSIZE_16M		0x00180000
 
 /* EEPROM address register */
 #define BGE_EEADDR_ADDRESS		0x0000FFFC
 #define BGE_EEADDR_HALFCLK		0x01FF0000
 #define BGE_EEADDR_START		0x02000000
 #define BGE_EEADDR_DEVID		0x1C000000
 #define BGE_EEADDR_RESET		0x20000000
 #define BGE_EEADDR_DONE			0x40000000
 #define BGE_EEADDR_RW			0x80000000 /* 1 = rd, 0 = wr */
 
 #define BGE_EEDEVID(x)			((x & 7) << 26)
 #define BGE_EEHALFCLK(x)		((x & 0x1FF) << 16)
 #define BGE_HALFCLK_384SCL		0x60
 #define BGE_EE_READCMD \
 	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
 	BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
 #define BGE_EE_WRCMD \
 	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
 	BGE_EEADDR_START|BGE_EEADDR_DONE)
 
 /* EEPROM Control register */
 #define BGE_EECTL_CLKOUT_TRISTATE	0x00000001
 #define BGE_EECTL_CLKOUT		0x00000002
 #define BGE_EECTL_CLKIN			0x00000004
 #define BGE_EECTL_DATAOUT_TRISTATE	0x00000008
 #define BGE_EECTL_DATAOUT		0x00000010
 #define BGE_EECTL_DATAIN		0x00000020
 
 /* MDI (MII/GMII) access register */
 #define BGE_MDI_DATA			0x00000001
 #define BGE_MDI_DIR			0x00000002
 #define BGE_MDI_SEL			0x00000004
 #define BGE_MDI_CLK			0x00000008
 
 #define BGE_MEMWIN_START		0x00008000
 #define BGE_MEMWIN_END			0x0000FFFF
 
 
 #define BGE_MEMWIN_READ(sc, x, val)					\
 	do {								\
 		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
 		    (0xFFFF0000 & x), 4);				\
 		val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF));	\
 	} while(0)
 
 #define BGE_MEMWIN_WRITE(sc, x, val)					\
 	do {								\
 		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
 		    (0xFFFF0000 & x), 4);				\
 		CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val);	\
 	} while(0)
 
 /*
  * This magic number is used to prevent PXE restart when we
  * issue a software reset. We write this magic number to the
  * firmware mailbox at 0xB50 in order to prevent the PXE boot
  * code from running.
  */
 #define BGE_MAGIC_NUMBER                0x4B657654
 
 typedef struct {
 	u_int32_t		bge_addr_hi;
 	u_int32_t		bge_addr_lo;
 } bge_hostaddr;
 #define BGE_HOSTADDR(x)	x.bge_addr_lo
 
 /* Ring control block structure */
 struct bge_rcb {
 	bge_hostaddr		bge_hostaddr;
 	u_int16_t		bge_flags;
 	u_int16_t		bge_max_len;
 	u_int32_t		bge_nicaddr;
 };
 
 struct bge_rcb_opaque {
 	u_int32_t		bge_reg0;
 	u_int32_t		bge_reg1;
 	u_int32_t		bge_reg2;
 	u_int32_t		bge_reg3;
 };
 
 #define BGE_RCB_FLAG_USE_EXT_RX_BD	0x0001
 #define BGE_RCB_FLAG_RING_DISABLED	0x0002
 
 struct bge_tx_bd {
 	bge_hostaddr		bge_addr;
 	u_int16_t		bge_flags;
 	u_int16_t		bge_len;
 	u_int16_t		bge_vlan_tag;
 	u_int16_t		bge_rsvd;
 };
 
 #define BGE_TXBDFLAG_TCP_UDP_CSUM	0x0001
 #define BGE_TXBDFLAG_IP_CSUM		0x0002
 #define BGE_TXBDFLAG_END		0x0004
 #define BGE_TXBDFLAG_IP_FRAG		0x0008
 #define BGE_TXBDFLAG_IP_FRAG_END	0x0010
 #define BGE_TXBDFLAG_VLAN_TAG		0x0040
 #define BGE_TXBDFLAG_COAL_NOW		0x0080
 #define BGE_TXBDFLAG_CPU_PRE_DMA	0x0100
 #define BGE_TXBDFLAG_CPU_POST_DMA	0x0200
 #define BGE_TXBDFLAG_INSERT_SRC_ADDR	0x1000
 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR	0x6000
 #define BGE_TXBDFLAG_NO_CRC		0x8000
 
 #define BGE_NIC_TXRING_ADDR(ringno, size)	\
 	BGE_SEND_RING_1_TO_4 +			\
 	((ringno * sizeof(struct bge_tx_bd) * size) / 4)
 
 struct bge_rx_bd {
 	bge_hostaddr		bge_addr;
 	u_int16_t		bge_len;
 	u_int16_t		bge_idx;
 	u_int16_t		bge_flags;
 	u_int16_t		bge_type;
 	u_int16_t		bge_tcp_udp_csum;
 	u_int16_t		bge_ip_csum;
 	u_int16_t		bge_vlan_tag;
 	u_int16_t		bge_error_flag;
 	u_int32_t		bge_rsvd;
 	u_int32_t		bge_opaque;
 };
 
 #define BGE_RXBDFLAG_END		0x0004
 #define BGE_RXBDFLAG_JUMBO_RING		0x0020
 #define BGE_RXBDFLAG_VLAN_TAG		0x0040
 #define BGE_RXBDFLAG_ERROR		0x0400
 #define BGE_RXBDFLAG_MINI_RING		0x0800
 #define BGE_RXBDFLAG_IP_CSUM		0x1000
 #define BGE_RXBDFLAG_TCP_UDP_CSUM	0x2000
 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP	0x4000
 
 #define BGE_RXERRFLAG_BAD_CRC		0x0001
 #define BGE_RXERRFLAG_COLL_DETECT	0x0002
 #define BGE_RXERRFLAG_LINK_LOST		0x0004
 #define BGE_RXERRFLAG_PHY_DECODE_ERR	0x0008
 #define BGE_RXERRFLAG_MAC_ABORT		0x0010
 #define BGE_RXERRFLAG_RUNT		0x0020
 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS	0x0040
 #define BGE_RXERRFLAG_GIANT		0x0080
 
 struct bge_sts_idx {
 	u_int16_t		bge_rx_prod_idx;
 	u_int16_t		bge_tx_cons_idx;
 };
 
 struct bge_status_block {
 	u_int32_t		bge_status;
 	u_int32_t		bge_rsvd0;
 	u_int16_t		bge_rx_jumbo_cons_idx;
 	u_int16_t		bge_rx_std_cons_idx;
 	u_int16_t		bge_rx_mini_cons_idx;
 	u_int16_t		bge_rsvd1;
 	struct bge_sts_idx	bge_idx[16];
 };
 
 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
 
 #define BGE_STATFLAG_UPDATED		0x00000001
 #define BGE_STATFLAG_LINKSTATE_CHANGED	0x00000002
 #define BGE_STATFLAG_ERROR		0x00000004
 
 
 /*
  * Broadcom Vendor ID
  * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
  * even though they're now manufactured by Broadcom)
  */
 #define BCOM_VENDORID			0x14E4
 #define BCOM_DEVICEID_BCM5700		0x1644
 #define BCOM_DEVICEID_BCM5701		0x1645
 
 /*
  * Alteon AceNIC PCI vendor/device ID.
  */
 #define ALT_VENDORID			0x12AE
 #define ALT_DEVICEID_ACENIC		0x0001
 #define ALT_DEVICEID_ACENIC_COPPER	0x0002
 #define ALT_DEVICEID_BCM5700		0x0003
 #define ALT_DEVICEID_BCM5701		0x0004
 
 /*
  * 3Com 3c985 PCI vendor/device ID.
  */
 #define TC_VENDORID			0x10B7
 #define TC_DEVICEID_3C985		0x0001
 #define TC_DEVICEID_3C996		0x0003
 
 /*
  * SysKonnect PCI vendor ID
  */
 #define SK_VENDORID			0x1148
 #define SK_DEVICEID_ALTIMA		0x4400
 #define SK_SUBSYSID_9D21		0x4421
 #define SK_SUBSYSID_9D41		0x4441
 
 /*
+ * Altima PCI vendor/device ID.
+ */
+#define ALTIMA_VENDORID			0x173b
+#define ALTIMA_DEVICE_AC1000		0x03e8
+
+/*
  * Offset of MAC address inside EEPROM.
  */
 #define BGE_EE_MAC_OFFSET		0x7C
 #define BGE_EE_HWCFG_OFFSET		0xC8
 
 #define BGE_PCI_READ_CMD		0x06000000
 #define BGE_PCI_WRITE_CMD		0x70000000
 
 #define BGE_TICKS_PER_SEC		1000000
 
 /*
  * Ring size constants.
  */
 #define BGE_EVENT_RING_CNT	256
 #define BGE_CMD_RING_CNT	64
 #define BGE_STD_RX_RING_CNT	512
 #define BGE_JUMBO_RX_RING_CNT	256
 #define BGE_MINI_RX_RING_CNT	1024
 #define BGE_RETURN_RING_CNT	1024
 
 /*
  * Possible TX ring sizes.
  */
 #define BGE_TX_RING_CNT_128	128
 #define BGE_TX_RING_BASE_128	0x3800
 
 #define BGE_TX_RING_CNT_256	256
 #define BGE_TX_RING_BASE_256	0x3000
 
 #define BGE_TX_RING_CNT_512	512
 #define BGE_TX_RING_BASE_512	0x2000
 
 #define BGE_TX_RING_CNT		BGE_TX_RING_CNT_512
 #define BGE_TX_RING_BASE	BGE_TX_RING_BASE_512
 
 /*
  * Tigon III statistics counters.
  */
 struct bge_stats {
 	u_int8_t		Reserved0[256];
 
 	/* Statistics maintained by Receive MAC. */
 	bge_hostaddr		ifHCInOctets;
 	bge_hostaddr		Reserved1;
 	bge_hostaddr		etherStatsFragments;
 	bge_hostaddr		ifHCInUcastPkts;
 	bge_hostaddr		ifHCInMulticastPkts;
 	bge_hostaddr		ifHCInBroadcastPkts;
 	bge_hostaddr		dot3StatsFCSErrors;
 	bge_hostaddr		dot3StatsAlignmentErrors;
 	bge_hostaddr		xonPauseFramesReceived;
 	bge_hostaddr		xoffPauseFramesReceived;
 	bge_hostaddr		macControlFramesReceived;
 	bge_hostaddr		xoffStateEntered;
 	bge_hostaddr		dot3StatsFramesTooLong;
 	bge_hostaddr		etherStatsJabbers;
 	bge_hostaddr		etherStatsUndersizePkts;
 	bge_hostaddr		inRangeLengthError;
 	bge_hostaddr		outRangeLengthError;
 	bge_hostaddr		etherStatsPkts64Octets;
 	bge_hostaddr		etherStatsPkts65Octetsto127Octets;
 	bge_hostaddr		etherStatsPkts128Octetsto255Octets;
 	bge_hostaddr		etherStatsPkts256Octetsto511Octets;
 	bge_hostaddr		etherStatsPkts512Octetsto1023Octets;
 	bge_hostaddr		etherStatsPkts1024Octetsto1522Octets;
 	bge_hostaddr		etherStatsPkts1523Octetsto2047Octets;
 	bge_hostaddr		etherStatsPkts2048Octetsto4095Octets;
 	bge_hostaddr		etherStatsPkts4096Octetsto8191Octets;
 	bge_hostaddr		etherStatsPkts8192Octetsto9022Octets;
 
 	bge_hostaddr		Unused1[37];
 
 	/* Statistics maintained by Transmit MAC. */
 	bge_hostaddr		ifHCOutOctets;
 	bge_hostaddr		Reserved2;
 	bge_hostaddr		etherStatsCollisions;
 	bge_hostaddr		outXonSent;
 	bge_hostaddr		outXoffSent;
 	bge_hostaddr		flowControlDone;
 	bge_hostaddr		dot3StatsInternalMacTransmitErrors;
 	bge_hostaddr		dot3StatsSingleCollisionFrames;
 	bge_hostaddr		dot3StatsMultipleCollisionFrames;
 	bge_hostaddr		dot3StatsDeferredTransmissions;
 	bge_hostaddr		Reserved3;
 	bge_hostaddr		dot3StatsExcessiveCollisions;
 	bge_hostaddr		dot3StatsLateCollisions;
 	bge_hostaddr		dot3Collided2Times;
 	bge_hostaddr		dot3Collided3Times;
 	bge_hostaddr		dot3Collided4Times;
 	bge_hostaddr		dot3Collided5Times;
 	bge_hostaddr		dot3Collided6Times;
 	bge_hostaddr		dot3Collided7Times;
 	bge_hostaddr		dot3Collided8Times;
 	bge_hostaddr		dot3Collided9Times;
 	bge_hostaddr		dot3Collided10Times;
 	bge_hostaddr		dot3Collided11Times;
 	bge_hostaddr		dot3Collided12Times;
 	bge_hostaddr		dot3Collided13Times;
 	bge_hostaddr		dot3Collided14Times;
 	bge_hostaddr		dot3Collided15Times;
 	bge_hostaddr		ifHCOutUcastPkts;
 	bge_hostaddr		ifHCOutMulticastPkts;
 	bge_hostaddr		ifHCOutBroadcastPkts;
 	bge_hostaddr		dot3StatsCarrierSenseErrors;
 	bge_hostaddr		ifOutDiscards;
 	bge_hostaddr		ifOutErrors;
 
 	bge_hostaddr		Unused2[31];
 
 	/* Statistics maintained by Receive List Placement. */
 	bge_hostaddr		COSIfHCInPkts[16];
 	bge_hostaddr		COSFramesDroppedDueToFilters;
 	bge_hostaddr		nicDmaWriteQueueFull;
 	bge_hostaddr		nicDmaWriteHighPriQueueFull;
 	bge_hostaddr		nicNoMoreRxBDs;
 	bge_hostaddr		ifInDiscards;
 	bge_hostaddr		ifInErrors;
 	bge_hostaddr		nicRecvThresholdHit;
 
 	bge_hostaddr		Unused3[9];
 
 	/* Statistics maintained by Send Data Initiator. */
 	bge_hostaddr		COSIfHCOutPkts[16];
 	bge_hostaddr		nicDmaReadQueueFull;
 	bge_hostaddr		nicDmaReadHighPriQueueFull;
 	bge_hostaddr		nicSendDataCompQueueFull;
 
 	/* Statistics maintained by Host Coalescing. */
 	bge_hostaddr		nicRingSetSendProdIndex;
 	bge_hostaddr		nicRingStatusUpdate;
 	bge_hostaddr		nicInterrupts;
 	bge_hostaddr		nicAvoidedInterrupts;
 	bge_hostaddr		nicSendThresholdHit;
 
 	u_int8_t		Reserved4[320];
 };
 
 /*
  * Tigon general information block. This resides in host memory
  * and contains the status counters, ring control blocks and
  * producer pointers.
  */
 
 struct bge_gib {
 	struct bge_stats	bge_stats;
 	struct bge_rcb		bge_tx_rcb[16];
 	struct bge_rcb		bge_std_rx_rcb;
 	struct bge_rcb		bge_jumbo_rx_rcb;
 	struct bge_rcb		bge_mini_rx_rcb;
 	struct bge_rcb		bge_return_rcb;
 };
 
 /*
  * NOTE!  On the Alpha, we have an alignment constraint.
  * The first thing in the packet is a 14-byte Ethernet header.
  * This means that the packet is misaligned.  To compensate,
  * we actually offset the data 2 bytes into the cluster.  This
  * alignes the packet after the Ethernet header at a 32-bit
  * boundary.
  */
 
 #define ETHER_ALIGN 2
 
 #define BGE_FRAMELEN		1518
 #define BGE_MAX_FRAMELEN	1536
 #define BGE_JUMBO_FRAMELEN	9018
 #define BGE_JUMBO_MTU		(BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
 #define BGE_PAGE_SIZE		PAGE_SIZE
 #define BGE_MIN_FRAMELEN		60
 
 /*
  * Other utility macros.
  */
 #define BGE_INC(x, y)	(x) = (x + 1) % y
 
 /*
  * Vital product data and structures.
  */
 #define BGE_VPD_FLAG		0x8000
  
 /* VPD structures */
 struct vpd_res {
 	u_int8_t		vr_id;
 	u_int8_t		vr_len;
 	u_int8_t		vr_pad;
 };
  
 struct vpd_key {
 	char			vk_key[2];
 	u_int8_t		vk_len;
 };
  
 #define VPD_RES_ID	0x82	/* ID string */
 #define VPD_RES_READ	0x90	/* start of read only area */
 #define VPD_RES_WRITE	0x81	/* start of read/write area */
 #define VPD_RES_END	0x78	/* end tag */
 
 
 /*
  * Register access macros. The Tigon always uses memory mapped register
  * accesses and all registers must be accessed with 32 bit operations.
  */
 
 #define CSR_WRITE_4(sc, reg, val)	\
 	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
 
 #define CSR_READ_4(sc, reg)		\
 	bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
 
 #define BGE_SETBIT(sc, reg, x)	\
 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
 #define BGE_CLRBIT(sc, reg, x)	\
 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
 
 #define PCI_SETBIT(dev, reg, x, s)	\
 	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
 #define PCI_CLRBIT(dev, reg, x, s)	\
 	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
 
 /*
  * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
  * values are tuneable. They control the actual amount of buffers
  * allocated for the standard, mini and jumbo receive rings.
  */
 
 #define BGE_SSLOTS	256
 #define BGE_MSLOTS	256
 #define BGE_JSLOTS	384
 
 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t))
 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \
 	(BGE_JRAWLEN % sizeof(u_int64_t))))
 #define BGE_JPAGESZ PAGE_SIZE
 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
 
 struct bge_jslot {
 	caddr_t			bge_buf;
         int			bge_inuse;
 };
 
 /*
  * Ring structures. Most of these reside in host memory and we tell
  * the NIC where they are via the ring control blocks. The exceptions
  * are the tx and command rings, which live in NIC memory and which
  * we access via the shared memory window.
  */
 struct bge_ring_data {
 	struct bge_rx_bd	bge_rx_std_ring[BGE_STD_RX_RING_CNT];
 	struct bge_rx_bd	bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT];
 	struct bge_rx_bd	bge_rx_return_ring[BGE_RETURN_RING_CNT];
 	struct bge_tx_bd	bge_tx_ring[BGE_TX_RING_CNT];
 	struct bge_status_block	bge_status_block;
 	struct bge_tx_desc	*bge_tx_ring_nic;/* pointer to shared mem */
 	struct bge_cmd_desc	*bge_cmd_ring;	/* pointer to shared mem */
 	struct bge_gib		bge_info;
 };
 
 /*
  * Mbuf pointers. We need these to keep track of the virtual addresses
  * of our mbuf chains since we can only convert from physical to virtual,
  * not the other way around.
  */
 struct bge_chain_data {
 	struct mbuf		*bge_tx_chain[BGE_TX_RING_CNT];
 	struct mbuf		*bge_rx_std_chain[BGE_STD_RX_RING_CNT];
 	struct mbuf		*bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
 	struct mbuf		*bge_rx_mini_chain[BGE_MINI_RX_RING_CNT];
 	/* Stick the jumbo mem management stuff here too. */
 	struct bge_jslot	bge_jslots[BGE_JSLOTS];
 	void			*bge_jumbo_buf;
 };
 
 struct bge_type {
 	u_int16_t		bge_vid;
 	u_int16_t		bge_did;
 	char			*bge_name;
 };
 
 #define BGE_HWREV_TIGON		0x01
 #define BGE_HWREV_TIGON_II	0x02
 #define BGE_TIMEOUT		1000
 #define BGE_TXCONS_UNSET		0xFFFF	/* impossible value */
 
 struct bge_jpool_entry {
 	int                             slot;
 	SLIST_ENTRY(bge_jpool_entry)	jpool_entries;
 };
 
 struct bge_bcom_hack {
 	int			reg;
 	int			val;
 };
 
 struct bge_softc {
 	struct arpcom		arpcom;		/* interface info */
 	device_t		bge_dev;
 	device_t		bge_miibus;
 	bus_space_handle_t	bge_bhandle;
 	vm_offset_t		bge_vhandle;
 	bus_space_tag_t		bge_btag;
 	void			*bge_intrhand;
 	struct resource		*bge_irq;
 	struct resource		*bge_res;
 	struct ifmedia		bge_ifmedia;	/* TBI media info */
 	u_int8_t		bge_unit;	/* interface number */
 	u_int8_t		bge_extram;	/* has external SSRAM */
 	u_int8_t		bge_tbi;
 	struct bge_ring_data	*bge_rdata;	/* rings */
 	struct bge_chain_data	bge_cdata;	/* mbufs */
 	u_int16_t		bge_tx_saved_considx;
 	u_int16_t		bge_rx_saved_considx;
 	u_int16_t		bge_ev_saved_considx;
 	u_int16_t		bge_std;	/* current std ring head */
 	u_int16_t		bge_jumbo;	/* current jumo ring head */
 	SLIST_HEAD(__bge_jfreehead, bge_jpool_entry)	bge_jfree_listhead;
 	SLIST_HEAD(__bge_jinusehead, bge_jpool_entry)	bge_jinuse_listhead;
 	u_int32_t		bge_stat_ticks;
 	u_int32_t		bge_rx_coal_ticks;
 	u_int32_t		bge_tx_coal_ticks;
 	u_int32_t		bge_rx_max_coal_bds;
 	u_int32_t		bge_tx_max_coal_bds;
 	u_int32_t		bge_tx_buf_ratio;
 	int			bge_if_flags;
 	int			bge_txcnt;
 	int			bge_link;
 	struct callout_handle	bge_stat_ch;
 	char			*bge_vpd_prodname;
 	char			*bge_vpd_readonly;
 };
 
 #ifdef __alpha__
 #undef vtophys
 #define vtophys(va)		alpha_XXX_dmamap((vm_offset_t)va)
 #endif
Index: stable/4/sys/i386/conf/LINT
===================================================================
--- stable/4/sys/i386/conf/LINT	(revision 90007)
+++ stable/4/sys/i386/conf/LINT	(revision 90008)
@@ -1,2619 +1,2619 @@
 #
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
 # $FreeBSD$
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
 # this file as required.
 #
 
 #
 # This directive is mandatory; it defines the architecture to be
 # configured for; in this case, the 386 family based IBM-PC and
 # compatibles.
 #
 machine		i386
 
 #
 # This is the ``identification'' of the kernel.  Usually this should
 # be the same as the name of your kernel.
 #
 ident		LINT
 
 #
 # The `maxusers' parameter controls the static sizing of a number of
 # internal system tables by a formula defined in subr_param.c.  Setting
 # maxusers to 0 will cause the system to auto-size based on physical
 # memory.
 #
 maxusers	10
 
 #
 # The `makeoptions' parameter allows variables to be passed to the
 # generated Makefile in the build area.
 #
 # CONF_CFLAGS gives some extra compiler flags that are added to ${CFLAGS}
 # after most other flags.  Here we use it to inhibit use of non-optimal
 # gcc builtin functions (e.g., memcmp).
 #
 # DEBUG happens to be magic.
 # The following is equivalent to 'config -g KERNELNAME' and creates
 # 'kernel.debug' compiled with -g debugging as well as a normal
 # 'kernel'.  Use 'make install.debug' to install the debug kernel
 # but that isn't normally necessary as the debug symbols are not loaded
 # by the kernel and are not useful there anyway.
 #
 # KERNEL can be overridden so that you can change the default name of your
 # kernel.
 #
 # MODULES_OVERRIDE can be used to limit modules built to a specific list.
 #
 makeoptions	CONF_CFLAGS=-fno-builtin  #Don't allow use of memcmp, etc.
 #makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
 #makeoptions	KERNEL=foo		#Build kernel "foo" and install "/foo"
 # Only build Linux API modules and plus those parts of the sound system I need.
 #makeoptions	MODULES_OVERRIDE="linux sound/snd sound/pcm sound/driver/maestro3"
 
 #
 # Certain applications can grow to be larger than the 128M limit
 # that FreeBSD initially imposes.  Below are some options to
 # allow that limit to grow to 256MB, and can be increased further
 # with changing the parameters.  MAXDSIZ is the maximum that the
 # limit can be set to, and the DFLDSIZ is the default value for
 # the limit.  MAXSSIZ is the maximum that the stack limit can be
 # set to.  You might want to set the default lower than the max, 
 # and explicitly set the maximum with a shell command for processes
 # that regularly exceed the limit like INND.
 #
 options 	MAXDSIZ="(256*1024*1024)"
 options 	MAXSSIZ="(256*1024*1024)"
 options 	DFLDSIZ="(256*1024*1024)"
 
 #
 # BLKDEV_IOSIZE sets the default block size used in user block
 # device I/O.  Note that this value will be overriden by the label
 # when specifying a block device from a label with a non-0
 # partition blocksize.  The default is PAGE_SIZE.
 #
 options 	BLKDEV_IOSIZE=8192
 
 # Options for the VM subsystem.
 options		PQ_CACHESIZE=512	# color for 512k/16k cache
 # Deprecated options supported for backwards compatibility.
 #options 	PQ_NOOPT		# No coloring
 #options 	PQ_LARGECACHE		# color for 512k/16k cache
 #options 	PQ_HUGECACHE		# color for 1024k/16k cache
 #options 	PQ_MEDIUMCACHE		# color for 256k/16k cache
 #options 	PQ_NORMALCACHE		# color for 64k/16k cache
 
 # This allows you to actually store this configuration file into
 # the kernel binary itself, where it may be later read by saying:
 #    strings -n 3 /kernel | sed -n 's/^___//p' > MYKERNEL
 #
 options 	INCLUDE_CONFIG_FILE     # Include this file in kernel
 
 #
 # The root device and filesystem type can be compiled in;
 # this provides a fallback option if the root device cannot
 # be correctly guessed by the bootstrap code, or an override if
 # the RB_DFLTROOT flag (-r) is specified when booting the kernel.
 #
 options 	ROOTDEVNAME=\"ufs:da0s2e\"
 
 
 #####################################################################
 # SMP OPTIONS:
 #
 # SMP enables building of a Symmetric MultiProcessor Kernel.
 # APIC_IO enables the use of the IO APIC for Symmetric I/O.
 #
 # Notes:
 #
 #  An SMP kernel will ONLY run on an Intel MP spec. qualified motherboard.
 #
 #  Be sure to disable 'cpu I386_CPU' && 'cpu I486_CPU' for SMP kernels.
 #
 #  Check the 'Rogue SMP hardware' section to see if additional options
 #   are required by your hardware.
 #
 
 # Mandatory:
 options 	SMP			# Symmetric MultiProcessor Kernel
 options 	APIC_IO			# Symmetric (APIC) I/O
 
 #
 # Rogue SMP hardware:
 #
 
 # Bridged PCI cards:
 #
 # The MP tables of most of the current generation MP motherboards
 #  do NOT properly support bridged PCI cards.  To use one of these
 #  cards you should refer to ???
 
 
 #####################################################################
 # CPU OPTIONS
 
 #
 # You must specify at least one CPU (the one you intend to run on);
 # deleting the specification for CPUs you don't need to use may make
 # parts of the system run faster.  This is especially true removing
 # I386_CPU.
 #
 cpu		I386_CPU
 cpu		I486_CPU
 cpu		I586_CPU		# aka Pentium(tm)
 cpu		I686_CPU		# aka Pentium Pro(tm)
 
 #
 # Options for CPU features.
 #
 # CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
 # BlueLightning CPU.  It works only with Cyrix FPU, and this option
 # should not be used with Intel FPU.
 #
 # CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning
 # CPU if CPU supports it. The default is double-clock mode on
 # BlueLightning CPU box.
 #
 # CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
 #
 # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
 # mapped mode.  Default is 2-way set associative mode.
 #
 # CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
 # of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
 # Otherwise, the NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
 #
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s).
 #
 # CPU_ENABLE_SSE enables SSE/MMX2 instructions support.
 #
 # CPU_FASTER_5X86_FPU enables faster FPU exception handler.
 #
 # CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
 # for i386 machines.
 #
 # CPU_IORT defines I/O clock delay time (NOTE 1).  Default values of
 # I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
 # (no clock delay).
 #
 # CPU_L2_LATENCY specifed the L2 cache latency value.  This option is used
 # only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
 # The default value is 5.
 #
 # CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
 # of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
 # 1).
 #
 # CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs.  This option
 # is useful when you use Socket 8 to Socket 370 converter, because most Pentium
 # Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
 #
 # CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
 #
 # CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
 # enters suspend mode following execution of HALT instruction.
 #
 # CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
 # K5/K6/K6-2 cpus.
 #
 # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
 # flush at hold state.
 #
 # CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
 # without cache flush at hold state, and (2) write-back CPU cache on
 # Cyrix 6x86 whose revision < 2.7 (NOTE 2).
 #
 # NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
 # Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
 # executed.  This option is only needed if I586_CPU is also defined,
 # and should be included for any non-Pentium CPU that defines it.
 #
 # NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors
 # which indicates that the 15-16MB range is *definitely* not being
 # occupied by an ISA memory hole.
 #
 # NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT,
 # CPU_LOOP_EN and CPU_RSTK_EN should not be used because of CPU bugs.
 # These options may crash your system.
 #
 # NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled
 # in write-through mode when revision < 2.7.  If revision of Cyrix
 # 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
 #
 # NOTE 3: This option may cause failures for software that requires
 # locked cycles in order to operate correctly.
 #
 options 	CPU_BLUELIGHTNING_FPU_OP_CACHE
 options 	CPU_BLUELIGHTNING_3X
 options 	CPU_BTB_EN
 options 	CPU_DIRECT_MAPPED_CACHE
 options 	CPU_DISABLE_5X86_LSSER
 options 	CPU_ENABLE_SSE
 options 	CPU_FASTER_5X86_FPU
 options 	CPU_I486_ON_386
 options 	CPU_IORT
 options 	CPU_L2_LATENCY=5
 options 	CPU_LOOP_EN
 options 	CPU_PPRO2CELERON
 options 	CPU_RSTK_EN
 options 	CPU_SUSP_HLT
 options 	CPU_WT_ALLOC
 options 	CYRIX_CACHE_WORKS
 options 	CYRIX_CACHE_REALLY_WORKS
 #options 	NO_F00F_HACK
 
 #
 # A math emulator is mandatory if you wish to run on hardware which
 # does not have a floating-point processor.  Pick either the original,
 # bogus (but freely-distributable) math emulator, or a much more
 # fully-featured but GPL-licensed emulator taken from Linux.
 #
 options 	MATH_EMULATE		#Support for x87 emulation
 # Don't enable both of these in a real config.
 options 	GPL_MATH_EMULATE	#Support for x87 emulation via
 					#new math emulator
 
 
 #####################################################################
 # COMPATIBILITY OPTIONS                                             
 
 #
 # Implement system calls compatible with 4.3BSD and older versions of
 # FreeBSD.  You probably do NOT want to remove this as much current code
 # still relies on the 4.3 emulation.
 #
 options 	COMPAT_43
 
 #
 # Allow applications running in user space to control the Local Descriptor
 # Table (LDT).  This is required by some ports.  Future versions of FreeBSD
 # may require this option for some programs in the base system.
 #
 options 	USER_LDT		#allow user-level control of i386 ldt
 
 #
 # These three options provide support for System V Interface
 # Definition-style interprocess communication, in the form of shared
 # memory, semaphores, and message queues, respectively.
 #
 # System V shared memory and tunable parameters
 options 	SYSVSHM		# include support for shared memory
 options 	SHMMAXPGS=1025	# max amount of shared memory pages (4k on i386)
 options 	SHMALL=1025	# max amount of shared memory (bytes)
 options 	SHMMAX="(SHMMAXPGS*PAGE_SIZE+1)"
 				# max shared memory segment size (bytes)
 options 	SHMMIN=2	# min shared memory segment size (bytes)
 options 	SHMMNI=33	# max number of shared memory identifiers
 options 	SHMSEG=9	# max shared memory segments per process
 
 # System V semaphores and tunable parameters
 options 	SYSVSEM		# include support for semaphores
 options 	SEMMAP=31	# amount of entries in semaphore map
 options 	SEMMNI=11	# number of semaphore identifiers in the system
 options 	SEMMNS=61	# number of semaphores in the system
 options 	SEMMNU=31	# number of undo structures in the system
 options 	SEMMSL=61	# max number of semaphores per id
 options 	SEMOPM=101	# max number of operations per semop call
 options 	SEMUME=11	# max number of undo entries per process
 
 # System V message queues and tunable parameters
 options 	SYSVMSG		# include support for message queues
 options 	MSGMNB=2049	# max characters per message queue
 options 	MSGMNI=41	# max number of message queue identifiers
 options 	MSGSEG=2049	# max number of message segments in the system
 options 	MSGSSZ=16	# size of a message segment MUST be power of 2
 options 	MSGTQL=41	# max amount of messages in the system
 
 
 #####################################################################
 # DEBUGGING OPTIONS
 
 #
 # Enable the kernel debugger.
 #
 options 	DDB
 
 #
 # Don't drop into DDB for a panic. Intended for unattended operation
 # where you may want to drop to DDB from the console, but still want
 # the machine to recover from a panic
 #
 options 	DDB_UNATTENDED
 
 #
 # If using GDB remote mode to debug the kernel, there's a non-standard
 # extension to the remote protocol that can be used to use the serial
 # port as both the debugging port and the system console.  It's non-
 # standard and you're on your own if you enable it.  See also the
 # "remotechat" variables in the FreeBSD specific version of gdb.
 #
 options 	GDB_REMOTE_CHAT
 
 #
 # KTRACE enables the system-call tracing facility ktrace(2).
 #
 options 	KTRACE			#kernel tracing
 
 #
 # The INVARIANTS option is used in a number of source files to enable
 # extra sanity checking of internal structures.  This support is not
 # enabled by default because of the extra time it would take to check
 # for these conditions, which can only occur as a result of
 # programming errors.
 #
 options 	INVARIANTS
 
 #
 # The INVARIANT_SUPPORT option makes us compile in support for
 # verifying some of the internal structures.  It is a prerequisite for
 # 'INVARIANTS', as enabling 'INVARIANTS' will make these functions be
 # called.  The intent is that you can set 'INVARIANTS' for single
 # source files (by changing the source file or specifying it on the
 # command line) if you have 'INVARIANT_SUPPORT' enabled.
 #
 options 	INVARIANT_SUPPORT
 
 #
 # The DIAGNOSTIC option is used to enable extra debugging information
 # from some parts of the kernel.  As this makes everything more noisy,
 # it is disabled by default.
 #
 options 	DIAGNOSTIC
 
 #
 # PERFMON causes the driver for Pentium/Pentium Pro performance counters
 # to be compiled.  See perfmon(4) for more information.
 #
 options 	PERFMON
 
 
 #
 # This option let some drivers co-exist that can't co-exist in a running
 # system.  This is used to be able to compile all kernel code in one go for
 # quality assurance purposes (like this file, which the option takes it name
 # from.)
 #
 options 	COMPILING_LINT
 
 
 # XXX - this doesn't belong here.
 # Allow ordinary users to take the console - this is useful for X.
 options 	UCONSOLE
 
 # XXX - this doesn't belong here either
 options 	USERCONFIG		#boot -c editor
 options 	INTRO_USERCONFIG	#imply -c and show intro screen
 options 	VISUAL_USERCONFIG	#visual boot -c editor
 
 
 #####################################################################
 # NETWORKING OPTIONS
 
 #
 # Protocol families:
 #  Only the INET (Internet) family is officially supported in FreeBSD.
 #  Source code for the NS (Xerox Network Service) is provided for amusement
 #  value.
 #
 options 	INET			#Internet communications protocols
 options 	INET6			#IPv6 communications protocols
 options 	IPSEC			#IP security
 options 	IPSEC_ESP		#IP security (crypto; define w/ IPSEC)
 options 	IPSEC_DEBUG		#debug for IP security
 
 options 	IPX			#IPX/SPX communications protocols
 options 	IPXIP			#IPX in IP encapsulation (not available)
 options 	IPTUNNEL		#IP in IPX encapsulation (not available)
 
 options 	NCP			#NetWare Core protocol
 
 options 	NETATALK		#Appletalk communications protocols
 
 # These are currently broken but are shipped due to interest.
 #options 	NS			#Xerox NS protocols
 #options 	NSIP			#XNS over IP
 
 #
 # SMB/CIFS requester
 # NETSMB enables support for SMB protocol, it requires LIBMCHAIN and LIBICONV
 # options.
 # NETSMBCRYPTO enables support for encrypted passwords.
 options 	NETSMB			#SMB/CIFS requester
 options 	NETSMBCRYPTO		#encrypted password support for SMB
 
 # mchain library. It can be either loaded as KLD or compiled into kernel
 options 	LIBMCHAIN		#mbuf management library
 
 # netgraph(4). Enable the base netgraph code with the NETGRAPH option.
 # Individual node types can be enabled with the corresponding option
 # listed below; however, this is not strictly necessary as netgraph
 # will automatically load the corresponding KLD module if the node type
 # is not already compiled into the kernel. Each type below has a
 # corresponding man page, e.g., ng_async(8).
 options 	NETGRAPH		#netgraph(4) system
 options 	NETGRAPH_ASYNC
 options 	NETGRAPH_BPF
 options 	NETGRAPH_CISCO
 options 	NETGRAPH_ECHO
 options 	NETGRAPH_ETHER
 options 	NETGRAPH_FRAME_RELAY
 options 	NETGRAPH_HOLE
 options 	NETGRAPH_IFACE
 options 	NETGRAPH_KSOCKET
 options 	NETGRAPH_LMI
 # MPPC compression requires proprietary files (not included)
 #options 	NETGRAPH_MPPC_COMPRESSION
 options 	NETGRAPH_MPPC_ENCRYPTION
 options 	NETGRAPH_ONE2MANY
 options 	NETGRAPH_PPP
 options 	NETGRAPH_PPPOE
 options 	NETGRAPH_PPTPGRE
 options 	NETGRAPH_RFC1490
 options 	NETGRAPH_SOCKET
 options 	NETGRAPH_TEE
 options 	NETGRAPH_TTY
 options 	NETGRAPH_UI
 options 	NETGRAPH_VJC
 
 device		mn	# Munich32x/Falc54 Nx64kbit/sec cards.
 
 #
 # Network interfaces:
 #  The `loop' pseudo-device is MANDATORY when networking is enabled.
 #  The `ether' pseudo-device provides generic code to handle
 #  Ethernets; it is MANDATORY when a Ethernet device driver is
 #  configured or token-ring is enabled.
 #  The 'fddi' pseudo-device provides generic code to support FDDI.
 #  The `sppp' pseudo-device serves a similar role for certain types
 #  of synchronous PPP links (like `cx', `ar').
 #  The `sl' pseudo-device implements the Serial Line IP (SLIP) service.
 #  The `ppp' pseudo-device implements the Point-to-Point Protocol.
 #  The `bpf' pseudo-device enables the Berkeley Packet Filter.  Be
 #  aware of the legal and administrative consequences of enabling this
 #  option.  The number of devices determines the maximum number of
 #  simultaneous BPF clients programs runnable.
 #  The `disc' pseudo-device implements a minimal network interface,
 #  which throws away all packets sent and never receives any.  It is
 #  included for testing purposes.  This shows up as the 'ds' interface.
 #  The `tun' pseudo-device implements (user-)ppp and nos-tun
 #  The `gif' pseudo-device implements IPv6 over IP4 tunneling,
 #  IPv4 over IPv6 tunneling, IPv4 over IPv4 tunneling and
 #  IPv6 over IPv6 tunneling.
 #  The `faith' pseudo-device captures packets sent to it and diverts them
 #  to the IPv4/IPv6 translation daemon.
 #  The `stf' device implements 6to4 encapsulation.
 #  The `ef' pseudo-device provides support for multiple ethernet frame types
 #  specified via ETHER_* options. See ef(4) for details.
 #
 # The PPP_BSDCOMP option enables support for compress(1) style entire
 # packet compression, the PPP_DEFLATE is for zlib/gzip style compression.
 # PPP_FILTER enables code for filtering the ppp data stream and selecting
 # events for resetting the demand dial activity timer - requires bpf.
 # See pppd(8) for more details.
 #
 pseudo-device	ether			#Generic Ethernet
 pseudo-device	vlan	1		#VLAN support
 pseudo-device	token			#Generic TokenRing
 pseudo-device	fddi			#Generic FDDI
 pseudo-device	sppp			#Generic Synchronous PPP
 pseudo-device	loop			#Network loopback device
 pseudo-device	bpf			#Berkeley packet filter
 pseudo-device	disc			#Discard device (ds0, ds1, etc)
 pseudo-device	tun			#Tunnel driver (ppp(8), nos-tun(8))
 pseudo-device	sl	2		#Serial Line IP
 pseudo-device	ppp	2		#Point-to-point protocol
 options 	PPP_BSDCOMP		#PPP BSD-compress support
 options 	PPP_DEFLATE		#PPP zlib/deflate/gzip support
 options 	PPP_FILTER		#enable bpf filtering (needs bpf)
 
 pseudo-device	ef			# Multiple ethernet frames support
 options 	ETHER_II		# enable Ethernet_II frame
 options 	ETHER_8023		# enable Ethernet_802.3 (Novell) frame
 options 	ETHER_8022		# enable Ethernet_802.2 frame
 options 	ETHER_SNAP		# enable Ethernet_802.2/SNAP frame
 
 # for IPv6
 pseudo-device	gif			#IPv6 and IPv4 tunneling
 pseudo-device	faith	1		#for IPv6 and IPv4 translation
 pseudo-device	stf			#6to4 IPv6 over IPv4 encapsulation
 
 #
 # Internet family options:
 #
 # MROUTING enables the kernel multicast packet forwarder, which works
 # with mrouted(8).
 #
 # IPFIREWALL enables support for IP firewall construction, in
 # conjunction with the `ipfw' program.  IPFIREWALL_VERBOSE sends
 # logged packets to the system logger.  IPFIREWALL_VERBOSE_LIMIT
 # limits the number of times a matching entry can be logged.
 #
 # WARNING:  IPFIREWALL defaults to a policy of "deny ip from any to any"
 # and if you do not add other rules during startup to allow access,
 # YOU WILL LOCK YOURSELF OUT.  It is suggested that you set firewall_type=open
 # in /etc/rc.conf when first enabling this feature, then refining the
 # firewall rules in /etc/rc.firewall after you've tested that the new kernel
 # feature works properly.
 #
 # IPFIREWALL_DEFAULT_TO_ACCEPT causes the default rule (at boot) to
 # allow everything.  Use with care, if a cracker can crash your
 # firewall machine, they can get to your protected machines.  However,
 # if you are using it as an as-needed filter for specific problems as
 # they arise, then this may be for you.  Changing the default to 'allow'
 # means that you won't get stuck if the kernel and /sbin/ipfw binary get
 # out of sync.
 #
 # IPDIVERT enables the divert IP sockets, used by ``ipfw divert''
 #
 # IPSTEALTH enables code to support stealth forwarding (i.e., forwarding
 # packets without touching the ttl).  This can be useful to hide firewalls
 # from traceroute and similar tools.
 #
 # TCPDEBUG is undocumented.
 #
 options 	MROUTING		# Multicast routing
 options 	IPFIREWALL		#firewall
 options 	IPFIREWALL_VERBOSE	#enable logging to syslogd(8)
 options 	IPFIREWALL_FORWARD	#enable transparent proxy support
 options 	IPFIREWALL_VERBOSE_LIMIT=100	#limit verbosity
 options 	IPFIREWALL_DEFAULT_TO_ACCEPT	#allow everything by default
 options 	IPV6FIREWALL		#firewall for IPv6
 options 	IPV6FIREWALL_VERBOSE
 options 	IPV6FIREWALL_VERBOSE_LIMIT=100
 options 	IPV6FIREWALL_DEFAULT_TO_ACCEPT
 options 	IPDIVERT		#divert sockets
 options 	IPFILTER		#ipfilter support
 options 	IPFILTER_LOG		#ipfilter logging
 options		IPFILTER_DEFAULT_BLOCK	#block all packets by default
 options 	IPSTEALTH		#support for stealth forwarding
 options 	TCPDEBUG
 
 # RANDOM_IP_ID causes the ID field in IP packets to be randomized
 # instead of incremented by 1 with each packet generated.  This
 # option closes a minor information leak which allows remote
 # observers to determine the rate of packet generation on the
 # machine by watching the counter.
 options		RANDOM_IP_ID
 
 # Statically Link in accept filters
 options                ACCEPT_FILTER_DATA
 options                ACCEPT_FILTER_HTTP
 
 #
 # TCP_DROP_SYNFIN adds support for ignoring TCP packets with SYN+FIN. This
 # prevents nmap et al. from identifying the TCP/IP stack, but breaks support
 # for RFC1644 extensions and is not recommended for web servers.
 #
 options 	TCP_DROP_SYNFIN		#drop TCP packets with SYN+FIN
 
 # ICMP_BANDLIM enables icmp error response bandwidth limiting.   You
 # typically want this option as it will help protect the machine from
 # D.O.S. packet attacks.
 #
 options 	ICMP_BANDLIM
 
 # DUMMYNET enables the "dummynet" bandwidth limiter. You need
 # IPFIREWALL as well. See the dummynet(4) manpage for more info.
 # BRIDGE enables bridging between ethernet cards -- see bridge(4).
 # You can use IPFIREWALL and dummynet together with bridging.
 options 	DUMMYNET
 options 	BRIDGE
 
 #
 # ATM (HARP version) options
 #
 # ATM_CORE includes the base ATM functionality code.  This must be included
 #	for ATM support.
 #
 # ATM_IP includes support for running IP over ATM.
 #
 # At least one (and usually only one) of the following signalling managers
 # must be included (note that all signalling managers include PVC support):
 # ATM_SIGPVC includes support for the PVC-only signalling manager `sigpvc'.
 # ATM_SPANS includes support for the `spans' signalling manager, which runs
 #	the FORE Systems's proprietary SPANS signalling protocol.
 # ATM_UNI includes support for the `uni30' and `uni31' signalling managers,
 #	which run the ATM Forum UNI 3.x signalling protocols.
 #
 # The `hea' driver provides support for the Efficient Networks, Inc.
 # ENI-155p ATM PCI Adapter.
 #
 # The `hfa' driver provides support for the FORE Systems, Inc.
 # PCA-200E ATM PCI Adapter.
 #
 options 	ATM_CORE		#core ATM protocol family
 options 	ATM_IP			#IP over ATM support
 options 	ATM_SIGPVC		#SIGPVC signalling manager
 options 	ATM_SPANS		#SPANS signalling manager
 options 	ATM_UNI			#UNI signalling manager
 device		hea			#Efficient ENI-155p ATM PCI
 device		hfa			#FORE PCA-200E ATM PCI
 
 
 #####################################################################
 # FILESYSTEM OPTIONS
 
 #
 # Only the root, /usr, and /tmp filesystems need be statically
 # compiled; everything else will be automatically loaded at mount
 # time.  (Exception: the UFS family---FFS, and MFS --- cannot
 # currently be demand-loaded.)  Some people still prefer to statically
 # compile other filesystems as well.
 #
 # NB: The NULL, PORTAL, UMAP and UNION filesystems are known to be
 # buggy, and WILL panic your system if you attempt to do anything with
 # them.  They are included here as an incentive for some enterprising
 # soul to sit down and fix them.
 #
 
 # One of these is mandatory:
 options 	FFS			#Fast filesystem
 options 	MFS			#Memory File System
 options 	NFS			#Network File System
 
 # The rest are optional:
 #options 	NFS_NOSERVER		#Disable the NFS-server code.
 options 	CD9660			#ISO 9660 filesystem
 options 	FDESC			#File descriptor filesystem
 options 	KERNFS			#Kernel filesystem
 options 	MSDOSFS			#MS DOS File System
 options 	NTFS			#NT File System
 options 	NULLFS			#NULL filesystem
 options 	NWFS			#NetWare filesystem
 options 	PORTAL			#Portal filesystem
 options 	PROCFS			#Process filesystem
 options		SMBFS			#SMB/CIFS filesystem
 options 	UMAPFS			#UID map filesystem
 options 	UNION			#Union filesystem
 # The xFS_ROOT options REQUIRE the associated ``options xFS''
 options 	CD9660_ROOT		#CD-ROM usable as root device
 options 	FFS_ROOT		#FFS usable as root device
 options 	NFS_ROOT		#NFS usable as root device
 
 # Soft updates is technique for improving file system speed and
 # making abrupt shutdown less risky.
 options 	SOFTUPDATES
 
 # Directory hashing improves the speed of operations on very large
 # directories at the expense of some memory.
 options		UFS_DIRHASH
 
 # Make space in the kernel for a root filesystem on a md device.
 # Define to the number of kilobytes to reserve for the filesystem.
 options 	MD_ROOT_SIZE=10
 
 # Make the md device a potential root device, either with preloaded
 # images of type mfs_root or md_root.
 options 	MD_ROOT
 
 # Specify double the default maximum size for malloc(9)-backed md devices.
 options 	MD_NSECT=40000
 
 # Allow this many swap-devices.
 #
 # In order to manage swap, the system must reserve bitmap space that
 # scales with the largest mounted swap device multiplied by NSWAPDEV, 
 # irregardless of whether other swap devices exist or not.  So it
 # is not a good idea to make this value too large.
 options 	NSWAPDEV=5
 
 # Disk quotas are supported when this option is enabled.
 options 	QUOTA			#enable disk quotas
 
 # If you are running a machine just as a fileserver for PC and MAC
 # users, using SAMBA or Netatalk, you may consider setting this option
 # and keeping all those users' directories on a filesystem that is
 # mounted with the suiddir option. This gives new files the same
 # ownership as the directory (similar to group). It's a security hole
 # if you let these users run programs, so confine it to file-servers
 # (but it'll save you lots of headaches in those cases). Root owned
 # directories are exempt and X bits are cleared. The suid bit must be
 # set on the directory as well; see chmod(1) PC owners can't see/set
 # ownerships so they keep getting their toes trodden on. This saves
 # you all the support calls as the filesystem it's used on will act as
 # they expect: "It's my dir so it must be my file".
 #
 options 	SUIDDIR
 
 # NFS options:
 options 	NFS_MINATTRTIMO=3	# VREG attrib cache timeout in sec
 options 	NFS_MAXATTRTIMO=60
 options 	NFS_MINDIRATTRTIMO=30	# VDIR attrib cache timeout in sec
 options 	NFS_MAXDIRATTRTIMO=60
 options 	NFS_GATHERDELAY=10	# Default write gather delay (msec)
 options 	NFS_UIDHASHSIZ=29	# Tune the size of nfssvc_sock with this
 options 	NFS_WDELAYHASHSIZ=16	# and with this
 options 	NFS_MUIDHASHSIZ=63	# Tune the size of nfsmount with this
 options 	NFS_DEBUG		# Enable NFS Debugging
 
 # Coda stuff:
 options 	CODA			#CODA filesystem.
 pseudo-device	vcoda	4		#coda minicache <-> venus comm.
 
 #
 # Add support for the EXT2FS filesystem of Linux fame.  Be a bit
 # careful with this - the ext2fs code has a tendency to lag behind
 # changes and not be exercised very much, so mounting read/write could
 # be dangerous (and even mounting read only could result in panics.)
 #
 options 	EXT2FS
 
 # Use real implementations of the aio_* system calls.  There are numerous
 # stability and security issues in the current aio code that make it
 # unsuitable for inclusion on machines with untrusted local users.
 options 	VFS_AIO
 
 
 #####################################################################
 # POSIX P1003.1B
 
 # Real time extensions added in the 1993 Posix
 # P1003_1B: Infrastructure
 # _KPOSIX_PRIORITY_SCHEDULING: Build in _POSIX_PRIORITY_SCHEDULING
 # _KPOSIX_VERSION:             Version kernel is built for
 
 options 	P1003_1B
 options 	_KPOSIX_PRIORITY_SCHEDULING
 options 	_KPOSIX_VERSION=199309L
 
 
 #####################################################################
 # CLOCK OPTIONS
 
 # The granularity of operation is controlled by the kernel option HZ whose
 # default value (100) means a granularity of 10ms.  For an accurate simulation
 # of high data rates it might be necessary to reduce the timer granularity to
 # 1ms or less.  Consider, however, that some interfaces using programmed I/O
 # may require a considerable time to output packets.  So, reducing the
 # granularity too much might actually cause ticks to be missed thus reducing
 # the accuracy of operation.
 
 options 	HZ=100
 
 # Other clock options
 
 options 	CLK_CALIBRATION_LOOP
 options 	CLK_USE_I8254_CALIBRATION
 options 	CLK_USE_TSC_CALIBRATION
 
 
 #####################################################################
 # SCSI DEVICES
 
 # SCSI DEVICE CONFIGURATION
 
 # The SCSI subsystem consists of the `base' SCSI code, a number of
 # high-level SCSI device `type' drivers, and the low-level host-adapter
 # device drivers.  The host adapters are listed in the ISA and PCI
 # device configuration sections below.
 #
 # Beginning with FreeBSD 2.0.5 you can wire down your SCSI devices so
 # that a given bus, target, and LUN always come on line as the same
 # device unit.  In earlier versions the unit numbers were assigned
 # in the order that the devices were probed on the SCSI bus.  This
 # means that if you removed a disk drive, you may have had to rewrite
 # your /etc/fstab file, and also that you had to be careful when adding
 # a new disk as it may have been probed earlier and moved your device
 # configuration around.
 
 # This old behavior is maintained as the default behavior.  The unit
 # assignment begins with the first non-wired down unit for a device
 # type.  For example, if you wire a disk as "da3" then the first
 # non-wired disk will be assigned da4.
 
 # The syntax for wiring down devices is:
 
 # device	scbus0 at ahc0		# Single bus device
 # device	scbus1 at ahc1 bus 0	# Single bus device
 # device	scbus3 at ahc2 bus 0	# Twin bus device
 # device	scbus2 at ahc2 bus 1	# Twin bus device
 # device 	da0 at scbus0 target 0 unit 0
 # device	da1 at scbus3 target 1
 # device	da2 at scbus2 target 3
 # device	sa1 at scbus1 target 6
 # device	cd
 
 # "units" (SCSI logical unit number) that are not specified are
 # treated as if specified as LUN 0.
 
 # All SCSI devices allocate as many units as are required.
 
 # The "unknown" device (uk? in pre-2.0.5) is now part of the base SCSI
 # configuration and doesn't have to be explicitly configured.
 
 device		scbus			#base SCSI code
 device		ch			#SCSI media changers
 device		da			#SCSI direct access devices (aka disks)
 device		sa			#SCSI tapes
 device		cd			#SCSI CD-ROMs
 device		pass			#CAM passthrough driver
 device		pt			#SCSI processor type
 device		ses			#SCSI SES/SAF-TE driver
 
 # CAM OPTIONS:
 # debugging options:
 # -- NOTE --  If you specify one of the bus/target/lun options, you must
 #             specify them all!
 # CAMDEBUG: When defined enables debugging macros
 # CAM_DEBUG_BUS:  Debug the given bus.  Use -1 to debug all busses.
 # CAM_DEBUG_TARGET:  Debug the given target.  Use -1 to debug all targets.
 # CAM_DEBUG_LUN:  Debug the given lun.  Use -1 to debug all luns.
 # CAM_DEBUG_FLAGS:  OR together CAM_DEBUG_INFO, CAM_DEBUG_TRACE,
 #                   CAM_DEBUG_SUBTRACE, and CAM_DEBUG_CDB
 #
 # CAM_MAX_HIGHPOWER: Maximum number of concurrent high power (start unit) cmds
 # SCSI_NO_SENSE_STRINGS: When defined disables sense descriptions
 # SCSI_NO_OP_STRINGS: When defined disables opcode descriptions
 # SCSI_DELAY: The number of MILLISECONDS to freeze the SIM (scsi adapter)
 #             queue after a bus reset, and the number of milliseconds to
 #             freeze the device queue after a bus device reset.
 options 	CAMDEBUG
 options 	CAM_DEBUG_BUS=-1
 options 	CAM_DEBUG_TARGET=-1
 options 	CAM_DEBUG_LUN=-1
 options 	CAM_DEBUG_FLAGS="CAM_DEBUG_INFO|CAM_DEBUG_TRACE|CAM_DEBUG_CDB"
 options 	CAM_MAX_HIGHPOWER=4
 options 	SCSI_NO_SENSE_STRINGS
 options 	SCSI_NO_OP_STRINGS
 options 	SCSI_DELAY=8000	# Be pessimistic about Joe SCSI device
 
 # Options for the CAM CDROM driver:
 # CHANGER_MIN_BUSY_SECONDS: Guaranteed minimum time quantum for a changer LUN
 # CHANGER_MAX_BUSY_SECONDS: Maximum time quantum per changer LUN, only
 #                           enforced if there is I/O waiting for another LUN
 # The compiled in defaults for these variables are 2 and 10 seconds,
 # respectively.
 #
 # These can also be changed on the fly with the following sysctl variables:
 # kern.cam.cd.changer.min_busy_seconds
 # kern.cam.cd.changer.max_busy_seconds
 #
 options 	CHANGER_MIN_BUSY_SECONDS=2
 options 	CHANGER_MAX_BUSY_SECONDS=10
 
 # Options for the CAM sequential access driver:
 # SA_IO_TIMEOUT: Timeout for read/write/wfm  operations, in minutes
 # SA_SPACE_TIMEOUT: Timeout for space operations, in minutes
 # SA_REWIND_TIMEOUT: Timeout for rewind operations, in minutes
 # SA_ERASE_TIMEOUT: Timeout for erase operations, in minutes
 # SA_1FM_AT_EOD: Default to model which only has a default one filemark at EOT.
 options 	SA_IO_TIMEOUT="(4)"
 options 	SA_SPACE_TIMEOUT="(60)"
 options 	SA_REWIND_TIMEOUT="(2*60)"
 options 	SA_ERASE_TIMEOUT="(4*60)"
 options 	SA_1FM_AT_EOD
 
 # Optional timeout for the CAM processor target (pt) device
 # This is specified in seconds.  The default is 60 seconds.
 options 	SCSI_PT_DEFAULT_TIMEOUT="60"
 
 # Optional enable of doing SES passthrough on other devices (e.g., disks)
 #
 # Normally disabled because a lot of newer SCSI disks report themselves
 # as having SES capabilities, but this can then clot up attempts to build
 # build a topology with the SES device that's on the box these drives
 # are in....
 options		SES_ENABLE_PASSTHROUGH
 
 
 #####################################################################
 # MISCELLANEOUS DEVICES AND OPTIONS
 
 # The `pty' device usually turns out to be ``effectively mandatory'',
 # as it is required for `telnetd', `rlogind', `screen', `emacs', and
 # `xterm', among others.
 
 pseudo-device	pty		#Pseudo ttys
 pseudo-device	speaker		#Play IBM BASIC-style noises out your speaker
 pseudo-device	gzip		#Exec gzipped a.out's
 pseudo-device	vn		#Vnode driver (turns a file into a device)
 pseudo-device	md		#Memory/malloc disk
 pseudo-device	snp	3	#Snoop device - to look at pty/vty/etc..
 pseudo-device	ccd	4	#Concatenated disk driver
 
 # Configuring Vinum into the kernel is not necessary, since the kld
 # module gets started automatically when vinum(8) starts.  This
 # device is also untested.  Use at your own risk.
 #
 # The option VINUMDEBUG must match the value set in CFLAGS
 # in src/sbin/vinum/Makefile.  Failure to do so will result in
 # the following message from vinum(8):
 #
 # Can't get vinum config: Invalid argument
 #
 # see vinum(4) for more reasons not to use these options.
 pseudo-device	vinum		#Vinum concat/mirror/raid driver
 options 	VINUMDEBUG	#enable Vinum debugging hooks
 
 # Kernel side iconv library
 options 	LIBICONV
 
 # Size of the kernel message buffer.  Should be N * pagesize.
 options 	MSGBUF_SIZE=40960
 
 
 #####################################################################
 # HARDWARE DEVICE CONFIGURATION
 
 # ISA and EISA devices:
 # EISA support is available for some device, so they can be auto-probed.
 # MicroChannel (MCA) support is available for some devices.
 
 #
 # Mandatory ISA devices: isa, npx
 #
 device		isa
 
 #
 # Options for `isa':
 #
 # AUTO_EOI_1 enables the `automatic EOI' feature for the master 8259A
 # interrupt controller.  This saves about 0.7-1.25 usec for each interrupt.
 # This option breaks suspend/resume on some portables.
 #
 # AUTO_EOI_2 enables the `automatic EOI' feature for the slave 8259A
 # interrupt controller.  This saves about 0.7-1.25 usec for each interrupt.
 # Automatic EOI is documented not to work for for the slave with the
 # original i8259A, but it works for some clones and some integrated
 # versions.
 #
 # MAXMEM specifies the amount of RAM on the machine; if this is not
 # specified, FreeBSD will first read the amount of memory from the CMOS
 # RAM, so the amount of memory will initially be limited to 64MB or 16MB
 # depending on the BIOS.  If the BIOS reports 64MB, a memory probe will
 # then attempt to detect the installed amount of RAM.  If this probe
 # fails to detect >64MB RAM you will have to use the MAXMEM option.
 # The amount is in kilobytes, so for a machine with 128MB of RAM, it would
 # be 131072 (128 * 1024).
 #
 # BROKEN_KEYBOARD_RESET disables the use of the keyboard controller to
 # reset the CPU for reboot.  This is needed on some systems with broken
 # keyboard controllers.
 #
 # PAS_JOYSTICK_ENABLE enables the gameport on the ProAudio Spectrum
 
 options 	AUTO_EOI_1
 #options 	AUTO_EOI_2
 options 	MAXMEM="(128*1024)"
 #options 	BROKEN_KEYBOARD_RESET
 #options 	PAS_JOYSTICK_ENABLE
 
 # Enable support for the kernel PLL to use an external PPS signal,
 # under supervision of [x]ntpd(8)
 # More info in ntpd documentation: http://www.eecis.udel.edu/~ntp
 
 options 	PPS_SYNC
 
 # If you see the "calcru: negative time of %ld usec for pid %d (%s)\n"
 # message you probably have some broken sw/hw which disables interrupts
 # for too long.  You can make the system more resistant to this by
 # choosing a high value for NTIMECOUNTER.  The default is 5, there
 # is no upper limit but more than a couple of hundred are not productive.
 # A better strategy may be to sysctl -w kern.timecounter.method=1
 
 options 	NTIMECOUNTER=20
 
 # The keyboard controller; it controls the keyboard and the PS/2 mouse.
 device		atkbdc0	at isa? port IO_KBD
 
 # The AT keyboard
 device		atkbd0	at atkbdc? irq 1
 
 # Options for atkbd:
 options 	ATKBD_DFLT_KEYMAP	# specify the built-in keymap
 makeoptions	ATKBD_DFLT_KEYMAP="jp.106"
 
 # These options are valid for other keyboard drivers as well.
 options 	KBD_DISABLE_KEYMAP_LOAD	# refuse to load a keymap
 options 	KBD_INSTALL_CDEV	# install a CDEV entry in /dev
 
 # `flags' for atkbd:
 #       0x01    Force detection of keyboard, else we always assume a keyboard
 #       0x02    Don't reset keyboard, useful for some newer ThinkPads
 #	0x03	Force detection and avoid reset, might help with certain
 #		dockingstations
 #       0x04    Old-style (XT) keyboard support, useful for older ThinkPads
 
 # PS/2 mouse
 device		psm0	at atkbdc? irq 12
 
 # Options for psm:
 options 	PSM_HOOKRESUME		#hook the system resume event, useful
 					#for some laptops
 options 	PSM_RESETAFTERSUSPEND	#reset the device at the resume event
 
 # The video card driver.
 device		vga0	at isa?
 
 # Options for vga:
 # Try the following option if the mouse pointer is not drawn correctly
 # or font does not seem to be loaded properly.  May cause flicker on
 # some systems.
 options 	VGA_ALT_SEQACCESS
 
 # If you can dispense with some vga driver features, you may want to
 # use the following options to save some memory.
 options 	VGA_NO_FONT_LOADING	# don't save/load font
 options 	VGA_NO_MODE_CHANGE	# don't change video modes
 
 # Older video cards may require this option for proper operation.
 options 	VGA_SLOW_IOACCESS	# do byte-wide i/o's to TS and GDC regs
 
 # The following option probably won't work with the LCD displays.
 options 	VGA_WIDTH90		# support 90 column modes
 
 # To include support for VESA video modes
 options 	VESA
 
 # Splash screen at start up!  Screen savers require this too.
 pseudo-device	splash
 
 # The pcvt console driver (vt220 compatible).
 device		vt0	at isa?
 options 	XSERVER			# support for running an X server on vt
 options 	FAT_CURSOR		# start with block cursor
 # This PCVT option is for keyboards such as those used on IBM ThinkPad laptops
 options 	PCVT_SCANSET=2 		# IBM keyboards are non-std
 # Other PCVT options are documented in pcvt(4).
 options 	PCVT_24LINESDEF
 options 	PCVT_CTRL_ALT_DEL
 options 	PCVT_EMU_MOUSE
 options 	PCVT_FREEBSD=211
 options 	PCVT_META_ESC
 options 	PCVT_NSCREENS=9
 options 	PCVT_PRETTYSCRNS
 options 	PCVT_SCREENSAVER
 options 	PCVT_USEKBDSEC
 options 	PCVT_VT220KEYB
 
 # The syscons console driver (sco color console compatible).
 device		sc0	at isa?
 options 	MAXCONS=16		# number of virtual consoles
 options 	SC_ALT_MOUSE_IMAGE	# simplified mouse cursor in text mode
 options 	SC_DFLT_FONT		# compile font in
 makeoptions	SC_DFLT_FONT=cp850
 options 	SC_DISABLE_DDBKEY	# disable `debug' key
 options 	SC_DISABLE_REBOOT	# disable reboot key sequence
 options 	SC_HISTORY_SIZE=200	# number of history buffer lines
 options 	SC_MOUSE_CHAR=0x3	# char code for text mode mouse cursor
 options 	SC_PIXEL_MODE		# add support for the raster text mode
 
 # The following options will let you change the default colors of syscons.
 options 	SC_NORM_ATTR="(FG_GREEN|BG_BLACK)"
 options 	SC_NORM_REV_ATTR="(FG_YELLOW|BG_GREEN)"
 options 	SC_KERNEL_CONS_ATTR="(FG_RED|BG_BLACK)"
 options 	SC_KERNEL_CONS_REV_ATTR="(FG_BLACK|BG_RED)"
 
 # If you have a two button mouse, you may want to add the following option
 # to use the right button of the mouse to paste text.
 options 	SC_TWOBUTTON_MOUSE
 
 # You can selectively disable features in syscons.
 options 	SC_NO_CUTPASTE
 options 	SC_NO_FONT_LOADING
 options 	SC_NO_HISTORY
 options 	SC_NO_SYSMOUSE
 
 #
 # The Numeric Processing eXtension driver.  In addition to this, you
 # may configure a math emulator (see above).  If your machine has a
 # hardware FPU and the kernel configuration includes the npx device
 # *and* a math emulator compiled into the kernel, the hardware FPU
 # will be used, unless it is found to be broken or unless "flags" to
 # npx0 includes "0x08", which requests preference for the emulator.
 device		npx0	at nexus? port IO_NPX flags 0x0 irq 13
 
 #
 # `flags' for npx0:
 #	0x01	don't use the npx registers to optimize bcopy.
 #	0x02	don't use the npx registers to optimize bzero.
 #	0x04	don't use the npx registers to optimize copyin or copyout.
 #	0x08	use emulator even if hardware FPU is available.
 # The npx registers are normally used to optimize copying and zeroing when
 # all of the following conditions are satisfied:
 #	I586_CPU is an option
 #	the cpu is an i586 (perhaps not a Pentium)
 #	the probe for npx0 succeeds
 #	INT 16 exception handling works.
 # Then copying and zeroing using the npx registers is normally 30-100% faster.
 # The flags can be used to control cases where it doesn't work or is slower.
 # Setting them at boot time using userconfig works right (the optimizations
 # are not used until later in the bootstrap when npx0 is attached).
 # Flag 0x08 automatically disables the i586 optimized routines.
 #
 
 #
 # Optional ISA and EISA devices:
 #
 
 #
 # SCSI host adapters: `aha', `aic', `bt'
 #
 # adv: All Narrow SCSI bus AdvanSys controllers.
 # adw: Second Generation AdvanSys controllers including the ADV940UW.
 # aha: Adaptec 154x
 # ahc: Adaptec 274x/284x/294x
 # aic: Adaptec 152x
 # bt: Most Buslogic controllers
 # ncv: NCR 53C500 based SCSI host adapters.
 # nsp: Workbit Ninja SCSI-3 based PC Card SCSI host adapters.
 # stg: TMC 18C30, 18C50 based ISA/PC Card SCSI host adapters.
 #
 # Note that the order is important in order for Buslogic cards to be
 # probed correctly.
 #
 
 device		bt0	at isa? port IO_BT0
 device		adv0	at isa?
 device		adw
 device		aha0	at isa?
 device		aic0	at isa?
 device		ncv
 device		nsp
 device		stg0	at isa? port 0x140 irq 11
 
 #
 # Adaptec FSA RAID controllers, including integrated DELL controller,
 # the Dell PERC 2/QC and the HP NetRAID-4M
 #
 # AAC_COMPAT_LINUX	Include code to support Linux-binary management
 #			utilities (requires Linux compatibility
 #			support).
 #
 device		aac
 
 #
 # Compaq Smart RAID, Mylex DAC960 and AMI MegaRAID controllers.  Only
 # one entry is needed; the code will find and configure all supported
 # controllers.
 #
 device		ida		# Compaq Smart RAID
 device		mlx		# Mylex DAC960
 device		amr		# AMI MegaRAID
 
 #
 # 3ware ATA RAID
 #
 device		twe		# 3ware ATA RAID
 
 #
 # The 'ATA' driver supports all ATA and ATAPI devices.
 # It can reuse the majors of wd.c for booting purposes.
 # You only need one "device ata" for it to find all
 # PCI ATA/ATAPI devices on modern machines.
 device		ata
 device		atadisk		# ATA disk drives
 device		atapicd		# ATAPI CDROM drives
 device		atapifd		# ATAPI floppy drives
 device		atapist		# ATAPI tape drives
 
 #The following options are valid on the ATA driver:
 #
 # ATA_STATIC_ID:	controller numbering is static (like the old driver)
 #			else the device numbers are dynamically allocated.
 options 	ATA_STATIC_ID
 
 #
 # For older non-PCI systems, these are the lines to use:
 #device		ata0	at isa? port IO_WD1 irq 14
 #device		ata1	at isa? port IO_WD2 irq 15
 
 #
 # ST-506, ESDI, and IDE hard disks: `wdc' and `wd'
 #
 # The flags fields are used to enable the multi-sector I/O and
 # the 32BIT I/O modes.  The flags may be used in either the controller
 # definition or in the individual disk definitions.  The controller
 # definition is supported for the boot configuration stuff.
 #
 # Each drive has a 16 bit flags value defined:
 #	The low 8 bits are the maximum value for the multi-sector I/O,
 #	where 0xff defaults to the maximum that the drive can handle.
 #	The high bit of the 16 bit flags (0x8000) allows probing for
 #	32 bit transfers.  Bit 14 (0x4000) enables a hack to wake
 #	up powered-down laptop drives.  Bit 13 (0x2000) allows
 #	probing for PCI IDE DMA controllers, such as Intel's PIIX
 #	south bridges. Bit 12 (0x1000) sets LBA mode instead of the
 #	default CHS mode for accessing the drive. See the wd.4 man page.
 #
 # The flags field for the drives can be specified in the controller
 # specification with the low 16 bits for drive 0, and the high 16 bits
 # for drive 1.
 # e.g.:
 #device		wdc0	at isa? port IO_WD1 irq 14 flags 0x00ff8004
 #
 # specifies that drive 0 will be allowed to probe for 32 bit transfers and
 # a maximum multi-sector transfer of 4 sectors, and drive 1 will not be
 # allowed to probe for 32 bit transfers, but will allow multi-sector
 # transfers up to the maximum that the drive supports.
 #
 # If you are using a PCI controller that is not running in compatibility
 # mode (for example, it is a 2nd IDE PCI interface), then use config line(s)
 # such as:
 #
 #device		wdc2	at isa? port 0 flags 0xa0ffa0ff
 #device		wd4	at wdc2 drive 0
 #device		wd5	at wdc2 drive 1
 #
 #device		wdc3	at isa? port 0 flags 0xa0ffa0ff
 #device		wd6	at wdc3 drive 0
 #device		wd7	at wdc3 drive 1
 #
 # Note that the above config would be useful for a Promise card, when used
 # on a MB that already has a PIIX controller.  Note the bogus irq and port
 # entries.  These are automatically filled in by the IDE/PCI support.
 #
 # This driver must be commented out because it is mutually exclusive with
 # the ata(4) driver.
 #
 device		wdc0	at isa? port IO_WD1 irq 14
 device		wd0	at wdc0 drive 0
 device		wd1	at wdc0 drive 1
 device		wdc1	at isa? port IO_WD2 irq 15
 device		wd2	at wdc1 drive 0
 device		wd3	at wdc1 drive 1
 
 #
 # This option allow you to override the default probe time for IDE
 # devices, to get a faster probe.  Setting this below 10000 violate
 # the IDE specs, but may still work for you (it will work for most
 # people).
 #
 options 	IDE_DELAY=8000	# Be optimistic about Joe IDE device
 
 # IDE CD-ROM & CD-R/RW  driver - requires wdc controller
 device		wcd
 
 # IDE floppy driver - requires wdc controller
 device		wfd
 
 # IDE tape driver - requires wdc controller
 device		wst
 
 
 #
 # Standard floppy disk controllers: `fdc' and `fd'
 #
 device		fdc0	at isa? port IO_FD1 irq 6 drq 2
 #
 # FDC_DEBUG enables floppy debugging.  Since the debug output is huge, you
 # gotta turn it actually on by setting the variable fd_debug with DDB,
 # however.
 options 	FDC_DEBUG
 
 device		fd0	at fdc0 drive 0
 device		fd1	at fdc0 drive 1
 
 # M-systems DiskOnchip products see src/sys/contrib/dev/fla/README
 device		fla0	at isa?
 
 #
 # Other standard PC hardware: `mse', `sio', etc.
 #
 # mse: Logitech and ATI InPort bus mouse ports
 # sio: serial ports (see sio(4))
 
 device		mse0	at isa? port 0x23c irq 5
 
 device		sio0	at isa? port IO_COM1 flags 0x10 irq 4
 
 #
 # `flags' for serial drivers that support consoles (only for sio now):
 #	0x10	enable console support for this unit.  The other console flags
 #		are ignored unless this is set.  Enabling console support does
 #		not make the unit the preferred console - boot with -h or set
 #		the 0x20 flag for that.  Currently, at most one unit can have
 #		console support; the first one (in config file order) with
 #		this flag set is preferred.  Setting this flag for sio0 gives
 #		the old behaviour.
 #	0x20	force this unit to be the console (unless there is another
 #		higher priority console).  This replaces the COMCONSOLE option.
 #	0x40	reserve this unit for low level console operations.  Do not
 #		access the device in any normal way.
 #	0x80	use this port for serial line gdb support in ddb.
 #
 # PnP `flags' (set via userconfig using pnp x flags y)
 #	0x1	disable probing of this device.  Used to prevent your modem
 #		from being attached as a PnP modem.
 #
 
 # Options for serial drivers that support consoles (only for sio now):
 options 	BREAK_TO_DEBUGGER	#a BREAK on a comconsole goes to
 					#DDB, if available.
 options 	CONSPEED=115200		# speed for serial console
 					# (default 9600)
 
 # Solaris implements a new BREAK which is initiated by a character
 # sequence CR ~ ^b which is similar to a familiar pattern used on
 # Sun servers by the Remote Console.
 options 	ALT_BREAK_TO_DEBUGGER
 
 # Options for sio:
 options 	COM_ESP			#code for Hayes ESP
 options 	COM_MULTIPORT		#code for some cards with shared IRQs
 
 # Other flags for sio that aren't documented in the man page.
 #	0x20000	enable hardware RTS/CTS and larger FIFOs.  Only works for
 #		ST16650A-compatible UARTs.
 
 #
 # Network interfaces: `cx', `ed', `el', `ep', `ie', `is', `le', `lnc'
 #
 # ar: Arnet SYNC/570i hdlc sync 2/4 port V.35/X.21 serial driver (requires sppp)
 # cs: IBM Etherjet and other Crystal Semi CS89x0-based adapters
 # cx: Cronyx/Sigma multiport sync/async (with Cisco or PPP framing)
 # ed: Western Digital and SMC 80xx; Novell NE1000 and NE2000; 3Com 3C503
 # el: 3Com 3C501 (slow!)
 # ep: 3Com 3C509
 # ex: Intel EtherExpress Pro/10 and other i82595-based adapters
 # fe: Fujitsu MB86960A/MB86965A Ethernet
 # ie: AT&T StarLAN 10 and EN100; 3Com 3C507; unknown NI5210; Intel EtherExpress
 # le: Digital Equipment EtherWorks 2 and EtherWorks 3 (DEPCA, DE100,
 #     DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422)
 # lnc: Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 & Am79C960)
 # rdp: RealTek RTL 8002-based pocket ethernet adapters
 # sbni: Granch SBNI12-xx adapters
 # sr: RISCom/N2 hdlc sync 1/2 port V.35/X.21 serial driver (requires sppp)
 # wl: Lucent Wavelan (ISA card only).
 # awi: IEEE 802.11b PRISM I cards.
 # wi: Lucent WaveLAN/IEEE 802.11 PCMCIA adapters. Note: this supports both
 #     the PCMCIA and ISA cards: the ISA card is really a PCMCIA to ISA
 #     bridge with a PCMCIA adapter plugged into it.
 # an: Aironet 4500/4800 802.11 wireless adapters. Supports the PCMCIA,
 #     PCI and ISA varieties.
 # xe: Xircom/Intel EtherExpress Pro100/16 PC Card ethernet controller.
 # ray: Raytheon Raylink 802.11 wireless NICs, OEM as Webgear Aviator 2.4GHz
 # oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133
 #       (no options needed)
 #
 device ar0 at isa? port 0x300 irq 10 iomem 0xd0000
 device cs0 at isa? port 0x300
 device cx0 at isa? port 0x240 irq 15 drq 7
 device ed0 at isa? port 0x280 irq 5 iomem 0xd8000
 device el0 at isa? port 0x300 irq 9
 device ep
 device ex
 device fe0 at isa? port 0x300
 device ie0 at isa? port 0x300 irq 5 iomem 0xd0000
 device ie1 at isa? port 0x360 irq 7 iomem 0xd0000
 device le0 at isa? port 0x300 irq 5 iomem 0xd0000
 device lnc0 at isa? port 0x280 irq 10 drq 0
 device rdp0 at isa? port 0x378 irq 7 flags 2
 device sbni0 at isa? port 0x210 irq 5 flags 0xefdead
 device sr0 at isa? port 0x300 irq 5 iomem 0xd0000
 device sn0 at isa? port 0x300 irq 10
 device awi
 device wi
 device an
 options 	WLCACHE		# enables the signal-strength cache
 options 	WLDEBUG		# enables verbose debugging output
 device wl0 at isa? port 0x300
 device xe
 device ray
 
 device oltr0 at isa?
 
 #
 # ATM related options
 #
 # The `en' device provides support for Efficient Networks (ENI)
 # ENI-155 PCI midway cards, and the Adaptec 155Mbps PCI ATM cards (ANA-59x0).
 #
 # atm pseudo-device provides generic atm functions and is required for
 # atm devices.
 # NATM enables the netnatm protocol family that can be used to
 # bypass TCP/IP.
 #
 # the current driver supports only PVC operations (no atm-arp, no multicast).
 # for more details, please read the original documents at
 # http://www.ccrc.wustl.edu/pub/chuck/tech/bsdatm/bsdatm.html
 #
 pseudo-device	atm
 device		en
 options 	NATM			#native ATM
 
 #
 # Audio drivers: `snd', `sb', `pas', `gus', `pca'
 #
 # snd: Voxware sound support code
 # sb: SoundBlaster PCM - SoundBlaster, SB Pro, SB16, ProAudioSpectrum
 # sbxvi: SoundBlaster 16
 # sbmidi: SoundBlaster 16 MIDI interface
 # pas: ProAudioSpectrum PCM and MIDI
 # gus: Gravis Ultrasound - Ultrasound, Ultrasound 16, Ultrasound MAX
 # gusxvi: Gravis Ultrasound 16-bit PCM	(do not use)
 # mss: Microsoft Sound System
 # css: Crystal Sound System (CSS 423x PnP)
 # sscape: Ensoniq Soundscape MIDI interface
 # sscape_mss: Ensoniq Soundscape PCM (requires sscape)
 # opl: Yamaha OPL-2 and OPL-3 FM - SB, SB Pro, SB 16, ProAudioSpectrum
 # uart: stand-alone 6850 UART for MIDI
 # mpu: Roland MPU-401 stand-alone card
 #
 # Note: It has been reported that ISA DMA with the SoundBlaster will
 # lock up the machine (PR docs/5358).  If this happens to you,
 # turning off USWC write posting in your machine's BIOS may fix
 # the problem.
 #
 # Beware!  The addresses specified below are also hard-coded in
 # src/sys/i386/isa/sound/sound_config.h.  If you change the values here, you
 # must also change the values in the include file.
 #
 # pcm: PCM audio through various sound cards.
 #
 # This has support for a large number of new audio cards, based on
 # CS423x, OPTi931, Yamaha OPL-SAx, and also for SB16, GusPnP.
 # For more information about this driver and supported cards,
 # see the pcm.4 man page.
 #
 # The flags of the device tells the device a bit more info about the
 # device that normally is obtained through the PnP interface.
 #	bit  2..0   secondary DMA channel;
 #	bit  4      set if the board uses two dma channels;
 #	bit 15..8   board type, overrides autodetection; leave it
 #		    zero if don't know what to put in (and you don't,
 #		    since this is unsupported at the moment...).
 #
 # This driver will use the new PnP code if it's available.
 #
 # pca: PCM audio through your PC speaker
 #
 # If you have a GUS-MAX card and want to use the CS4231 codec on the
 # card the drqs for the gus max must be 8 bit (1, 2, or 3).
 #
 # If you would like to use the full duplex option on the gus, then define
 # flags to be the ``read dma channel''.
 #
 # options BROKEN_BUS_CLOCK	#PAS-16 isn't working and OPTI chipset
 # options SYMPHONY_PAS		#PAS-16 isn't working and SYMPHONY chipset
 # options EXCLUDE_SBPRO		#PAS-16
 # options SBC_IRQ=5		#PAS-16. Must match irq on sb0 line.
 # PAS16: The order of the pas0/sb0/opl0 is important since the
 #	sb emulation is enabled in the pas-16 attach.
 #
 # To override the GUS defaults use:
 # options GUS_DMA2
 # options GUS_DMA
 # options GUS_IRQ
 #
 # The src/sys/i386/isa/sound/sound.doc has more information.
 
 # Controls all "VOXWARE" driver sound devices.  See Luigi's driver
 # below for an alternate which may work better for some cards.
 #
 #device		snd
 #device pas0	at isa? port 0x388 irq 10 drq 6
 #device sb0	at isa? port 0x220 irq 5 drq 1
 #device sbxvi0	at isa? drq 5
 #device sbmidi0	at isa? port 0x330
 #device awe0	at isa? port 0x620
 #device gus0	at isa? port 0x220 irq 12 drq 1
 ##device gus0	at isa? port 0x220 irq 12 drq 1 flags 0x3
 #device mss0	at isa? port 0x530 irq 10 drq 1
 #device css0	at isa? port 0x534 irq 5 drq 1 flags 0x08
 #device sscape0	at isa? port 0x330 irq 9 drq 0
 #device trix0	at isa? port 0x330 irq 6 drq 0
 #device sscape_mss0 at isa? port 0x534 irq 5 drq 1
 #device opl0	at isa? port 0x388
 #device mpu0	at isa? port 0x330 irq 6 drq 0
 #device uart0	at isa? port 0x330 irq 5
 
 # The newpcm driver (use INSTEAD of snd0 and all VOXWARE drivers!).
 # Note that motherboard sound devices may require options PNPBIOS.
 #
 # Supported cards include:
 # Creative SoundBlaster ISA PnP/non-PnP
 # Supports ESS and Avance ISA chips as well.
 # Gravis UltraSound ISA PnP/non-PnP
 # Crystal Semiconductor CS461x/428x PCI
 # Neomagic 256AV (ac97)
 # Most of the more common ISA/PnP sb/mss/ess compatable cards.
 
 # For non-pnp sound cards with no bridge drivers only:
 device		pcm0 at isa? irq 10 drq 1 flags 0x0
 #
 # For PnP/PCI sound cards
 device		pcm
 
 # The bridge drivers for sound cards.  These can be seperately configured
 # for providing services to the likes of new-midi (not in the tree yet).
 # When used with 'device pcm' they also provide pcm sound services.
 #
 # sbc:  Creative SoundBlaster ISA PnP/non-PnP
 #	Supports ESS and Avance ISA chips as well.
 # gusc: Gravis UltraSound ISA PnP/non-PnP
 # csa:  Crystal Semiconductor CS461x/428x PCI
 
 # For non-PnP cards:
 device		sbc0	at isa? port 0x220 irq 5 drq 1 flags 0x15
 device		gusc0	at isa? port 0x220 irq 5 drq 1 flags 0x13
 
 # Not controlled by `snd'
 device		pca0 at isa? port IO_TIMER1
 
 #
 # Miscellaneous hardware:
 #
 # mcd: Mitsumi CD-ROM using proprietary (non-ATAPI) interface
 # scd: Sony CD-ROM using proprietary (non-ATAPI) interface
 # matcd: Matsushita/Panasonic CD-ROM using proprietary (non-ATAPI) interface
 # wt: Wangtek and Archive QIC-02/QIC-36 tape drives
 # ctx: Cortex-I frame grabber
 # apm: Laptop Advanced Power Management (experimental)
 # spigot: The Creative Labs Video Spigot video-acquisition board
 # meteor: Matrox Meteor video capture board
 # bktr: Brooktree bt848/848a/849a/878/879 video capture and TV Tuner board
 # cy: Cyclades serial driver
 # dgb: Digiboard PC/Xi and PC/Xe series driver (ALPHA QUALITY!)
 # dgm: Digiboard PC/Xem driver
 # gp:  National Instruments AT-GPIB and AT-GPIB/TNT board
 # asc: GI1904-based hand scanners, e.g. the Trust Amiscan Grey
 # gsc: Genius GS-4500 hand scanner.
 # joy: joystick
 # labpc: National Instrument's Lab-PC and Lab-PC+
 # rc: RISCom/8 multiport card
 # rp: Comtrol Rocketport(ISA) - single card
 # tw: TW-523 power line interface for use with X-10 home control products
 # si: Specialix SI/XIO 4-32 port terminal multiplexor
 # stl: Stallion EasyIO and EasyConnection 8/32 (ISA and PCI), EasyConnection 8/64 PCI
 # stli: Stallion EasyConnection 8/64 ISA/EISA, ONboard, Brumby (intelligent)
 # nmdm: nullmodem terminal driver (see nmdm(4))
 
 # Notes on APM
 #  The flags takes the following meaning for apm0:
 #    0x0020  Statclock is broken.
 #  If apm is omitted, some systems require sysctl -w kern.timecounter.method=1
 #  for correct timekeeping.
 
 # Notes on the spigot:
 #  The video spigot is at 0xad6.  This port address can not be changed.
 #  The irq values may only be 10, 11, or 15
 #  I/O memory is an 8kb region.  Possible values are:
 #    0a0000, 0a2000, ..., 0fffff, f00000, f02000, ..., ffffff
 #    The start address must be on an even boundary.
 #  Add the following option if you want to allow non-root users to be able
 #  to access the spigot.  This option is not secure because it allows users
 #  direct access to the I/O page.
 #  	options SPIGOT_UNSECURE
 
 # Notes on the Comtrol Rocketport driver:
 #
 # The exact values used for rp0 depend on how many boards you have
 # in the system.  The manufacturer's sample configs are listed as:
 #
 #   Comtrol Rocketport ISA single card
 #               device  rp0     at isa? port 0x280
 #
 #   If instead you have two ISA cards, one installed at 0x100 and the
 #   second installed at 0x180, then you should add the following to
 #   your kernel configuration file:
 #
 #               device  rp0     at isa? port 0x100
 #               device  rp1     at isa? port 0x180
 #
 #   For 4 ISA cards, it might be something like this:
 #
 #               device  rp0     at isa? port 0x180
 #               device  rp1     at isa? port 0x100
 #               device  rp2     at isa? port 0x340
 #               device  rp3     at isa? port 0x240
 #
 #   And for PCI cards, you only need say:
 #
 #               device rp
 
 # Notes on the Digiboard driver:
 #
 # The following flag values have special meanings:
 #	0x01 - alternate layout of pins (dgb & dgm)
 #	0x02 - use the windowed PC/Xe in 64K mode (dgb only)
 
 # Notes on the Specialix SI/XIO driver:
 #  **This is NOT a Specialix supported Driver!**
 #  The host card is memory, not IO mapped.
 #  The Rev 1 host cards use a 64K chunk, on a 32K boundary.
 #  The Rev 2 host cards use a 32K chunk, on a 32K boundary.
 #  The cards can use an IRQ of 11, 12 or 15.
 
 # Notes on the Stallion stl and stli drivers:
 #  See src/i386/isa/README.stl for complete instructions.
 #  This is version 2.0.0, unsupported by Stallion.
 #  The stl driver has a secondary IO port hard coded at 0x280.  You need
 #     to change src/i386/isa/stallion.c if you reconfigure this on the boards.
 #  The "flags" and "iosiz" settings on the stli driver depend on the board:
 #	EasyConnection 8/64 ISA:     flags 23         iosiz 0x1000
 #	EasyConnection 8/64 EISA:    flags 24         iosiz 0x10000
 #	EasyConnection 8/64 MCA:     flags 25         iosiz 0x1000
 #	ONboard ISA:                 flags 4          iosiz 0x10000
 #	ONboard EISA:                flags 7          iosiz 0x10000
 #	ONboard MCA:                 flags 3          iosiz 0x10000
 #	Brumby:                      flags 2          iosiz 0x4000
 #	Stallion:                    flags 1          iosiz 0x10000
 #  For the PCI cards, "device stl" will suffice.
 
 device		mcd0	at isa? port 0x300 irq 10
 # for the Sony CDU31/33A CDROM
 device		scd0	at isa? port 0x230
 # for the SoundBlaster 16 multicd - up to 4 devices
 device		matcd0  at isa? port 0x230
 device		wt0	at isa? port 0x300 irq 5 drq 1
 device		ctx0	at isa? port 0x230 iomem 0xd0000
 device		spigot0 at isa? port 0xad6 irq 15 iomem 0xee000
 device		apm0
 device		gp0	at isa? port 0x2c0
 device		gsc0	at isa? port IO_GSC1 drq 3
 device		joy0	at isa? port IO_GAME
 device		cy0	at isa? irq 10 iomem 0xd4000 iosiz 0x2000
 options 	CY_PCI_FASTINTR		# Use with cy_pci unless irq is shared
 device		dgb0	at isa? port 0x220 iomem 0xfc000
 options 	NDGBPORTS=16		# Defaults to 16*NDGB
 device		dgm0	at isa? port 0x104 iomem 0xd0000
 device		labpc0	at isa? port 0x260 irq 5
 device		rc0	at isa? port 0x220 irq 12
 device		rp0	at isa? port 0x280
 # the port and irq for tw0 are fictitious
 device		tw0	at isa? port 0x380 irq 11
 device		si0	at isa? iomem 0xd0000 irq 12
 device		asc0	at isa? port IO_ASC1 drq 3 irq 10
 device		stl0	at isa? port 0x2a0 irq 10
 device		stli0	at isa? port 0x2a0 iomem 0xcc000 flags 23 iosiz 0x1000
 # You are unlikely to have the hardware for loran0 <phk@FreeBSD.org>
 device		loran0	at isa? irq 5
 # HOT1 Xilinx 6200 card (http://www.vcc.com/)
 device		xrpu
 # nullmodem terminal driver
 device		nmdm
 
 #
 # MCA devices:
 #
 # The MCA bus device is `mca'.  It provides auto-detection and
 # configuration support for all devices on the MCA bus.
 #
 # The 'aha' device provides support for the Adaptec 1640
 #
 # The 'bt' device provides support for various Buslogic/Bustek
 # and Storage Dimensions SCSI adapters.
 #
 # The 'ep' device provides support for the 3Com 3C529 ethernet card.
 #
 device		mca
 
 #
 # EISA devices:
 #
 # The EISA bus device is `eisa'.  It provides auto-detection and
 # configuration support for all devices on the EISA bus.
 #
 # The `ahb' device provides support for the Adaptec 174X adapter.
 #
 # The `ahc' device provides support for the Adaptec 274X and 284X
 # adapters.  The 284X, although a VLB card, responds to EISA probes.
 #
 # fea: DEC DEFEA EISA FDDI adapter
 #
 device		eisa
 device		ahb
 device		ahc
 device		fea
 
 # The aic7xxx driver will attempt to use memory mapped I/O for all PCI
 # controllers that have it configured only if this option is set. Unfortunately,
 # this doesn't work on some motherboards, which prevents it from being the
 # default.
 options 	AHC_ALLOW_MEMIO
 
 # The adw driver will attempt to use memory mapped I/O for all PCI
 # controllers that have it configured only if this option is set.
 options 	ADW_ALLOW_MEMIO
 
 # By default, only 10 EISA slots are probed, since the slot numbers
 # above clash with the configuration address space of the PCI subsystem,
 # and the EISA probe is not very smart about this.  This is sufficient
 # for most machines, but in particular the HP NetServer LC series comes
 # with an onboard AIC7770 dual-channel SCSI controller on EISA slot #11,
 # thus you need to bump this figure to 12 for them.
 options 	EISA_SLOTS=12
 
 #
 # PCI devices & PCI options:
 #
 # The main PCI bus device is `pci'.  It provides auto-detection and
 # configuration support for all devices on the PCI bus, using either
 # configuration mode defined in the PCI specification.
 
 device		pci
 
 # PCI options
 #
 #options 	PCI_QUIET	#quiets PCI code on chipset settings
 
 
 # The `ahc' device provides support for the Adaptec 29/3940(U)(W)
 # and motherboard based AIC7870/AIC7880 adapters.
 #
 # The `amd' device provides support for the AMD 53C974 SCSI host
 # adapter chip as found on devices such as the Tekram DC-390(T).
 #
 # The `bge' device provides support for gigabit ethernet adapters
 # based on the Broadcom BCM570x familiy of controllers, including the
-# 3Com 3c996-T, the SysKonnect SK-9D21 and SK-9D41, and the embedded
-# gigE NICs on Dell PowerEdge 2550 servers.
+# 3Com 3c996-T, the Netgear GA302T, the SysKonnect SK-9D21 and SK-9D41,
+# and the embedded gigE NICs on Dell PowerEdge 2550 servers.
 #
 # The `ncr' device provides support for the NCR 53C810 and 53C825
 # self-contained SCSI host adapters.
 #
 # The `isp' device provides support for the Qlogic ISP 1020, 1040
 # nd 1040B PCI SCSI host adapters, ISP 1240 Dual Ultra SCSI,
 # ISP 1080 and 1280 (Dual) Ultra2, ISP 12160 Ultra3 SCSI, as well as
 # the Qlogic ISP 2100 and ISP 2200 Fibre Channel Host Adapters.
 #
 # The `dc' device provides support for PCI fast ethernet adapters
 # based on the DEC/Intel 21143 and various workalikes including:
 # the ADMtek AL981 Comet and AN985 Centaur, the ASIX Electronics
 # AX88140A and AX88141, the Davicom DM9100 and DM9102, the Lite-On
 # 82c168 and 82c169 PNIC, the Lite-On/Macronix LC82C115 PNIC II
 # and the Macronix 98713/98713A/98715/98715A/98725 PMAC. This driver
 # replaces the old al, ax, dm, pn and mx drivers.  List of brands:
 # Digital DE500-BA, Kingston KNE100TX, D-Link DFE-570TX, SOHOware SFA110, 
 # SVEC PN102-TX, CNet Pro110B, 120A, and 120B, Compex RL100-TX, 
 # LinkSys LNE100TX, LNE100TX V2.0, Jaton XpressNet, Alfa Inc GFC2204,
 # KNE110TX.
 #
 # The `de' device provides support for the Digital Equipment DC21040
 # self-contained Ethernet adapter.
 #
 # The `fxp' device provides support for the Intel EtherExpress Pro/100B
 # PCI Fast Ethernet adapters.
 #
 # The `gx' device provides support for the Intel Pro/1000 Gigabit Ethernet
 # PCI adapters (82542, 82543-F, 82543-T).
 #
 # The 'lge' device provides support for PCI gigabit ethernet adapters
 # based on the Level 1 LXT1001 NetCellerator chipset. This includes the
 # D-Link DGE-500SX, SMC TigerCard 1000 (SMC9462SX), and some Addtron cards.
 #
 # The 'nge' device provides support for PCI gigabit ethernet adapters
 # based on the National Semiconductor DP83820 and DP83821 chipset. This
 # includes the SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante
 # FriendlyNet GigaNIX 1000TA and 1000TPC, the Addtron AEG320T, the
 # LinkSys EG1032 and EG1064, the Surecom EP-320G-TX and the Netgear GA622T.
 #
 # The 'pcn' device provides support for PCI fast ethernet adapters based
 # on the AMD Am79c97x chipsets, including the PCnet/FAST, PCnet/FAST+,
 # PCnet/PRO and PCnet/Home. These were previously handled by the lnc
 # driver (and still will be if you leave this driver out of the kernel).
 #
 # The 'rl' device provides support for PCI fast ethernet adapters based
 # on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
 # to using programmed I/O to do register accesses because memory mapped
 # mode seems to cause severe lockups on SMP hardware. This driver also
 # supports the Accton EN1207D `Cheetah' adapter, which uses a chip called
 # the MPX 5030/5038, which is either a RealTek in disguise or a RealTek
 # workalike.  Note that the D-Link DFE-530TX+ uses the RealTek chipset
 # and is supported by this driver, not the 'vr' driver.
 #
 # The 'sf' device provides support for Adaptec Duralink PCI fast
 # ethernet adapters based on the Adaptec AIC-6915 "starfire" controller.
 # This includes dual and quad port cards, as well as one 100baseFX card.
 # Most of these are 64-bit PCI devices, except for one single port
 # card which is 32-bit.
 #
 # The 'ste' device provides support for adapters based on the Sundance
 # Technologies ST201 PCI fast ethernet controller. This includes the
 # D-Link DFE-550TX.
 #
 # The 'sis' device provides support for adapters based on the Silicon
 # Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet controller
 # chips.
 #
 # The 'sk' device provides support for the SysKonnect SK-984x series
 # PCI gigabit ethernet NICs. This includes the SK-9841 and SK-9842
 # single port cards (single mode and multimode fiber) and the
 # SK-9843 and SK-9844 dual port cards (also single mode and multimode).
 # The driver will autodetect the number of ports on the card and
 # attach each one as a separate network interface.
 #
 # The 'ti' device provides support for PCI gigabit ethernet NICs based
 # on the Alteon Networks Tigon 1 and Tigon 2 chipsets. This includes the
 # Alteon AceNIC, the 3Com 3c985, the Netgear GA620 and various others.
 # Note that you will probably want to bump up NMBCLUSTERS a lot to use
 # this driver.
 #
 # The 'tl' device provides support for the Texas Instruments TNETE100
 # series 'ThunderLAN' cards and integrated ethernet controllers. This
 # includes several Compaq Netelligent 10/100 cards and the built-in
 # ethernet controllers in several Compaq Prosignia, Proliant and
 # Deskpro systems. It also supports several Olicom 10Mbps and 10/100
 # boards.
 #
 # The `tx' device provides support for the SMC 9432 TX, BTX and FTX cards.
 #
 # The `txp' device provides support for the 3Com 3cR990 "Typhoon"
 # 10/100 adapters.
 #
 # The `vr' device provides support for various fast ethernet adapters
 # based on the VIA Technologies VT3043 `Rhine I' and VT86C100A `Rhine II'
 # chips, including the D-Link DFE530TX (see 'rl' for DFE530TX+), the Hawking 
 # Technologies PN102TX, and the AOpen/Acer ALN-320.
 #
 # The `vx' device provides support for the 3Com 3C590 and 3C595
 # early support
 #
 # The `wb' device provides support for various fast ethernet adapters
 # based on the Winbond W89C840F chip. Note: this is not the same as
 # the Winbond W89C940F, which is an NE2000 clone.
 #
 # The `wx' device provides support for the Intel Gigabit Ethernet
 # PCI card (`Wiseman').
 #
 # The `xl' device provides support for the 3Com 3c900, 3c905 and
 # 3c905B (Fast) Etherlink XL cards and integrated controllers. This
 # includes the integrated 3c905B-TX chips in certain Dell Optiplex and
 # Dell Precision desktop machines and the integrated 3c905-TX chips
 # in Dell Latitude laptop docking stations.
 #
 # The `fpa' device provides support for the Digital DEFPA PCI FDDI
 # adapter. pseudo-device fddi is also needed.
 #
 # The `meteor' device is a PCI video capture board. It can also have the
 # following options:
 #   options METEOR_ALLOC_PAGES=xxx	preallocate kernel pages for data entry
 #	figure (ROWS*COLUMN*BYTES_PER_PIXEL*FRAME+PAGE_SIZE-1)/PAGE_SIZE
 #   options METEOR_DEALLOC_PAGES	remove all allocated pages on close(2)
 #   options METEOR_DEALLOC_ABOVE=xxx	remove all allocated pages above the
 #	specified amount. If this value is below the allocated amount no action
 #	taken
 #   options METEOR_SYSTEM_DEFAULT={METEOR_PAL|METEOR_NTSC|METEOR_SECAM}, used
 #	for initialization of fps routine when a signal is not present.
 #
 # The 'bktr' device is a PCI video capture device using the Brooktree
 # bt848/bt848a/bt849a/bt878/bt879 chipset. When used with a TV Tuner it forms a
 # TV card, eg Miro PC/TV, Hauppauge WinCast/TV WinTV, VideoLogic Captivator,
 # Intel Smart Video III, AverMedia, IMS Turbo, FlyVideo.
 #
 # options 	OVERRIDE_CARD=xxx
 # options 	OVERRIDE_TUNER=xxx
 # options 	OVERRIDE_MSP=1
 # options 	OVERRIDE_DBX=1
 # These options can be used to override the auto detection
 # The current values for xxx are found in src/sys/dev/bktr/bktr_card.h
 # Using sysctl(8) run-time overrides on a per-card basis can be made
 #
 # options 	BROOKTREE_SYSTEM_DEFAULT=BROOKTREE_PAL
 # or
 # options 	BROOKTREE_SYSTEM_DEFAULT=BROOKTREE_NTSC
 # Specifes the default video capture mode.
 # This is required for Dual Crystal (28&35Mhz) boards where PAL is used
 # to prevent hangs during initialisation.  eg VideoLogic Captivator PCI.
 #
 # options 	BKTR_USE_PLL
 # PAL or SECAM users who have a 28Mhz crystal (and no 35Mhz crystal)
 # must enable PLL mode with this option. eg some new Bt878 cards.
 #
 # options 	BKTR_GPIO_ACCESS
 # This enable IOCTLs which give user level access to the GPIO port.
 #
 # options 	BKTR_NO_MSP_RESET
 # Prevents the MSP34xx reset. Good if you initialise the MSP in another OS first
 #
 # options 	BKTR_430_FX_MODE
 # Switch Bt878/879 cards into Intel 430FX chipset compatibility mode.
 #
 # options 	BKTR_SIS_VIA_MODE
 # Switch Bt878/879 cards into SIS/VIA chipset compatibility mode which is
 # needed for some old SiS and VIA chipset motherboards.
 # This also allows Bt878/879 chips to work on old OPTi (<1997) chipset
 # motherboards and motherboards with bad or incomplete PCI 2.1 support.
 # As a rough guess, old = before 1998
 #
 #
 # The oltr driver supports the following Olicom PCI token-ring adapters
 # OC-3136, OC-3137, OC-3139, OC-3140, OC-3141, OC-3540, OC-3250
 #
 device		ahc		# AHA2940 and onboard AIC7xxx devices
 device		amd		# AMD 53C974 (Teckram DC-390(T))
 device		isp		# Qlogic family
 device		ispfw		# Firmware for QLogic HBAs
 device		ncr		# NCR/Symbios Logic
 device		sym		# NCR/Symbios Logic (newer chipsets)
 #
 # Options for ISP
 #
 #	ISP_TARGET_MODE		-	enable target mode operation
 #options 	ISP_TARGET_MODE=1
 
 # Options used in dev/sym/ (Symbios SCSI driver).
 #options 	SYM_SETUP_LP_PROBE_MAP	#-Low Priority Probe Map (bits)
 					# Allows the ncr to take precedence
 					# 1 (1<<0) -> 810a, 860
 					# 2 (1<<1) -> 825a, 875, 885, 895
 					# 4 (1<<2) -> 895a, 896, 1510d 
 #options 	SYM_SETUP_SCSI_DIFF	#-HVD support for 825a, 875, 885
 					# disabled:0 (default), enabled:1
 #options 	SYM_SETUP_PCI_PARITY	#-PCI parity checking
 					# disabled:0, enabled:1 (default)
 #options 	SYM_SETUP_MAX_LUN	#-Number of LUNs supported
 					# default:8, range:[1..64]
 
 
 # MII bus support is required for some PCI 10/100 ethernet NICs,
 # namely those which use MII-compliant transceivers or implement
 # tranceiver control interfaces that operate like an MII. Adding
 # "device miibus0" to the kernel config pulls in support for
 # the generic miibus API and all of the PHY drivers, including a
 # generic one for PHYs that aren't specifically handled by an
 # individual driver.
 device		miibus
 
 # PCI Ethernet NICs that use the common MII bus controller code.
 device		dc		# DEC/Intel 21143 and various workalikes
 device		fxp		# Intel EtherExpress PRO/100B (82557, 82558)
 device		pcn		# AMD Am79C97x PCI 10/100 NICs
 device		rl		# RealTek 8129/8139
 device		sf		# Adaptec AIC-6915 (``Starfire'')
 device		sis		# Silicon Integrated Systems SiS 900/SiS 7016
 device		ste		# Sundance ST201 (D-Link DFE-550TX)
 device		tl		# Texas Instruments ThunderLAN
 device		tx		# SMC EtherPower II (83c17x ``EPIC'')
 device		vr		# VIA Rhine, Rhine II
 device		wb		# Winbond W89C840F
 device		xl		# 3Com 3c90x (``Boomerang'', ``Cyclone'')
 
 # PCI Ethernet NICs.
 device		de		# DEC/Intel DC21x4x (``Tulip'')
 device		txp		# 3Com 3cR990 (``Typhoon'')
 device		vx		# 3Com 3c590, 3c595 (``Vortex'')
 
 # Gigabit Ethernet NICs.
 device		bge		# Broadcom BCM570x (``Tigon III'')
 device		gx		# Intel Pro/1000 (82542, 82543)
 device		lge		# Level 1 LXT1001 (``Mercury'')
 device		nge		# NatSemi DP83820 and DP83821
 device		sk		# SysKonnect GEnesis
 device		ti		# Alteon (``Tigon I'', ``Tigon II'')
 device		wx
 
 
 device		fpa
 device		meteor
 #The oltr driver in the ISA section will also find PCI cards.
 #device		oltr0
 
 
 # Brooktree driver has been ported to the new I2C framework. Thus,
 # you'll need to have the following 3 lines in the kernel config.
 #     device smbus
 #     device iicbus
 #     device iicbb
 # The iic and smb devices are only needed if you want to control other
 # I2C slaves connected to the external connector of some cards.
 #
 device		bktr
 
 #
 # PCCARD/PCMCIA
 #
 # card: pccard slots
 # pcic: isa/pccard bridge
 device		pcic0 at isa?
 device		pcic1 at isa?
 device		card
 
 # You may need to reset all pccards after resuming
 options 	PCIC_RESUME_RESET	# reset after resume
 
 #
 # Laptop/Notebook options:
 #
 # See also:
 #  apm under `Miscellaneous hardware'
 # above.
 
 # For older notebooks that signal a powerfail condition (external
 # power supply dropped, or battery state low) by issuing an NMI:
 
 options 	POWERFAIL_NMI	# make it beep instead of panicing
 
 #
 # SMB bus
 #
 # System Management Bus support is provided by the 'smbus' device.
 # Access to the SMBus device is via the 'smb' device (/dev/smb*),
 # which is a child of the 'smbus' device.
 #
 # Supported devices:
 # smb		standard io through /dev/smb*
 #
 # Supported SMB interfaces:
 # iicsmb	I2C to SMB bridge with any iicbus interface
 # bktr		brooktree848 I2C hardware interface
 # intpm		Intel PIIX4 (82371AB, 82443MX) Power Management Unit
 # alpm		Acer Aladdin-IV/V/Pro2 Power Management Unit
 # ichsmb	Intel ICH SMBus controller chips (82801AA, 82801AB, 82801BA)
 #
 device		smbus		# Bus support, required for smb below.
 
 device		intpm
 device		alpm
 device		ichsmb
 
 device		smb
 
 #
 # I2C Bus
 #
 # Philips i2c bus support is provided by the `iicbus' device.
 #
 # Supported devices:
 # ic	i2c network interface
 # iic	i2c standard io
 # iicsmb i2c to smb bridge. Allow i2c i/o with smb commands.
 #
 # Supported interfaces:
 # pcf	Philips PCF8584 ISA-bus controller
 # bktr	brooktree848 I2C software interface
 #
 # Other:
 # iicbb	generic I2C bit-banging code (needed by lpbb, bktr)
 #
 device		iicbus		# Bus support, required for ic/iic/iicsmb below.
 device		iicbb
 
 device		ic
 device		iic
 device		iicsmb		# smb over i2c bridge
 
 device		pcf0	at isa? port 0x320 irq 5
 
 #---------------------------------------------------------------------------
 # ISDN4BSD
 #
 # See /usr/share/examples/isdn/ROADMAP for an introduction to isdn4bsd.
 #
 # i4b passive ISDN cards support contains the following hardware drivers:
 #
 #       isic  - Siemens/Infineon ISDN ISAC/HSCX/IPAC chipset driver
 #       iwic  - Winbond W6692 PCI bus ISDN S/T interface controller
 #       ifpi  - AVM Fritz!Card PCI driver
 #       ihfc  - Cologne Chip HFC ISA/ISA-PnP chipset driver
 #       ifpnp - AVM Fritz!Card PnP driver 
 #       itjc  - Siemens ISAC / TJNet Tiger300/320 chipset
 #
 # i4b active ISDN cards support contains the following hardware drivers:
 #
 #       iavc  - AVM B1 PCI, AVM B1 ISA, AVM T1
 #
 # Note that the ``options'' (if given) and ``device'' lines must BOTH
 # be uncommented to enable support for a given card !
 #
 # In addition to a hardware driver (and probably an option) the mandatory
 # ISDN protocol stack devices and the mandatory support device must be 
 # enabled as well as one or more devices from the optional devices section.
 #
 #---------------------------------------------------------------------------
 # isic driver (Siemens/Infineon chipsets)
 #---------------------------------------------------------------------------
 #
 # ISA bus non-PnP Cards:
 # ----------------------
 #
 # Teles S0/8 or Niccy 1008
 options 	TEL_S0_8
 device		isic0	at isa? iomem 0xd0000 irq 5 flags 1
 #
 # Teles S0/16 or Creatix ISDN-S0 or Niccy 1016
 options 	TEL_S0_16
 #device		isic0	at isa? port 0xd80 iomem 0xd0000 irq 5 flags 2
 #
 # Teles S0/16.3
 options 	TEL_S0_16_3
 #device		isic0	at isa? port 0xd80 irq 5 flags 3
 #
 # AVM A1 or AVM Fritz!Card
 options 	AVM_A1
 #device		isic0	at isa? port 0x340 irq 5 flags 4
 #
 # USRobotics Sportster ISDN TA intern
 options 	USR_STI
 #device		isic0	at isa? port 0x268 irq 5 flags 7
 #
 # ITK ix1 Micro ( < V.3, non-PnP version )
 options 	ITKIX1
 #device		isic0	at isa? port 0x398 irq 10 flags 18
 #
 # ELSA PCC-16
 options 	ELSA_PCC16
 #device		isic0	at isa? port 0x360 irq 10 flags 20
 #
 # ISA bus PnP Cards:
 # ------------------
 #
 # Teles S0/16.3 PnP
 options 	TEL_S0_16_3_P
 #device		isic
 #
 # Creatix ISDN-S0 P&P
 options 	CRTX_S0_P
 #device		isic
 #
 # Dr. Neuhaus Niccy Go@
 options 	DRN_NGO
 #device		isic
 #
 # Sedlbauer Win Speed
 options 	SEDLBAUER
 #device		isic
 #
 # Dynalink IS64PH
 options 	DYNALINK 
 #device		isic
 #
 # ELSA QuickStep 1000pro ISA
 options 	ELSA_QS1ISA
 #device		isic
 #
 # ITK ix1 Micro ( V.3, PnP version )
 options 	ITKIX1
 #device		isic
 #
 # Siemens I-Surf 2.0
 options 	SIEMENS_ISURF2
 #device		isic
 #
 # Asuscom ISDNlink 128K ISAC
 options 	ASUSCOM_IPAC
 #device 	isic
 #
 # Eicon Diehl DIVA 2.0 and 2.02
 options       EICON_DIVA
 #device 	isic
 #
 # PCI bus Cards:
 # --------------
 #
 # ELSA MicroLink ISDN/PCI (same as ELSA QuickStep 1000pro PCI)
 options 	ELSA_QS1PCI
 #device		isic
 #
 #---------------------------------------------------------------------------
 #       ifpnp driver for AVM Fritz!Card ISA PnP
 #---------------------------------------------------------------------------
 #
 # AVM Fritz!Card ISA PnP
 device ifpnp
 #
 #---------------------------------------------------------------------------
 #       ihfc driver for Cologne Chip ISA chipsets (experimental!)
 #---------------------------------------------------------------------------
 #
 # Teles 16.3c ISA PnP
 # AcerISDN P10 ISA PnP
 # TELEINT ISDN SPEED No.1
 device ihfc
 #
 #---------------------------------------------------------------------------
 #       ifpi driver for AVM Fritz!Card PCI 1.0 (2.0 unsupported!)
 #---------------------------------------------------------------------------
 #
 # AVM Fritz!Card PCI 1.0
 device  ifpi
 #
 #---------------------------------------------------------------------------
 #       iwic driver for Winbond W6692 chipset
 #---------------------------------------------------------------------------
 #
 # ASUSCOM P-IN100-ST-D (and other Winbond W6692 based cards)
 device  iwic
 #
 #---------------------------------------------------------------------------
 #       itjc driver for Simens ISAC / TJNet Tiger300/320 chipset
 #---------------------------------------------------------------------------
 #
 # Traverse Technologies NETjet-S
 # Teles PCI-TJ
 device  itjc
 #
 #---------------------------------------------------------------------------
 #       iavc driver (AVM active cards, needs i4bcapi driver!)
 #---------------------------------------------------------------------------
 #
 pseudo-device   "i4bcapi"	2
 #
 # AVM B1 PCI
 device          iavc0
 #
 # AVM B1 ISA bus (PnP mode not supported!)
 #device  iavc0 at isa? port 0x150 irq 5
 #
 #
 # ISDN Protocol Stack (mandatory)
 # -------------------------------
 #
 # Q.921 / layer 2 - i4b passive cards D channel handling
 pseudo-device	"i4bq921"
 #
 # Q.931 / layer 3 - i4b passive cards D channel handling
 pseudo-device	"i4bq931"
 #
 # layer 4 - i4b common passive and active card handling
 pseudo-device	"i4b"
 #
 # ISDN devices
 # ------------
 #
 # userland driver to do ISDN tracing (for passive cards only)
 pseudo-device	"i4btrc"	4
 #
 # userland driver to control the whole thing (mandatory)
 pseudo-device	"i4bctl"
 #
 # userland driver for access to raw B channel
 pseudo-device	"i4brbch"	4
 #
 # userland driver for telephony
 pseudo-device	"i4btel"	2
 #
 # network driver for IP over raw HDLC ISDN
 pseudo-device	"i4bipr"	4
 # enable VJ header compression detection for ipr i/f
 options 	IPR_VJ
 # enable logging of the first n IP packets to isdnd (n=32 here)
 #options	IPR_LOG=32
 #
 # network driver for sync PPP over ISDN
 pseudo-device	"i4bisppp"	4
 
 
 # Parallel-Port Bus
 #
 # Parallel port bus support is provided by the `ppbus' device.
 # Multiple devices may be attached to the parallel port, devices
 # are automatically probed and attached when found.
 #
 # Supported devices:
 # vpo	Iomega Zip Drive
 #	Requires SCSI disk support ('scbus' and 'da'), best
 #	performance is achieved with ports in EPP 1.9 mode.
 # lpt	Parallel Printer
 # plip	Parallel network interface
 # ppi	General-purpose I/O ("Geek Port") + IEEE1284 I/O
 # pps	Pulse per second Timing Interface
 # lpbb	Philips official parallel port I2C bit-banging interface
 #
 # Supported interfaces:
 # ppc	ISA-bus parallel port interfaces.
 #
 
 options		PPC_PROBE_CHIPSET # Enable chipset specific detection
 				  # (see flags in ppc(4))
 options 	DEBUG_1284	# IEEE1284 signaling protocol debug
 options 	PERIPH_1284	# Makes your computer act as a IEEE1284
 				# compliant peripheral
 options 	DONTPROBE_1284	# Avoid boot detection of PnP parallel devices
 options 	VP0_DEBUG	# ZIP/ZIP+ debug
 options 	LPT_DEBUG	# Printer driver debug
 options 	PPC_DEBUG	# Parallel chipset level debug
 options 	PLIP_DEBUG	# Parallel network IP interface debug
 options		PCFCLOCK_VERBOSE         # Verbose pcfclock driver
 options		PCFCLOCK_MAX_RETRIES=5   # Maximum read tries (default 10)
 
 device		ppc0	at isa? irq 7
 device		ppbus
 device		vpo
 device		lpt
 device		plip
 device		ppi
 device		pps
 device		lpbb
 device		pcfclock
 
 # Kernel BOOTP support
 
 options 	BOOTP		# Use BOOTP to obtain IP address/hostname
 options 	BOOTP_NFSROOT	# NFS mount root filesystem using BOOTP info
 options 	BOOTP_NFSV3	# Use NFS v3 to NFS mount root
 options 	BOOTP_COMPAT	# Workaround for broken bootp daemons.
 options 	BOOTP_WIRED_TO=fxp0 # Use interface fxp0 for BOOTP
 
 #
 # Add tie-ins for a hardware watchdog.  This only enable the hooks;
 # the user must still supply the actual driver.
 #
 options 	HW_WDOG
 
 #
 # Set the number of PV entries per process.  Increasing this can
 # stop panics related to heavy use of shared memory. However, that can
 # (combined with large amounts of physical memory) cause panics at
 # boot time due the kernel running out of VM space.
 #
 # If you're tweaking this, you might also want to increase the sysctls
 # "vm.v_free_min", "vm.v_free_reserved", and "vm.v_free_target".
 #
 # The value below is the one more than the default.
 #
 options 	PMAP_SHPGPERPROC=201
 
 #
 # Change the size of the kernel virtual address space.  Due to
 # constraints in loader(8) on i386, this must be a multiple of 4.
 # 256 = 1 GB of kernel address space.  Increasing this also causes
 # a reduction of the address space in user processes.  512 splits
 # the 4GB cpu address space in half (2GB user, 2GB kernel).
 #
 options 	KVA_PAGES=260
 
 #
 # Disable swapping. This option removes all code which actually performs
 # swapping, so it's not possible to turn it back on at run-time.
 #
 # This is sometimes usable for systems which don't have any swap space
 # (see also sysctls "vm.defer_swapspace_pageouts" and
 # "vm.disable_swapspace_pageouts")
 #
 #options 	NO_SWAPPING
 
 # Set the number of sf_bufs to allocate. sf_bufs are virtual buffers
 # for sendfile(2) that are used to map file VM pages, and normally
 # default to a quantity that is roughly 16*MAXUSERS+512. You would
 # typically want about 4 of these for each simultaneous file send.
 #
 options 	NSFBUFS=1024
 
 # Set the size of the buffer cache KVM reservation, in buffers.  This is
 # scaled by approximately 16384 bytes.  The system will auto-size the buffer
 # cache if this option is not specified or set to 0.
 #
 options 	NBUF=512
 
 # Set the size of the mbuf KVM reservation, in clusters.  This is scaled
 # by approximately 2048 bytes.  The system will auto-size the mbuf area
 # if this options is not specified or set to 0.
 #
 options 	NMBCLUSTERS=1024
 
 # Tune the kernel malloc area parameters.  VM_KMEM_SIZE represents the 
 # minimum, in bytes, and is typically (12*1024*1024) (12MB). 
 # VM_KMEM_SIZE_MAX represents the maximum, typically 200 megabytes.
 # VM_KMEM_SIZE_SCALE can be set to adjust the auto-tuning factor, which
 # typically defaults to 4 (kernel malloc area size is physical memory 
 # divided by the scale factor).
 #
 options 	VM_KMEM_SIZE="(10*1024*1024)"
 options 	VM_KMEM_SIZE_MAX="(100*1024*1024)"
 options 	VM_KMEM_SIZE_SCALE="4"
 
 # Tune the buffer cache maximum KVA reservation, in bytes.  The maximum is
 # usually capped at 200 MB, effecting machines with > 1GB of ram.  Note
 # that the buffer cache only really governs write buffering and disk block
 # translations.  The VM page cache is our primary disk cache and is not
 # effected by the size of the buffer cache.
 #
 options		VM_BCACHE_SIZE_MAX="(100*1024*1024)"
 
 # Tune the swap zone KVA reservation, in bytes.  The default is typically
 # 70 MB, giving the system the ability to manage a maximum of 28GB worth
 # of swapped out data.  
 #
 options		VM_SWZONE_SIZE_MAX="(50*1024*1024)"
 
 #
 # Enable extra debugging code for locks.  This stores the filename and
 # line of whatever acquired the lock in the lock itself, and change a
 # number of function calls to pass around the relevant data.  This is
 # not at all useful unless you are debugging lock code.  Also note
 # that it is likely to break e.g. fstat(1) unless you recompile your
 # userland with -DDEBUG_LOCKS as well.
 #
 options 	DEBUG_LOCKS
 
 # Set the amount of time (in seconds) the system will wait before
 # rebooting automatically when a kernel panic occurs.  If set to (-1),
 # the system will wait indefinitely until a key is pressed on the
 # console.
 options 	PANIC_REBOOT_WAIT_TIME=16
 
 #
 # SysVR4 ABI emulation
 #
 # The svr4 ABI emulator can be statically compiled into the kernel or loaded as
 # a KLD module.  
 # The STREAMS network emulation code can also be compiled statically or as a 
 # module.  If loaded as a module, it must be loaded before the svr4 module
 # (the /usr/sbin/svr4 script does this for you).  If compiling statically,
 # the `streams' pseudo-device must be configured into any kernel which also
 # specifies COMPAT_SVR4.  It is possible to have a statically-configured 
 # STREAMS device and a dynamically loadable svr4 emulator;  the /usr/sbin/svr4
 # script understands that it doesn't need to load the `streams' module under
 # those circumstances.
 # Caveat:  At this time, `options KTRACE' is required for the svr4 emulator
 # (whether static or dynamic).  
 # 
 options		COMPAT_SVR4	# build emulator statically
 options		DEBUG_SVR4	# enable verbose debugging
 pseudo-device	streams		# STREAMS network driver (required for svr4).
 
 # The 'asr' driver provides support for current DPT/Adaptec SCSI RAID
 # controllers (SmartRAID V and VI and later).
 # These controllers require the CAM infrastructure.
 #
 device		asr
 
 # The 'dpt' driver provides support for DPT controllers (http://www.dpt.com/).
 # These have hardware RAID-{0,1,5} support, and do multi-initiator I/O.
 # The DPT controllers are commonly re-licensed under other brand-names -
 # some controllers by Olivetti, Dec, HP, AT&T, SNI, AST, Alphatronic, NEC and
 # Compaq are actually DPT controllers.
 #
 # See src/sys/dev/dpt for debugging and other subtle options.
 #   DPT_MEASURE_PERFORMANCE Enables a set of (semi)invasive metrics. Various
 #                           instruments are enabled.  The tools in
 #                           /usr/sbin/dpt_* assume these to be enabled.
 #   DPT_HANDLE_TIMEOUTS     Normally device timeouts are handled by the DPT.
 #                           If you ant the driver to handle timeouts, enable
 #                           this option.  If your system is very busy, this
 #                           option will create more trouble than solve.
 #   DPT_TIMEOUT_FACTOR      Used to compute the excessive amount of time to
 #                           wait when timing out with the above option.
 #  DPT_DEBUG_xxxx           These are controllable from sys/dev/dpt/dpt.h
 #  DPT_LOST_IRQ             When enabled, will try, once per second, to catch
 #                           any interrupt that got lost.  Seems to help in some
 #                           DPT-firmware/Motherboard combinations.  Minimal
 #                           cost, great benefit.
 #  DPT_RESET_HBA            Make "reset" actually reset the controller
 #                           instead of fudging it.  Only enable this if you
 #			    are 100% certain you need it.
 
 device		dpt
 
 # DPT options
 #!CAM# options 	DPT_MEASURE_PERFORMANCE
 #!CAM# options 	DPT_HANDLE_TIMEOUTS
 options 	DPT_TIMEOUT_FACTOR=4
 options 	DPT_LOST_IRQ
 options 	DPT_RESET_HBA
 options 	DPT_ALLOW_MEMIO
 
 #
 # Compaq "CISS" RAID controllers (SmartRAID 5* series)
 # These controllers have a SCSI-like interface, and require the
 # CAM infrastructure.
 #
 device		ciss
 
 #
 # Mylex AcceleRAID and eXtremeRAID controllers with v6 and later
 # firmware.  These controllers have a SCSI-like interface, and require
 # the CAM infrastructure.
 #
 device          mly
 
 # USB support
 # UHCI controller
 device		uhci
 # OHCI controller
 device		ohci
 # General USB code (mandatory for USB)
 device		usb
 #
 # Generic USB device driver
 device		ugen
 # Human Interface Device (anything with buttons and dials)
 device		uhid
 # USB keyboard
 device		ukbd
 # USB printer
 device		ulpt
 # USB Iomega Zip 100 Drive (Requires scbus and da)
 device		umass
 # USB modem support
 device		umodem
 # USB mouse
 device		ums
 # USB Rio (MP3 Player)
 device		urio
 # USB scanners
 device		uscanner
 #
 # ADMtek USB ethernet. Supports the LinkSys USB100TX,
 # the Billionton USB100, the Melco LU-ATX, the D-Link DSB-650TX
 # and the SMC 2202USB. Also works with the ADMtek AN986 Pegasus
 # eval board.
 device		aue
 #
 # CATC USB-EL1201A USB ethernet. Supports the CATC Netmate
 # and Netmate II, and the Belkin F5U111.
 device		cue
 #
 # Kawasaki LSI ethernet. Supports the LinkSys USB10T,
 # Entrega USB-NET-E45, Peracom Ethernet Adapter, the
 # 3Com 3c19250, the ADS Technologies USB-10BT, the ATen UC10T,
 # the Netgear EA101, the D-Link DSB-650, the SMC 2102USB
 # and 2104USB, and the Corega USB-T.
 device		kue
 
 # debugging options for the USB subsystem
 #
 options 	UHCI_DEBUG
 options 	OHCI_DEBUG
 options 	USB_DEBUG
 
 options 	UGEN_DEBUG
 options 	UHID_DEBUG
 options 	UHUB_DEBUG
 options 	UKBD_DEBUG
 options 	ULPT_DEBUG
 options 	UMASS_DEBUG
 options 	UMS_DEBUG
 
 # options for ukbd:
 options 	UKBD_DFLT_KEYMAP	# specify the built-in keymap
 makeoptions	UKBD_DFLT_KEYMAP=it.iso
 
 #
 # Embedded system options:
 #
 # An embedded system might want to run something other than init.
 options 	INIT_PATH="/sbin/init:/stand/sysinstall"
 
 # Debug options
 options 	BUS_DEBUG       # enable newbus debugging
 options 	DEBUG_VFS_LOCKS # enable vfs lock debugging
 options 	NPX_DEBUG       # enable npx debugging (FPU/math emu)
 
 # More undocumented options for linting.
 # Note that documenting these are not considered an affront.
 
 options 	AHC_DUMP_EEPROM
 options 	AHC_TMODE_ENABLE
 options 	CAM_DEBUG_DELAY
 options 	CLUSTERDEBUG
 options 	COMPAT_LINUX
 options 	CPU_UPGRADE_HW_CACHE
 options 	DEBUG
 options 	DEBUG_LINUX
 #options 	DISABLE_PSE
 options 	ENABLE_ALART
 options 	ENABLE_VFS_IOOPT
 options 	FB_DEBUG
 options 	FB_INSTALL_CDEV
 options 	FE_8BIT_SUPPORT
 options 	I4B_SMP_WORKAROUND
 options 	I586_PMC_GUPROF=0x70000
 options 	IBCS2
 options 	KBDIO_DEBUG=2
 options 	KBD_MAXRETRY=4
 options 	KBD_MAXWAIT=6
 options 	KBD_RESETDELAY=201
 options 	KEY
 options 	LOCKF_DEBUG
 options 	LOUTB
 options 	NETATALKDEBUG
 #options 	OLTR_NO_BULLSEYE_MAC
 #options 	OLTR_NO_HAWKEYE_MAC
 #options 	OLTR_NO_TMS_MAC
 options 	PNPBIOS
 options 	PSM_DEBUG=1
 options 	SCSI_NCR_DEBUG
 options 	SCSI_NCR_MAX_SYNC=10000
 options 	SCSI_NCR_MAX_WIDE=1
 options 	SCSI_NCR_MYADDR=7
 options 	SC_DEBUG_LEVEL
 options 	SC_RENDER_DEBUG
 options 	SHOW_BUSYBUFS	# List buffers that prevent root unmount
 options 	SIMPLELOCK_DEBUG
 options 	SI_DEBUG
 options 	SLIP_IFF_OPTS
 options 	SPX_HACK
 options 	TIMER_FREQ="((14318182+6)/12)"
 options 	VFS_BIO_DEBUG
 options		XBONEHACK