Index: head/sys/alpha/alpha/autoconf.c =================================================================== --- head/sys/alpha/alpha/autoconf.c (revision 38214) +++ head/sys/alpha/alpha/autoconf.c (revision 38215) @@ -1,119 +1,124 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: autoconf.c,v 1.4 1998/07/12 16:07:05 dfr Exp $ + * $Id: autoconf.c,v 1.5 1998/07/22 08:34:19 dfr Exp $ */ #include #include #include #include #include /* for BASE_SLICE, MAX_SLICES */ #include #include #include #include #include #include #include #include #include #include "scbus.h" #if NSCBUS > 0 #include #endif static void configure __P((void *)); SYSINIT(configure, SI_SUB_CONFIGURE, SI_ORDER_FIRST, configure, NULL) static void configure_finish __P((void)); static void configure_start __P((void)); device_t isa_bus_device = 0; static void configure_start() { #if NSCBUS > 0 scsi_configure_start(); #endif } static void configure_finish() { #if NSCBUS > 0 scsi_configure_finish(); #endif } extern void pci_configure(void); /* * Determine i/o configuration for a machine. */ static void configure(void *dummy) { configure_start(); device_add_child(root_bus, platform.iobus, 0, 0); root_bus_configure(); pci_configure(); /* * Probe ISA devices after everything. */ bus_generic_attach(isa_bus_device); configure_finish(); cninit_finish(); /* * Now we're ready to handle (pending) interrupts. * XXX this is slightly misplaced. */ spl0(); cold = 0; } void cpu_rootconf() { + static char rootname[] = "sd0a"; mountrootfsname = "ufs"; - rootdevs[0] = makedev(4, dkmakeminor(0, COMPATIBILITY_SLICE, 0)); - rootdevs[1] = makedev(4, dkmakeminor(1, COMPATIBILITY_SLICE, 0)); - rootdevnames[0] = "sd0a"; + + rootdevs[0] = rootdev; + rootname[2] += dkunit(rootdev); + rootdevnames[0] = rootname; + + rootdevs[1] = makedev(4, dkmakeminor(0, COMPATIBILITY_SLICE, 0)); + rootdevnames[1] = "sd0a"; } void cpu_dumpconf() { } Index: head/sys/alpha/alpha/cpuconf.c =================================================================== --- head/sys/alpha/alpha/cpuconf.c (revision 38214) +++ head/sys/alpha/alpha/cpuconf.c (revision 38215) @@ -1,161 +1,167 @@ -/* $Id$ */ +/* $Id: cpuconf.c,v 1.1 1998/06/10 10:52:18 dfr Exp $ */ /* $NetBSD: cpuconf.c,v 1.10 1998/03/20 21:48:21 thorpej Exp $ */ /* * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Christopher G. Demetriou * for the NetBSD Project. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include "opt_cpu.h" #ifdef DEC_3000_500 extern void dec_3000_500_init __P((int)); #else #define dec_3000_500_init platform_not_configured #endif #ifdef DEC_3000_300 extern void dec_3000_300_init __P((int)); #else #define dec_3000_300_init platform_not_configured #endif #ifdef DEC_AXPPCI_33 extern void dec_axppci_33_init __P((int)); #else #define dec_axppci_33_init platform_not_configured #endif #ifdef DEC_KN8AE extern void dec_kn8ae_init __P((int)); #else #define dec_kn8ae_init platform_not_configured #endif #ifdef DEC_2100_A50 extern void dec_2100_a50_init __P((int)); #else #define dec_2100_a50_init platform_not_configured #endif #ifdef DEC_KN20AA extern void dec_kn20aa_init __P((int)); #else #define dec_kn20aa_init platform_not_configured #endif #ifdef DEC_EB64PLUS extern void dec_eb64plus_init __P((int)); #else #define dec_eb64plus_init platform_not_configured #endif #ifdef DEC_EB164 extern void dec_eb164_init __P((int)); #else #define dec_eb164_init platform_not_configured #endif #ifdef AVALON_A12 extern void avalon_a12_init __P((int)); #else #define avalon_a12_init platform_not_configured #endif +#ifdef DEC_ST550 +extern void st550_init __P((int)); +#else +#define st550_init platform_not_configured +#endif + struct cpuinit cpuinit[] = { cpu_notsupp("???"), /* 0: ??? */ cpu_notsupp("ST_ADU"), /* 1: ST_ADU */ cpu_notsupp("ST_DEC_4000"), /* 2: ST_DEC_4000 */ cpu_notsupp("ST_DEC_7000"), /* 3: ST_DEC_7000 */ cpu_init(dec_3000_500_init,"DEC_3000_500"), /* 4: ST_DEC_3000_500 */ cpu_notsupp("???"), /* 5: ??? */ cpu_notsupp("ST_DEC_2000_300"), /* 6: ST_DEC_2000_300 */ cpu_init(dec_3000_300_init,"DEC_3000_300"), /* 7: ST_DEC_3000_300 */ cpu_init(avalon_a12_init,"ST_AVALON_A12"), /* 8: ST_AVALON_A12 */ cpu_notsupp("ST_DEC_2100_A500"), /* 9: ST_DEC_2100_A500 */ cpu_notsupp("ST_DEC_APXVME_64"), /* 10: ST_DEC_APXVME_64 */ cpu_init(dec_axppci_33_init,"DEC_AXPPCI_33"),/* 11: ST_DEC_AXPPCI_33 */ cpu_init(dec_kn8ae_init,"DEC_KN8AE"), /* 12: ST_DEC_21000 */ cpu_init(dec_2100_a50_init,"DEC_2100_A50"), /* 13: ST_DEC_2100_A50 */ cpu_notsupp("ST_DEC_MUSTANG"), /* 14: ST_DEC_MUSTANG */ cpu_init(dec_kn20aa_init,"DEC_KN20AA"), /* 15: ST_DEC_KN20AA */ cpu_notsupp("???"), /* 16: ??? */ cpu_notsupp("ST_DEC_1000"), /* 17: ST_DEC_1000 */ cpu_notsupp("???"), /* 18: ??? */ cpu_notsupp("ST_EB66"), /* 19: ST_EB66 */ cpu_init(dec_eb64plus_init,"DEC_EB64PLUS"), /* 20: ST_EB64P */ cpu_notsupp("ST_ALPHABOOK1"), /* 21: ST_ALPHABOOK1 */ cpu_notsupp("ST_DEC_4100"), /* 22: ST_DEC_4100 */ cpu_notsupp("ST_DEC_EV45_PBP"), /* 23: ST_DEC_EV45_PBP */ cpu_notsupp("ST_DEC_2100A_A500"), /* 24: ST_DEC_2100A_A500 */ cpu_notsupp("???"), /* 25: ??? */ cpu_init(dec_eb164_init,"DEC_EB164"), /* 26: ST_EB164 */ cpu_notsupp("ST_DEC_1000A"), /* 27: ST_DEC_1000A */ cpu_notsupp("ST_DEC_ALPHAVME_224"), /* 28: ST_DEC_ALPHAVME_224 */ cpu_notsupp("???"), /* 29: ??? */ - cpu_notsupp("???"), /* 30: ??? */ + cpu_init(st550_init,"DEC_ST550"), /* 30: ST_DEC_550 */ cpu_notsupp("???"), /* 31: ??? */ cpu_notsupp("ST_DEC_EV56_PBP"), /* 32: ST_DEC_EV56_PBP */ cpu_notsupp("ST_DEC_ALPHAVME_320"), /* 33: ST_DEC_ALPHAVME_320 */ }; int ncpuinit = (sizeof(cpuinit) / sizeof(cpuinit[0])); void platform_not_configured(int cputype) { printf("\n"); printf("Support for system type %d is not present in this kernel.\n", cputype); printf("Please build a kernel with \"options %s\" and reboot.\n", cpuinit[cputype].option); printf("\n"); panic("platform not configured\n"); } void platform_not_supported(int cputype) { const char *typestr; if (cputype >= ncpuinit) typestr = "???"; else typestr = cpuinit[cputype].option; printf("\n"); - printf("NetBSD does not yet support system type %d (%s).\n", cputype, + printf("FreeBSD does not yet support system type %d (%s).\n", cputype, typestr); printf("\n"); panic("platform not supported"); } Index: head/sys/alpha/alpha/dec_2100_a50.c =================================================================== --- head/sys/alpha/alpha/dec_2100_a50.c (nonexistent) +++ head/sys/alpha/alpha/dec_2100_a50.c (revision 38215) @@ -0,0 +1,252 @@ +/* $NetBSD: dec_2100_a50.c,v 1.39 1998/04/17 02:45:19 mjacob Exp $ */ + +/* + * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include "opt_ddb.h" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sio.h" +#include "sc.h" +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void dec_2100_a50_init __P((void)); +static void dec_2100_a50_cons_init __P((void)); +static void dec_2100_a50_device_register __P((struct device *, void *)); +static void dec_2100_a50_intr_map __P((void *)); +void sio_intr_establish __P((int)); +void sio_intr_disestablish __P((int)); +void sio_intr_setup __P((void)); + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +const struct alpha_variation_table dec_2100_a50_variations[] = { + { SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" }, + { SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" }, + { SV_ST_MUSTANG2_4_233, "AlphaStation 200 4/233 (\"Mustang II\")" }, + { SV_ST_AVANTI_4_266, "AlphaStation 250 4/266" }, + { SV_ST_MUSTANG2_4_100, "AlphaStation 200 4/100 (\"Mustang II\")" }, + { SV_ST_AVANTI_4_233, "AlphaStation 255/233" }, + { 0, NULL }, +}; + +void +dec_2100_a50_init() +{ + u_int64_t variation; + + platform.family = "AlphaStation 200/400 (\"Avanti\")"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + variation = hwrpb->rpb_variation & SV_ST_MASK; + if (variation == SV_ST_AVANTI_XXX) { + /* XXX apparently the same? */ + variation = SV_ST_AVANTI; + } + if ((platform.model = alpha_variation_name(variation, + dec_2100_a50_variations)) == NULL) + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "apecs"; + platform.cons_init = dec_2100_a50_cons_init; + platform.pci_intr_map = dec_2100_a50_intr_map; +} + +extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */ + +static void +dec_2100_a50_cons_init() +{ + struct ctb *ctb; + + apecs_init(); + +#ifdef DDB + siogdbattach(0x2f8, 9600); +#endif + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + /* + * force a comconsole on com1 if the SRM has a serial console + */ + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %d\n", + ctb->ctb_term_type); + } +} + +#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */ + +void +dec_2100_a50_intr_map(void *arg) +{ + u_int8_t pirqline; + u_int32_t pirqreg; + int pirq=0; /* gcc -Wuninitialized XXX */ + pcicfgregs *cfg = (pcicfgregs *)arg; + static int intr_setup_done=0; + + /* + * Slot->interrupt translation. Taken from NetBSD + */ + + if(cfg->intpin == 0) + return; + + if(cfg->intpin > 4) + panic("dec_2100_a50_intr_map: bad intpin %d",cfg->intpin); + + switch (cfg->slot) { + case 6: /* NCR SCSI */ + pirq = 3; + break; + + case 11: /* slot 1 */ + case 14: /* slot 3 */ + switch(cfg->intpin){ + case 1: + case 4: + pirq = 0; + break; + case 2: + pirq = 2; + break; + case 3: + pirq = 1; + break; + default: + panic("dec_2100_a50_intr_map bogus PCI pin %d\n", + cfg->intpin); + + } + break; + case 12: /* slot 2 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 1; + break; + case 2: + pirq = 0; + break; + case 3: + pirq = 2; + break; + default: + panic("dec_2100_a50_intr_map bogus PCI pin %d\n", + cfg->intpin); + + }; + break; + + case 13: /* slot 3 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 2; + break; + case 2: + pirq = 1; + break; + case 3: + pirq = 0; + break; + }; + break; + default: + printf("dec_2100_a50_intr_map: weird slot %d\n", + cfg->slot); +/* return;*/ + } + + /* + * read the SIO IRQ routing register to determine where the + * interrupt will actually be routed. Thank you, NetBSD + */ + + pirqreg = chipset.cfgreadl(0, 7, 0, SIO_PCIREG_PIRQ_RTCTRL); + pirqline = (pirqreg >> (pirq * 8)) & 0xff; + if ((pirqline & 0x80) != 0) + panic("bad pirqline %d",pirqline); + pirqline &= 0xf; + cfg->intline = pirqline; +} Property changes on: head/sys/alpha/alpha/dec_2100_a50.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/alpha/dec_axppci_33.c =================================================================== --- head/sys/alpha/alpha/dec_axppci_33.c (nonexistent) +++ head/sys/alpha/alpha/dec_axppci_33.c (revision 38215) @@ -0,0 +1,282 @@ +/* $Id$ */ +/* $NetBSD: dec_axppci_33.c,v 1.38 1998/07/07 08:49:12 ross Exp $ */ + +/* + * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center + */ + +#include "opt_ddb.h" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "sio.h" +#include "sc.h" +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void dec_axppci_33_init __P((void)); +static void dec_axppci_33_cons_init __P((void)); +static void dec_axppci_33_intr_map __P((void *)); + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +const struct alpha_variation_table dec_axppci_33_variations[] = { + { 0, "Alpha PC AXPpci33 (\"NoName\")" }, + { 0, NULL }, +}; + +#define NSIO_PORT 0x26e /* Hardware enabled option: 0x398 */ +#define NSIO_BASE 0 +#define NSIO_INDEX NSIO_BASE +#define NSIO_DATA 1 +#define NSIO_SIZE 2 +#define NSIO_CFG0 0 +#define NSIO_CFG1 1 +#define NSIO_CFG2 2 +#define NSIO_IDE_ENABLE 0x40 + +void +dec_axppci_33_init() +{ + int cfg0val; + u_int64_t variation; + + platform.family = "DEC AXPpci"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + variation = hwrpb->rpb_variation & SV_ST_MASK; + if ((platform.model = alpha_variation_name(variation, + dec_axppci_33_variations)) == NULL) + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "lca"; + platform.cons_init = dec_axppci_33_cons_init; + platform.pci_intr_map = dec_axppci_33_intr_map; + + lca_init(); + + outb(NSIO_PORT + NSIO_INDEX, NSIO_CFG0); + alpha_mb(); + cfg0val = inb(NSIO_PORT + NSIO_DATA); + + cfg0val |= NSIO_IDE_ENABLE; + + outb(NSIO_PORT + NSIO_INDEX, NSIO_CFG0); + alpha_mb(); + outb(NSIO_PORT + NSIO_DATA, cfg0val); + alpha_mb(); + outb(NSIO_PORT + NSIO_DATA, cfg0val); +} + +extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */ + +static void +dec_axppci_33_cons_init() +{ + struct ctb *ctb; + struct lca_config *lcp; + + lca_init(); + +#ifdef DDB + siogdbattach(0x2f8, 9600); +#endif + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + /* + * force a comconsole on com1 if the SRM has a serial console + */ + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %d\n", + ctb->ctb_term_type); + } +} + +#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */ + +void +dec_axppci_33_intr_map(void *arg) +{ + pcicfgregs *cfg = (pcicfgregs *)arg; + int pirq; + u_int32_t pirqreg; + u_int8_t pirqline; + +#ifndef DIAGNOSTIC + pirq = 0; /* XXX gcc -Wuninitialized */ +#endif + + /* + * Slot->interrupt translation. Taken from NetBSD + */ + + if (cfg->intpin == 0) { + /* No IRQ used. */ + return; + } + if (cfg->intpin > 4) { + printf("dec_axppci_33_intr_map: bad interrupt pin %d\n", + cfg->intpin); + return; + } + + switch (cfg->slot) { + case 6: /* NCR SCSI */ + pirq = 3; + break; + + case 11: /* slot 1 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 0; + break; + case 2: + pirq = 2; + break; + case 3: + pirq = 1; + break; +#ifdef DIAGNOSTIC + default: /* XXX gcc -Wuninitialized */ + panic("dec_axppci_33_intr_map: bogus PCI pin %d\n", + cfg->intpin); +#endif + }; + break; + + case 12: /* slot 2 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 1; + break; + case 2: + pirq = 0; + break; + case 3: + pirq = 2; + break; +#ifdef DIAGNOSTIC + default: /* XXX gcc -Wuninitialized */ + panic("dec_axppci_33_intr_map: bogus PCI pin %d\n", + cfg->intpin); +#endif + }; + break; + + case 8: /* slot 3 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 2; + break; + case 2: + pirq = 1; + break; + case 3: + pirq = 0; + break; +#ifdef DIAGNOSTIC + default: /* XXX gcc -Wuninitialized */ + panic("dec_axppci_33_intr_map bogus: PCI pin %d\n", + cfg->intpin); +#endif + }; + break; + + default: + printf("dec_axppci_33_intr_map: weird device number %d\n", + cfg->slot); + return; + } + + pirqreg = chipset.cfgreadl(0, 7, 0, SIO_PCIREG_PIRQ_RTCTRL); +#if 0 + printf("dec_axppci_33_intr_map: device %d pin %c: pirq %d, reg = %x\n", + device, '@' + cfg->intpin, pirq, pirqreg); +#endif + pirqline = (pirqreg >> (pirq * 8)) & 0xff; + if ((pirqline & 0x80) != 0) + panic("bad pirqline %d",pirqline); + pirqline &= 0xf; + +#if 0 + printf("dec_axppci_33_intr_map: device %d pin %c: mapped to line %d\n", + device, '@' + cfg->intpin, pirqline); +#endif + + cfg->intline = pirqline; +} Property changes on: head/sys/alpha/alpha/dec_axppci_33.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/alpha/dec_eb164.c =================================================================== --- head/sys/alpha/alpha/dec_eb164.c (revision 38214) +++ head/sys/alpha/alpha/dec_eb164.c (revision 38215) @@ -1,123 +1,140 @@ -/* $Id: dec_eb164.c,v 1.2 1998/07/12 16:07:43 dfr Exp $ */ +/* $Id: dec_eb164.c,v 1.3 1998/07/22 08:18:34 dfr Exp $ */ /* $NetBSD: dec_eb164.c,v 1.26 1998/04/17 02:45:19 mjacob Exp $ */ /* * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ /* * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center */ #include "opt_ddb.h" #include #include #include #include #include #include #include +#include + #include "sio.h" #include "sc.h" #ifndef CONSPEED #define CONSPEED TTYDEF_SPEED #endif static int comcnrate = CONSPEED; void dec_eb164_init __P((void)); static void dec_eb164_cons_init __P((void)); +static void eb164_intr_init(void); extern void eb164_intr_enable(int irq); extern void eb164_intr_disable(int irq); +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + void dec_eb164_init() { platform.family = "EB164"; if ((platform.model = alpha_dsr_sysname()) == NULL) { /* XXX Don't know the system variations, yet. */ platform.model = alpha_unknown_sysname(); } platform.iobus = "cia"; platform.cons_init = dec_eb164_cons_init; + platform.pci_intr_init = eb164_intr_init; platform.pci_intr_map = NULL; platform.pci_intr_disable = eb164_intr_disable; platform.pci_intr_enable = eb164_intr_enable; } static void dec_eb164_cons_init() { struct ctb *ctb; cia_init(); #ifdef DDB siogdbattach(0x2f8, 57600); #endif ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); switch (ctb->ctb_term_type) { case 2: /* serial console ... */ /* XXX */ { /* * Delay to allow PROM putchars to complete. * FIFO depth * character time, * character time = (1000000 / (defaultrate / 10)) */ DELAY(160000000 / comcnrate); if (siocnattach(0x3f8, comcnrate)) panic("can't init serial console"); break; } case 3: /* display console ... */ /* XXX */ #if NSC > 0 sccnattach(); #else panic("not configured to use display && keyboard console"); #endif break; default: printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); panic("consinit: unknown console type %d\n", ctb->ctb_term_type); } +} + +static void +eb164_intr_init() +{ + /* + * Enable ISA-PCI cascade interrupt. + */ + eb164_intr_enable(4); } Index: head/sys/alpha/alpha/dec_kn20aa.c =================================================================== --- head/sys/alpha/alpha/dec_kn20aa.c (revision 38214) +++ head/sys/alpha/alpha/dec_kn20aa.c (revision 38215) @@ -1,338 +1,354 @@ /* $NetBSD: dec_kn20aa.c,v 1.38 1998/04/17 02:45:19 mjacob Exp $ */ /* * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ /* * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center */ #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include +#include #include "sio.h" #include "sc.h" #ifndef CONSPEED #define CONSPEED TTYDEF_SPEED #endif static int comcnrate = CONSPEED; void dec_kn20aa_init __P((void)); static void dec_kn20aa_cons_init __P((void)); +static void dec_kn20aa_intr_init __P((void)); static void dec_kn20aa_intr_map __P((void *)); static void dec_kn20aa_intr_disable __P((int)); static void dec_kn20aa_intr_enable __P((int)); +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + #if 0 static void dec_kn20aa_device_register __P((struct device *, void *)); #endif const struct alpha_variation_table dec_kn20aa_variations[] = { { 0, "AlphaStation 500 or 600 (KN20AA)" }, { 0, NULL }, }; extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */ void dec_kn20aa_init() { u_int64_t variation; platform.family = "AlphaStation 500 or 600 (KN20AA)"; if ((platform.model = alpha_dsr_sysname()) == NULL) { variation = hwrpb->rpb_variation & SV_ST_MASK; if ((platform.model = alpha_variation_name(variation, dec_kn20aa_variations)) == NULL) platform.model = alpha_unknown_sysname(); } platform.iobus = "cia"; platform.cons_init = dec_kn20aa_cons_init; + platform.pci_intr_init = dec_kn20aa_intr_init; platform.pci_intr_map = dec_kn20aa_intr_map; platform.pci_intr_disable = dec_kn20aa_intr_disable; platform.pci_intr_enable = dec_kn20aa_intr_enable; } static void dec_kn20aa_cons_init() { struct ctb *ctb; cia_init(); #ifdef DDB siogdbattach(0x2f8, 9600); #endif ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); switch (ctb->ctb_term_type) { case 2: /* serial console ... */ /* XXX */ { /* * Delay to allow PROM putchars to complete. * FIFO depth * character time, * character time = (1000000 / (defaultrate / 10)) */ DELAY(160000000 / comcnrate); comconsole = 0; if (siocnattach(0x3f8, comcnrate)) panic("can't init serial console"); break; } case 3: /* display console ... */ /* XXX */ #if NPCKBD > 0 sccnattach(); #else panic("not configured to use display && keyboard console"); break; default: printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); panic("consinit: unknown console type %d\n", ctb->ctb_term_type); } #endif } #if 0 static void dec_kn20aa_device_register(dev, aux) struct device *dev; void *aux; { static int found, initted, scsiboot, netboot; static struct device *pcidev, *scsidev; struct bootdev_data *b = bootdev_data; struct device *parent = dev->dv_parent; struct cfdata *cf = dev->dv_cfdata; struct cfdriver *cd = cf->cf_driver; if (found) return; if (!initted) { scsiboot = (strcmp(b->protocol, "SCSI") == 0); netboot = (strcmp(b->protocol, "BOOTP") == 0); #if 0 printf("scsiboot = %d, netboot = %d\n", scsiboot, netboot); #endif initted =1; } if (pcidev == NULL) { if (strcmp(cd->cd_name, "pci")) return; else { struct pcibus_attach_args *pba = aux; if ((b->slot / 1000) != pba->pba_bus) return; pcidev = dev; #if 0 printf("\npcidev = %s\n", pcidev->dv_xname); #endif return; } } if (scsiboot && (scsidev == NULL)) { if (parent != pcidev) return; else { struct pci_attach_args *pa = aux; if ((b->slot % 1000) != pa->pa_device) return; /* XXX function? */ scsidev = dev; #if 0 printf("\nscsidev = %s\n", scsidev->dv_xname); #endif return; } } if (scsiboot && (!strcmp(cd->cd_name, "sd") || !strcmp(cd->cd_name, "st") || !strcmp(cd->cd_name, "cd"))) { struct scsipibus_attach_args *sa = aux; if (parent->dv_parent != scsidev) return; if (b->unit / 100 != sa->sa_sc_link->scsipi_scsi.target) return; /* XXX LUN! */ switch (b->boot_dev_type) { case 0: if (strcmp(cd->cd_name, "sd") && strcmp(cd->cd_name, "cd")) return; break; case 1: if (strcmp(cd->cd_name, "st")) return; break; default: return; } /* we've found it! */ booted_device = dev; #if 0 printf("\nbooted_device = %s\n", booted_device->dv_xname); #endif found = 1; } if (netboot) { if (parent != pcidev) return; else { struct pci_attach_args *pa = aux; if ((b->slot % 1000) != pa->pa_device) return; /* XXX function? */ booted_device = dev; #if 0 printf("\nbooted_device = %s\n", booted_device->dv_xname); #endif found = 1; return; } } } #endif #define KN20AA_MAX_IRQ 32 +void +dec_kn20aa_intr_init() +{ + /* + * Enable ISA-PCI cascade interrupt. + */ + dec_kn20aa_intr_enable(31); +} + void dec_kn20aa_intr_map(void *arg) { pcicfgregs *cfg = (pcicfgregs *)arg; /* * Slot->interrupt translation. Appears to work, though it * may not hold up forever. * * The DEC engineers who did this hardware obviously engaged * in random drug testing. */ switch (cfg->slot) { case 11: case 12: cfg->intline = ((cfg->slot - 11) + 0) * 4; break; case 7: cfg->intline = 8; break; case 9: cfg->intline = 12; break; case 6: /* 21040 on AlphaStation 500 */ cfg->intline = 13; break; case 8: cfg->intline = 16; break; case 10: /* 8275EB on AlphaStation 500 */ return; default: if(!cfg->bus){ printf("dec_kn20aa_intr_map: weird slot %d\n", cfg->slot); return; } else { cfg->intline = cfg->slot; } } cfg->intline += cfg->bus*16; if (cfg->intline > KN20AA_MAX_IRQ) panic("dec_kn20aa_intr_map: cfg->intline too large (%d)\n", cfg->intline); } void dec_kn20aa_intr_enable(irq) int irq; { /* * From disassembling small bits of the OSF/1 kernel: * the following appears to enable a given interrupt request. * "blech." I'd give valuable body parts for better docs or * for a good decompiler. */ alpha_mb(); REGVAL(0x8780000000L + 0x40L) |= (1 << irq); /* XXX */ alpha_mb(); } void dec_kn20aa_intr_disable(irq) int irq; { alpha_mb(); REGVAL(0x8780000000L + 0x40L) &= ~(1 << irq); /* XXX */ alpha_mb(); } Index: head/sys/alpha/alpha/dec_st550.c =================================================================== --- head/sys/alpha/alpha/dec_st550.c (nonexistent) +++ head/sys/alpha/alpha/dec_st550.c (revision 38215) @@ -0,0 +1,271 @@ +/* + * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sio.h" +#include "sc.h" + +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void st550_init __P((void)); +static void st550_cons_init __P((void)); +static void st550_intr_init __P((void)); +static void pyxis_intr_enable __P((int)); +static void pyxis_intr_disable __P((int)); +static void st550_intr_enable __P((int)); +static void st550_intr_disable __P((int)); +static void st550_intr_map __P((void *)); +#define ST550_PCI_IRQ_BEGIN 8 +#define ST550_PCI_MAX_IRQ 47 + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +void +st550_init() +{ + int i; + platform.family = "Digital Personal Workstation (Miata)"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + /* XXX Don't know the system variations, yet. */ + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "cia"; + platform.cons_init = st550_cons_init; + platform.pci_intr_init = st550_intr_init; + platform.pci_intr_map = st550_intr_map; + platform.pci_intr_disable = st550_intr_disable; + platform.pci_intr_enable = st550_intr_enable; +} + +extern int comconsole; + +static void +st550_cons_init() +{ + struct ctb *ctb; + + cia_init(); + +#ifdef DDB + siogdbattach(0x2f8, 57600); +#endif + + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %d\n", + ctb->ctb_term_type); + } +} + +static void +st550_intr_init() +{ + /* This is here because we need to disable extraneous pci interrupts. */ + int i; + for(i = ST550_PCI_IRQ_BEGIN; i <= ST550_PCI_MAX_IRQ; i++) + pyxis_intr_disable(i); + /* From Linux... */ + pyxis_intr_enable(2); /* enable HALT switch */ + pyxis_intr_enable(6); /* enable timer */ + pyxis_intr_enable(7); /* enable ISA PIC cascade */ +} + +static void +st550_intr_map(void *arg) +{ + pcicfgregs *cfg = (pcicfgregs *)arg; + + /* There are two main variants of Miata: Miata 1 (Intel SIO) + * and Miata {1.5,2} (Cypress). + * + * The Miata 1 has a CMD PCI IDE wired to compatibility mode at + * slot 4 of bus 0. This variant has the Pyxis DMA bug. + * + * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives + * on device 7 of bus 0. This device has PCI IDE wired to + * compatibility mode on functions 1 and 2. + * + * There will be no interrupt mapping for these devices, so just + * bail out now. + */ + if(cfg->bus == 0) { + if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { + /* Miata 1 */ + if (cfg->slot == 7) + return; + else if (cfg->func == 4) + return; + } else { + /* Miata 1.5 or Miata 2 */ + if (cfg->slot == 7) { + if (cfg->func == 0) + return; + return; + } + } + } + /* Account for the PCI interrupt offset. */ + /* cfg->intline += ST550_PCI_IRQ_BEGIN; */ + return; +} + +/* + * The functions below were written based on a draft copy of the + * 21174 TRM. + */ +static void +pyxis_intr_enable(irq) + int irq; +{ + volatile u_int64_t temp; + + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); + alpha_mb(); + + temp |= ( 1L << irq ); + REGVAL64(PYXIS_INT_MASK) = temp; + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); +#ifdef 0 + printf("pyxis_intr_enable: enabling %d, current mask= ", irq); + { + int i; + for ( i = 0; i < 61; i++) + if (temp & (1 << i)){ + printf("%d " ,i); + } + printf("\n"); + } +#endif + +} + +static void +pyxis_intr_disable(irq) + int irq; +{ + volatile u_int64_t temp; + + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); + temp &= ~(1L << irq ); + REGVAL64(PYXIS_INT_MASK) = temp; + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); +#if 0 + printf("pyxis_intr_disable: disabled %d, current mask ", irq); + { + int i; + for ( i = 0; i < 61; i++) + if (temp & (1 << i)){ + printf("%d ",i); + } + printf("\n"); + } +#endif + +} + +static void +st550_intr_enable(irq) + int irq; +{ + pyxis_intr_enable(irq + ST550_PCI_IRQ_BEGIN); +} + +static void +st550_intr_disable(irq) + int irq; +{ + pyxis_intr_disable(irq + ST550_PCI_IRQ_BEGIN); +} Property changes on: head/sys/alpha/alpha/dec_st550.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/alpha/interrupt.c =================================================================== --- head/sys/alpha/alpha/interrupt.c (revision 38214) +++ head/sys/alpha/alpha/interrupt.c (revision 38215) @@ -1,317 +1,317 @@ -/* $Id: interrupt.c,v 1.3 1998/07/05 12:22:56 dfr Exp $ */ +/* $Id: interrupt.c,v 1.4 1998/07/12 16:09:27 dfr Exp $ */ /* $NetBSD: interrupt.c,v 1.23 1998/02/24 07:38:01 thorpej Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. * All rights reserved. * * Authors: Keith Bostic, Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ /* * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center. * Redistribute and modify at will, leaving only this additional copyright * notice. */ #include /* RCS ID & Copyright macro defns */ /* __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.23 1998/02/24 07:38:01 thorpej Exp $");*/ #include #include #include #include #include #include #include #include #include #include #include #if 0 #ifdef EVCNT_COUNTERS #include struct evcnt clock_intr_evcnt; /* event counter for clock intrs. */ #else #include #endif #endif volatile int mc_expected, mc_received; void interrupt(a0, a1, a2, framep) unsigned long a0, a1, a2; struct trapframe *framep; { { struct proc* p = curproc; if (!p) p = &proc0; if ((caddr_t) framep < (caddr_t) p->p_addr + 1024) - printf("possible stack overflow\n"); + panic("possible stack overflow\n"); } switch (a0) { case ALPHA_INTR_XPROC: /* interprocessor interrupt */ printf("interprocessor interrupt!\n"); break; case ALPHA_INTR_CLOCK: /* clock interrupt */ cnt.v_intr++; #if 0 #ifdef EVCNT_COUNTERS clock_intr_evcnt.ev_count++; #else intrcnt[INTRCNT_CLOCK]++; #endif #endif if (platform.clockintr) (*platform.clockintr)(framep); break; case ALPHA_INTR_ERROR: /* Machine Check or Correctable Error */ a0 = alpha_pal_rdmces(); if (platform.mcheck_handler) (*platform.mcheck_handler)(a0, framep, a1, a2); else machine_check(a0, framep, a1, a2); break; case ALPHA_INTR_DEVICE: /* I/O device interrupt */ cnt.v_intr++; if (platform.iointr) (*platform.iointr)(framep, a1); break; case ALPHA_INTR_PERF: /* interprocessor interrupt */ printf("performance interrupt!\n"); break; case ALPHA_INTR_PASSIVE: #if 0 printf("passive release interrupt vec 0x%lx (ignoring)\n", a1); #endif break; default: panic("unexpected interrupt: type 0x%lx vec 0x%lx a2 0x%lx\n", a0, a1, a2); /* NOTREACHED */ } } void set_iointr(niointr) void (*niointr) __P((void *, unsigned long)); { if (platform.iointr) panic("set iointr twice"); platform.iointr = niointr; } void machine_check(mces, framep, vector, param) unsigned long mces; struct trapframe *framep; unsigned long vector, param; { const char *type; /* Make sure it's an error we know about. */ if ((mces & (ALPHA_MCES_MIP|ALPHA_MCES_SCE|ALPHA_MCES_PCE)) == 0) { type = "fatal machine check or error (unknown type)"; goto fatal; } /* Machine checks. */ if (mces & ALPHA_MCES_MIP) { /* If we weren't expecting it, then we punt. */ if (!mc_expected) { type = "unexpected machine check"; goto fatal; } mc_expected = 0; mc_received = 1; } /* System correctable errors. */ if (mces & ALPHA_MCES_SCE) printf("Warning: received system correctable error.\n"); /* Processor correctable errors. */ if (mces & ALPHA_MCES_PCE) printf("Warning: received processor correctable error.\n"); /* Clear pending machine checks and correctable errors */ alpha_pal_wrmces(mces); return; fatal: /* Clear pending machine checks and correctable errors */ alpha_pal_wrmces(mces); printf("\n"); printf("%s:\n", type); printf("\n"); printf(" mces = 0x%lx\n", mces); printf(" vector = 0x%lx\n", vector); printf(" param = 0x%lx\n", param); printf(" pc = 0x%lx\n", framep->tf_regs[FRAME_PC]); printf(" ra = 0x%lx\n", framep->tf_regs[FRAME_RA]); printf(" curproc = %p\n", curproc); if (curproc != NULL) printf(" pid = %d, comm = %s\n", curproc->p_pid, curproc->p_comm); printf("\n"); panic("machine check"); } int badaddr(addr, size) void *addr; size_t size; { return(badaddr_read(addr, size, NULL)); } int badaddr_read(addr, size, rptr) void *addr; size_t size; void *rptr; { long rcpt; /* Get rid of any stale machine checks that have been waiting. */ alpha_pal_draina(); /* Tell the trap code to expect a machine check. */ mc_received = 0; mc_expected = 1; /* Read from the test address, and make sure the read happens. */ alpha_mb(); switch (size) { case sizeof (u_int8_t): if (alpha_implver() == ALPHA_IMPLVER_EV5 && alpha_amask(ALPHA_AMASK_BWX) == 0) rcpt = ldbu((vm_offset_t)addr); else rcpt = *(volatile u_int8_t *)addr; break; case sizeof (u_int16_t): if (alpha_implver() == ALPHA_IMPLVER_EV5 && alpha_amask(ALPHA_AMASK_BWX) == 0) rcpt = ldwu((vm_offset_t)addr); else rcpt = *(volatile u_int16_t *)addr; break; case sizeof (u_int32_t): rcpt = *(volatile u_int32_t *)addr; break; case sizeof (u_int64_t): rcpt = *(volatile u_int64_t *)addr; break; default: panic("badaddr: invalid size (%ld)\n", size); } alpha_mb(); /* Make sure we took the machine check, if we caused one. */ alpha_pal_draina(); /* disallow further machine checks */ mc_expected = 0; if (rptr) { switch (size) { case sizeof (u_int8_t): *(volatile u_int8_t *)rptr = rcpt; break; case sizeof (u_int16_t): *(volatile u_int16_t *)rptr = rcpt; break; case sizeof (u_int32_t): *(volatile u_int32_t *)rptr = rcpt; break; case sizeof (u_int64_t): *(volatile u_int64_t *)rptr = rcpt; break; } } /* Return non-zero (i.e. true) if it's a bad address. */ return (mc_received); } #define HASHVEC(vector) ((vector) % 31) static struct alpha_intr_list alpha_intr_hash[31]; struct alpha_intr * alpha_create_intr(int vector, driver_intr_t *intr, void *arg) { struct alpha_intr *i; i = malloc(sizeof(struct alpha_intr), M_DEVBUF, M_NOWAIT); if (!i) return NULL; i->vector = vector; i->intr = intr; i->arg = arg; return i; } int alpha_connect_intr(struct alpha_intr *i) { int h = HASHVEC(i->vector); int s; s = splhigh(); LIST_INSERT_HEAD(&alpha_intr_hash[h], i, list); splx(s); return 0; } void -alpha_dispatch_intr(int vector) +alpha_dispatch_intr(void *frame, unsigned long vector) { struct alpha_intr *i; int h = HASHVEC(vector); for (i = LIST_FIRST(&alpha_intr_hash[h]); i; i = LIST_NEXT(i, list)) if (i->vector == vector) i->intr(i->arg); } Index: head/sys/alpha/alpha/locore.s =================================================================== --- head/sys/alpha/alpha/locore.s (revision 38214) +++ head/sys/alpha/alpha/locore.s (revision 38215) @@ -1,297 +1,295 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: locore.s,v 1.1 1998/06/10 10:52:50 dfr Exp $ + * $Id: locore.s,v 1.2 1998/06/10 19:59:40 dfr Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ #include #include #include /* * PTmap is recursive pagemap at top of virtual address space. * Within PTmap, the lev1 and lev0 page tables can be found. */ .globl PTmap,PTlev2,PTlev1,PTlev1pte .equ PTmap,VPTBASE .equ PTlev2,PTmap + (PTLEV1I << ALPHA_L2SHIFT) .equ PTlev1,PTlev2 + (PTLEV1I << ALPHA_L3SHIFT) .equ PTlev1pte,PTlev1 + (PTLEV1I * PTESIZE) /* * Perform actions necessary to switch to a new context. The * hwpcb should be in a0. */ #define SWITCH_CONTEXT \ /* Make a note of the context we're running on. */ \ stq a0, curpcb ; \ \ /* Swap in the new context. */ \ call_pal PAL_OSF1_swpctx .text - EXPORT(kernel_text) -kernel_text: NESTED(locorestart, 1, 0, ra, 0, 0) br pv,1f 1: LDGP(pv) /* Load KGP with current GP. */ or a0,zero,s0 /* save pfn */ or gp,zero,a0 call_pal PAL_OSF1_wrkgp /* clobbers a0, t0, t8-t11 */ or s0,zero,a0 /* restore pfn */ /* * Call alpha_init() to do pre-main initialization. * alpha_init() gets the arguments we were called with, * which are already in a0, a1, a2, a3, and a4. */ CALL(alpha_init) /* Set up the virtual page table pointer. */ ldiq a0, VPTBASE call_pal PAL_OSF1_wrvptptr /* clobbers a0, t0, t8-t11 */ /* * Switch to proc0's PCB, which is at U_PCB off of proc0paddr. */ lda t0,proc0 /* get phys addr of pcb */ ldq a0,P_MD_PCBPADDR(t0) SWITCH_CONTEXT /* * We've switched to a new page table base, so invalidate the TLB * and I-stream. This happens automatically everywhere but here. */ ldiq a0, -2 /* TBIA */ call_pal PAL_OSF1_tbi call_pal PAL_imb /* * Construct a fake trap frame, so execve() can work normally. * Note that setregs() is responsible for setting its contents * to 'reasonable' values. */ lda sp,-(FRAME_SIZE * 8)(sp) /* space for struct trapframe */ mov sp, a0 /* main()'s arg is frame ptr */ CALL(main) /* go to main()! */ /* * Call exception_return, to simulate return from (fake) * exception to user-land, running process 1, init! */ jmp zero, exception_return /* "And that's all she wrote." */ END(locorestart) /**************************************************************************/ /* * Signal "trampoline" code. Invoked from RTE setup by sendsig(). * * On entry, stack & registers look like: * * a0 signal number * a1 signal specific code * a2 pointer to signal context frame (scp) * a3 address of handler * sp+0 saved hardware state * . * . * scp+0 beginning of signal context frame */ NESTED(sigcode,0,0,ra,0,0) lda sp, -16(sp) /* save the sigcontext pointer */ stq a2, 0(sp) jsr ra, (t12) /* call the signal handler (t12==pv) */ ldq a0, 0(sp) /* get the sigcontext pointer */ lda sp, 16(sp) CALLSYS_NOERROR(sigreturn) /* and call sigreturn() with it. */ mov v0, a0 /* if that failed, get error code */ CALLSYS_NOERROR(exit) /* and call exit() with it. */ XNESTED(esigcode,0) END(sigcode) .data EXPORT(szsigcode) .quad esigcode-sigcode .text /**************************************************************************/ /* * savefpstate: Save a process's floating point state. * * Arguments: * a0 'struct fpstate *' to save into */ LEAF(savefpstate, 1) LDGP(pv) /* save all of the FP registers */ lda t1, FPREG_FPR_REGS(a0) /* get address of FP reg. save area */ stt $f0, (0 * 8)(t1) /* save first register, using hw name */ stt $f1, (1 * 8)(t1) /* etc. */ stt $f2, (2 * 8)(t1) stt $f3, (3 * 8)(t1) stt $f4, (4 * 8)(t1) stt $f5, (5 * 8)(t1) stt $f6, (6 * 8)(t1) stt $f7, (7 * 8)(t1) stt $f8, (8 * 8)(t1) stt $f9, (9 * 8)(t1) stt $f10, (10 * 8)(t1) stt $f11, (11 * 8)(t1) stt $f12, (12 * 8)(t1) stt $f13, (13 * 8)(t1) stt $f14, (14 * 8)(t1) stt $f15, (15 * 8)(t1) stt $f16, (16 * 8)(t1) stt $f17, (17 * 8)(t1) stt $f18, (18 * 8)(t1) stt $f19, (19 * 8)(t1) stt $f20, (20 * 8)(t1) stt $f21, (21 * 8)(t1) stt $f22, (22 * 8)(t1) stt $f23, (23 * 8)(t1) stt $f24, (24 * 8)(t1) stt $f25, (25 * 8)(t1) stt $f26, (26 * 8)(t1) stt $f27, (27 * 8)(t1) .set noat stt $f28, (28 * 8)(t1) .set at stt $f29, (29 * 8)(t1) stt $f30, (30 * 8)(t1) /* * Then save the FPCR; note that the necessary 'trapb's are taken * care of on kernel entry and exit. */ mf_fpcr ft0 stt ft0, FPREG_FPR_CR(a0) /* store to FPCR save area */ RET END(savefpstate) /**************************************************************************/ /* * restorefpstate: Restore a process's floating point state. * * Arguments: * a0 'struct fpstate *' to restore from */ LEAF(restorefpstate, 1) LDGP(pv) /* * Restore the FPCR; note that the necessary 'trapb's are taken care of * on kernel entry and exit. */ ldt ft0, FPREG_FPR_CR(a0) /* load from FPCR save area */ mt_fpcr ft0 /* Restore all of the FP registers. */ lda t1, FPREG_FPR_REGS(a0) /* get address of FP reg. save area */ ldt $f0, (0 * 8)(t1) /* restore first reg., using hw name */ ldt $f1, (1 * 8)(t1) /* etc. */ ldt $f2, (2 * 8)(t1) ldt $f3, (3 * 8)(t1) ldt $f4, (4 * 8)(t1) ldt $f5, (5 * 8)(t1) ldt $f6, (6 * 8)(t1) ldt $f7, (7 * 8)(t1) ldt $f8, (8 * 8)(t1) ldt $f9, (9 * 8)(t1) ldt $f10, (10 * 8)(t1) ldt $f11, (11 * 8)(t1) ldt $f12, (12 * 8)(t1) ldt $f13, (13 * 8)(t1) ldt $f14, (14 * 8)(t1) ldt $f15, (15 * 8)(t1) ldt $f16, (16 * 8)(t1) ldt $f17, (17 * 8)(t1) ldt $f18, (18 * 8)(t1) ldt $f19, (19 * 8)(t1) ldt $f20, (20 * 8)(t1) ldt $f21, (21 * 8)(t1) ldt $f22, (22 * 8)(t1) ldt $f23, (23 * 8)(t1) ldt $f24, (24 * 8)(t1) ldt $f25, (25 * 8)(t1) ldt $f26, (26 * 8)(t1) ldt $f27, (27 * 8)(t1) ldt $f28, (28 * 8)(t1) ldt $f29, (29 * 8)(t1) ldt $f30, (30 * 8)(t1) RET END(restorefpstate) /* * When starting init, call this to configure the process for user * mode. This will be inherited by other processes. */ LEAF_NOPROFILE(prepare_usermode, 0) RET END(prepare_usermode) .data EXPORT(proc0paddr) .quad 0 .text Index: head/sys/alpha/alpha/machdep.c =================================================================== --- head/sys/alpha/alpha/machdep.c (revision 38214) +++ head/sys/alpha/alpha/machdep.c (revision 38215) @@ -1,1803 +1,1819 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: machdep.c,v 1.9 1998/07/29 18:36:29 dfr Exp $ + * $Id: machdep.c,v 1.10 1998/07/30 08:10:26 dfr Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, * NASA Ames Research Center and by Chris G. Demetriou. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the NetBSD * Foundation, Inc. and its contributors. * 4. Neither the name of The NetBSD Foundation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ #include "opt_ddb.h" #include "opt_simos.h" #include "opt_sysvipc.h" #include "opt_msgbuf.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef SYSVSHM #include #endif #ifdef SYSVMSG #include #endif #ifdef SYSVSEM #include #endif struct proc* curproc; struct proc* fpcurproc; struct pcb* curpcb; u_int64_t cycles_per_usec; u_int32_t cycles_per_sec; int whichqs, whichrtqs, whichidqs; int adjkerntz; int cold = 1; struct platform platform; alpha_chipset_t chipset; struct bootinfo_kernel bootinfo; struct timeval switchtime; struct user *proc0paddr; char machine[] = "alpha"; SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, ""); static char cpu_model[128]; SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, ""); #ifdef DDB /* start and end of kernel symbol table */ void *ksym_start, *ksym_end; #endif /* for cpu_sysctl() */ int alpha_unaligned_print = 1; /* warn about unaligned accesses */ int alpha_unaligned_fix = 1; /* fix up unaligned accesses */ int alpha_unaligned_sigbus = 0; /* don't SIGBUS on fixed-up accesses */ static void cpu_startup __P((void *)); SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL) static MALLOC_DEFINE(M_MBUF, "mbuf", "mbuf"); struct msgbuf *msgbufp=0; int bootverbose = 0, Maxmem = 0; long dumplo; int totalphysmem; /* total amount of physical memory in system */ int physmem; /* physical memory used by NetBSD + some rsvd */ int resvmem; /* amount of memory reserved for PROM */ int unusedmem; /* amount of memory for OS that we don't use */ int unknownmem; /* amount of memory with an unknown use */ int ncpus; /* number of cpus */ vm_offset_t phys_avail[10]; /* must be 2 less so 0 0 can signal end of chunks */ #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(vm_offset_t)) - 2) static void setup_netisrs __P((struct linker_set *)); /* XXX declare elsewhere */ static void identifycpu __P((void)); static vm_offset_t buffer_sva, buffer_eva; vm_offset_t clean_sva, clean_eva; static vm_offset_t pager_sva, pager_eva; extern struct linker_set netisr_set; #define offsetof(type, member) ((size_t)(&((type *)0)->member)) static void cpu_startup(dummy) void *dummy; { register unsigned i; register caddr_t v; vm_offset_t maxaddr; vm_size_t size = 0; vm_offset_t firstaddr; vm_offset_t minaddr; if (boothowto & RB_VERBOSE) bootverbose++; /* * Good {morning,afternoon,evening,night}. */ printf(version); identifycpu(); /* startrtclock(); */ #ifdef PERFMON perfmon_init(); #endif printf("real memory = %d (%dK bytes)\n", alpha_ptob(Maxmem), alpha_ptob(Maxmem) / 1024); /* * Display any holes after the first chunk of extended memory. */ if (bootverbose) { int indx; printf("Physical memory chunk(s):\n"); for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { int size1 = phys_avail[indx + 1] - phys_avail[indx]; printf("0x%08lx - 0x%08lx, %d bytes (%d pages)\n", phys_avail[indx], phys_avail[indx + 1] - 1, size1, size1 / PAGE_SIZE); } } /* * Quickly wire in netisrs. */ setup_netisrs(&netisr_set); /* * Calculate callout wheel size */ for (callwheelsize = 1, callwheelbits = 0; callwheelsize < ncallout; callwheelsize <<= 1, ++callwheelbits) ; callwheelmask = callwheelsize - 1; /* * Allocate space for system data structures. * The first available kernel virtual address is in "v". * As pages of kernel virtual memory are allocated, "v" is incremented. * As pages of memory are allocated and cleared, * "firstaddr" is incremented. * An index into the kernel page table corresponding to the * virtual memory address maintained in "v" is kept in "mapaddr". */ /* * Make two passes. The first pass calculates how much memory is * needed and allocates it. The second pass assigns virtual * addresses to the various data structures. */ firstaddr = 0; again: v = (caddr_t)firstaddr; #define valloc(name, type, num) \ (name) = (type *)v; v = (caddr_t)((name)+(num)) #define valloclim(name, type, num, lim) \ (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) valloc(callout, struct callout, ncallout); valloc(callwheel, struct callout_tailq, callwheelsize); #ifdef SYSVSHM valloc(shmsegs, struct shmid_ds, shminfo.shmmni); #endif #ifdef SYSVSEM valloc(sema, struct semid_ds, seminfo.semmni); valloc(sem, struct sem, seminfo.semmns); /* This is pretty disgusting! */ valloc(semu, int, (seminfo.semmnu * seminfo.semusz) / sizeof(int)); #endif #ifdef SYSVMSG valloc(msgpool, char, msginfo.msgmax); valloc(msgmaps, struct msgmap, msginfo.msgseg); valloc(msghdrs, struct msg, msginfo.msgtql); valloc(msqids, struct msqid_ds, msginfo.msgmni); #endif if (nbuf == 0) { nbuf = 30; if( physmem > 1024) nbuf += min((physmem - 1024) / 8, 2048); } nswbuf = max(min(nbuf/4, 64), 16); valloc(swbuf, struct buf, nswbuf); valloc(buf, struct buf, nbuf); /* * End of first pass, size has been calculated so allocate memory */ if (firstaddr == 0) { size = (vm_size_t)(v - firstaddr); firstaddr = (vm_offset_t)kmem_alloc(kernel_map, round_page(size)); if (firstaddr == 0) panic("startup: no room for tables"); goto again; } /* * End of second pass, addresses have been assigned */ if ((vm_size_t)(v - firstaddr) != size) panic("startup: table size inconsistency"); clean_map = kmem_suballoc(kernel_map, &clean_sva, &clean_eva, (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size); buffer_map = kmem_suballoc(clean_map, &buffer_sva, &buffer_eva, (nbuf*BKVASIZE)); pager_map = kmem_suballoc(clean_map, &pager_sva, &pager_eva, (nswbuf*MAXPHYS) + pager_map_size); pager_map->system_map = 1; exec_map = kmem_suballoc(kernel_map, &minaddr, &maxaddr, (16*(ARG_MAX+(PAGE_SIZE*3)))); /* * Finally, allocate mbuf pool. Since mclrefcnt is an off-size * we use the more space efficient malloc in place of kmem_alloc. */ { vm_offset_t mb_map_size; mb_map_size = nmbufs * MSIZE + nmbclusters * MCLBYTES; mb_map_size = roundup2(mb_map_size, max(MCLBYTES, PAGE_SIZE)); mclrefcnt = malloc(mb_map_size / MCLBYTES, M_MBUF, M_NOWAIT); bzero(mclrefcnt, mb_map_size / MCLBYTES); mb_map = kmem_suballoc(kmem_map, (vm_offset_t *)&mbutl, &maxaddr, mb_map_size); mb_map->system_map = 1; } /* * Initialize callouts */ SLIST_INIT(&callfree); for (i = 0; i < ncallout; i++) { SLIST_INSERT_HEAD(&callfree, &callout[i], c_links.sle); } for (i = 0; i < callwheelsize; i++) { TAILQ_INIT(&callwheel[i]); } #if defined(USERCONFIG) #if defined(USERCONFIG_BOOT) if (1) #else if (boothowto & RB_CONFIG) #endif { userconfig(); cninit(); /* the preferred console may have changed */ } #endif printf("avail memory = %d (%dK bytes)\n", ptoa(cnt.v_free_count), ptoa(cnt.v_free_count) / 1024); /* * Set up buffers, so they can be used to read disk labels. */ bufinit(); vm_pager_bufferinit(); } int register_netisr(num, handler) int num; netisr_t *handler; { if (num < 0 || num >= (sizeof(netisrs)/sizeof(*netisrs)) ) { printf("register_netisr: bad isr number: %d\n", num); return (EINVAL); } netisrs[num] = handler; return (0); } static void setup_netisrs(ls) struct linker_set *ls; { int i; const struct netisrtab *nit; for(i = 0; ls->ls_items[i]; i++) { nit = (const struct netisrtab *)ls->ls_items[i]; register_netisr(nit->nit_num, nit->nit_isr); } } /* * Retrieve the platform name from the DSR. */ const char * alpha_dsr_sysname() { struct dsrdb *dsr; const char *sysname; /* * DSR does not exist on early HWRPB versions. */ if (hwrpb->rpb_version < HWRPB_DSRDB_MINVERS) return (NULL); dsr = (struct dsrdb *)(((caddr_t)hwrpb) + hwrpb->rpb_dsrdb_off); sysname = (const char *)((caddr_t)dsr + (dsr->dsr_sysname_off + sizeof(u_int64_t))); return (sysname); } /* * Lookup the system specified system variation in the provided table, * returning the model string on match. */ const char * alpha_variation_name(u_int64_t variation, const struct alpha_variation_table *avtp) { int i; for (i = 0; avtp[i].avt_model != NULL; i++) if (avtp[i].avt_variation == variation) return (avtp[i].avt_model); return (NULL); } /* * Generate a default platform name based for unknown system variations. */ const char * alpha_unknown_sysname() { static char s[128]; /* safe size */ sprintf(s, "%s family, unknown model variation 0x%lx", platform.family, hwrpb->rpb_variation & SV_ST_MASK); return ((const char *)s); } static void identifycpu(void) { /* * print out CPU identification information. */ printf("%s\n%s, %ldMHz\n", platform.family, platform.model, hwrpb->rpb_cc_freq / 1000000); /* XXX true for 21164? */ printf("%ld byte page size, %d processor%s.\n", hwrpb->rpb_page_size, ncpus, ncpus == 1 ? "" : "s"); #if 0 /* this isn't defined for any systems that we run on? */ printf("serial number 0x%lx 0x%lx\n", ((long *)hwrpb->rpb_ssn)[0], ((long *)hwrpb->rpb_ssn)[1]); /* and these aren't particularly useful! */ printf("variation: 0x%lx, revision 0x%lx\n", hwrpb->rpb_variation, *(long *)hwrpb->rpb_revision); #endif } extern char kernel_text[], _end[]; void alpha_init(pfn, ptb, bim, bip, biv) u_long pfn; /* first free PFN number */ u_long ptb; /* PFN of current level 1 page table */ u_long bim; /* bootinfo magic */ u_long bip; /* bootinfo pointer */ u_long biv; /* bootinfo version */ { int phys_avail_cnt; char *bootinfo_msg; vm_offset_t kernstart, kernend; vm_offset_t kernstartpfn, kernendpfn, pfn0, pfn1; struct mddt *mddtp; struct mddt_cluster *memc; int i, mddtweird; int cputype; char* p; /* NO OUTPUT ALLOWED UNTIL FURTHER NOTICE */ /* * Turn off interrupts (not mchecks) and floating point. * Make sure the instruction and data streams are consistent. */ (void)alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH); /* alpha_pal_wrfen(0); */ ALPHA_TBIA(); alpha_pal_imb(); /* * Get critical system information (if possible, from the * information provided by the boot program). */ bootinfo_msg = NULL; if (bim == BOOTINFO_MAGIC) { if (biv == 0) { /* backward compat */ biv = *(u_long *)bip; bip += 8; } switch (biv) { case 1: { struct bootinfo_v1 *v1p = (struct bootinfo_v1 *)bip; bootinfo.ssym = v1p->ssym; bootinfo.esym = v1p->esym; /* hwrpb may not be provided by boot block in v1 */ if (v1p->hwrpb != NULL) { bootinfo.hwrpb_phys = ((struct rpb *)v1p->hwrpb)->rpb_phys; bootinfo.hwrpb_size = v1p->hwrpbsize; } else { bootinfo.hwrpb_phys = ((struct rpb *)HWRPB_ADDR)->rpb_phys; bootinfo.hwrpb_size = ((struct rpb *)HWRPB_ADDR)->rpb_size; } bcopy(v1p->boot_flags, bootinfo.boot_flags, min(sizeof v1p->boot_flags, sizeof bootinfo.boot_flags)); bcopy(v1p->booted_kernel, bootinfo.booted_kernel, min(sizeof v1p->booted_kernel, sizeof bootinfo.booted_kernel)); /* booted dev not provided in bootinfo */ init_prom_interface((struct rpb *) ALPHA_PHYS_TO_K0SEG(bootinfo.hwrpb_phys)); prom_getenv(PROM_E_BOOTED_DEV, bootinfo.booted_dev, sizeof bootinfo.booted_dev); break; } default: bootinfo_msg = "unknown bootinfo version"; goto nobootinfo; } } else { bootinfo_msg = "boot program did not pass bootinfo"; nobootinfo: bootinfo.ssym = (u_long)&_end; bootinfo.esym = (u_long)&_end; #ifdef SIMOS { char* p = (char*)bootinfo.ssym + 8; if (p[EI_MAG0] == ELFMAG0 && p[EI_MAG1] == ELFMAG1 && p[EI_MAG2] == ELFMAG2 && p[EI_MAG3] == ELFMAG3) { bootinfo.ssym = (u_long) p; bootinfo.esym = (u_long)p + *(u_long*)(p - 8); } } #endif bootinfo.hwrpb_phys = ((struct rpb *)HWRPB_ADDR)->rpb_phys; bootinfo.hwrpb_size = ((struct rpb *)HWRPB_ADDR)->rpb_size; init_prom_interface((struct rpb *)HWRPB_ADDR); prom_getenv(PROM_E_BOOTED_OSFLAGS, bootinfo.boot_flags, sizeof bootinfo.boot_flags); #ifndef SIMOS prom_getenv(PROM_E_BOOTED_FILE, bootinfo.booted_kernel, sizeof bootinfo.booted_kernel); #endif prom_getenv(PROM_E_BOOTED_DEV, bootinfo.booted_dev, sizeof bootinfo.booted_dev); } /* * Initialize the kernel's mapping of the RPB. It's needed for * lots of things. */ hwrpb = (struct rpb *)ALPHA_PHYS_TO_K0SEG(bootinfo.hwrpb_phys); /* * Remember how many cycles there are per microsecond, * so that we can use delay(). Round up, for safety. */ cycles_per_usec = (hwrpb->rpb_cc_freq + 999999) / 1000000; /* * Remember how many cycles per closk for coping with missed * clock interrupts. */ cycles_per_sec = hwrpb->rpb_cc_freq; /* * Initalize the (temporary) bootstrap console interface, so * we can use printf until the VM system starts being setup. * The real console is initialized before then. */ init_bootstrap_console(); /* OUTPUT NOW ALLOWED */ /* delayed from above */ if (bootinfo_msg) printf("WARNING: %s (0x%lx, 0x%lx, 0x%lx)\n", bootinfo_msg, bim, bip, biv); /* * Point interrupt/exception vectors to our own. */ alpha_pal_wrent(XentInt, ALPHA_KENTRY_INT); alpha_pal_wrent(XentArith, ALPHA_KENTRY_ARITH); alpha_pal_wrent(XentMM, ALPHA_KENTRY_MM); alpha_pal_wrent(XentIF, ALPHA_KENTRY_IF); alpha_pal_wrent(XentUna, ALPHA_KENTRY_UNA); alpha_pal_wrent(XentSys, ALPHA_KENTRY_SYS); /* * Clear pending machine checks and error reports, and enable * system- and processor-correctable error reporting. */ alpha_pal_wrmces(alpha_pal_rdmces() & ~(ALPHA_MCES_DSC|ALPHA_MCES_DPC)); /* * Find out what hardware we're on, and do basic initialization. */ cputype = hwrpb->rpb_type; if (cputype >= ncpuinit) { platform_not_supported(cputype); /* NOTREACHED */ } cpuinit[cputype].init(cputype); strcpy(cpu_model, platform.model); /* * Initalize the real console, so the the bootstrap console is * no longer necessary. */ if (platform.cons_init) platform.cons_init(); /* NO MORE FIRMWARE ACCESS ALLOWED */ #ifdef _PMAP_MAY_USE_PROM_CONSOLE /* * XXX (unless _PMAP_MAY_USE_PROM_CONSOLE is defined and * XXX pmap_uses_prom_console() evaluates to non-zero.) */ #endif /* * find out this system's page size */ if (hwrpb->rpb_page_size != PAGE_SIZE) panic("page size %d != 8192?!", hwrpb->rpb_page_size); /* * Find the beginning and end of the kernel (and leave a * bit of space before the beginning for the bootstrap * stack). */ kernstart = trunc_page(kernel_text) - 2 * PAGE_SIZE; #ifdef DDB ksym_start = (void *)bootinfo.ssym; ksym_end = (void *)bootinfo.esym; kernend = (vm_offset_t)round_page(ksym_end); #else kernend = (vm_offset_t)round_page(_end); #endif kernstartpfn = atop(ALPHA_K0SEG_TO_PHYS(kernstart)); kernendpfn = atop(ALPHA_K0SEG_TO_PHYS(kernend)); #ifdef SIMOS /* * SimOS console puts the bootstrap stack after kernel */ kernendpfn += 4; #endif /* * Find out how much memory is available, by looking at * the memory cluster descriptors. This also tries to do * its best to detect things things that have never been seen * before... */ mddtp = (struct mddt *)(((caddr_t)hwrpb) + hwrpb->rpb_memdat_off); /* MDDT SANITY CHECKING */ mddtweird = 0; if (mddtp->mddt_cluster_cnt < 2) { mddtweird = 1; printf("WARNING: weird number of mem clusters: %d\n", mddtp->mddt_cluster_cnt); } #if 0 printf("Memory cluster count: %d\n", mddtp->mddt_cluster_cnt); #endif phys_avail_cnt = 0; for (i = 0; i < mddtp->mddt_cluster_cnt; i++) { memc = &mddtp->mddt_clusters[i]; #if 0 printf("MEMC %d: pfn 0x%lx cnt 0x%lx usage 0x%lx\n", i, memc->mddt_pfn, memc->mddt_pg_cnt, memc->mddt_usage); #endif totalphysmem += memc->mddt_pg_cnt; if (memc->mddt_usage & MDDT_mbz) { mddtweird = 1; printf("WARNING: mem cluster %d has weird " "usage 0x%lx\n", i, memc->mddt_usage); unknownmem += memc->mddt_pg_cnt; continue; } if (memc->mddt_usage & MDDT_NONVOLATILE) { /* XXX should handle these... */ printf("WARNING: skipping non-volatile mem " "cluster %d\n", i); unusedmem += memc->mddt_pg_cnt; continue; } if (memc->mddt_usage & MDDT_PALCODE) { resvmem += memc->mddt_pg_cnt; continue; } /* * We have a memory cluster available for system * software use. We must determine if this cluster * holds the kernel. */ /* * XXX If the kernel uses the PROM console, we only use the * XXX memory after the kernel in the first system segment, * XXX to avoid clobbering prom mapping, data, etc. */ if (!pmap_uses_prom_console() || physmem == 0) { physmem += memc->mddt_pg_cnt; pfn0 = memc->mddt_pfn; pfn1 = memc->mddt_pfn + memc->mddt_pg_cnt; if (pfn0 <= kernendpfn && kernstartpfn <= pfn1) { /* * Must compute the location of the kernel * within the segment. */ #if 0 printf("Cluster %d contains kernel\n", i); #endif if (!pmap_uses_prom_console()) { if (pfn0 < kernstartpfn) { /* * There is a chunk before the kernel. */ #if 0 printf("Loading chunk before kernel: " "0x%lx / 0x%lx\n", pfn0, kernstartpfn); #endif phys_avail[phys_avail_cnt] = alpha_ptob(pfn0); phys_avail[phys_avail_cnt+1] = alpha_ptob(kernstartpfn); phys_avail_cnt += 2; } } if (kernendpfn < pfn1) { /* * There is a chunk after the kernel. */ #if 0 printf("Loading chunk after kernel: " "0x%lx / 0x%lx\n", kernendpfn, pfn1); #endif phys_avail[phys_avail_cnt] = alpha_ptob(kernendpfn); phys_avail[phys_avail_cnt+1] = alpha_ptob(pfn1); phys_avail_cnt += 2; } } else { /* * Just load this cluster as one chunk. */ #if 0 printf("Loading cluster %d: 0x%lx / 0x%lx\n", i, pfn0, pfn1); #endif phys_avail[phys_avail_cnt] = alpha_ptob(pfn0); phys_avail[phys_avail_cnt+1] = alpha_ptob(pfn1); phys_avail_cnt += 2; } } } phys_avail[phys_avail_cnt] = 0; /* * Dump out the MDDT if it looks odd... */ if (mddtweird) { printf("\n"); printf("complete memory cluster information:\n"); for (i = 0; i < mddtp->mddt_cluster_cnt; i++) { printf("mddt %d:\n", i); printf("\tpfn %lx\n", mddtp->mddt_clusters[i].mddt_pfn); printf("\tcnt %lx\n", mddtp->mddt_clusters[i].mddt_pg_cnt); printf("\ttest %lx\n", mddtp->mddt_clusters[i].mddt_pg_test); printf("\tbva %lx\n", mddtp->mddt_clusters[i].mddt_v_bitaddr); printf("\tbpa %lx\n", mddtp->mddt_clusters[i].mddt_p_bitaddr); printf("\tbcksum %lx\n", mddtp->mddt_clusters[i].mddt_bit_cksum); printf("\tusage %lx\n", mddtp->mddt_clusters[i].mddt_usage); } printf("\n"); } Maxmem = physmem; /* * Initialize error message buffer (at end of core). */ { size_t sz = round_page(MSGBUF_SIZE); int i = phys_avail_cnt - 2; char* cp; /* shrink so that it'll fit in the last segment */ if (phys_avail[i+1] - phys_avail[i] < sz) sz = phys_avail[i+1] - phys_avail[i]; phys_avail[i+1] -= sz; msgbufp = (struct msgbuf*) ALPHA_PHYS_TO_K0SEG(phys_avail[i+1]); msgbufinit(msgbufp, MSGBUF_SIZE); /* Remove the last segment if it now has no pages. */ if (phys_avail[i] == phys_avail[i+1]) phys_avail[i] = 0; /* warn if the message buffer had to be shrunk */ if (sz != round_page(MSGBUFSIZE)) printf("WARNING: %d bytes not available for msgbuf in last cluster (%d used)\n", round_page(MSGBUFSIZE), sz); } /* * Init mapping for u page(s) for proc 0 */ proc0.p_addr = proc0paddr = (struct user *)pmap_steal_memory(UPAGES * PAGE_SIZE); /* * Initialize the virtual memory system, and set the * page table base register in proc 0's PCB. */ pmap_bootstrap(ALPHA_PHYS_TO_K0SEG(alpha_ptob(ptb)), hwrpb->rpb_max_asn); /* * Initialize the rest of proc 0's PCB, and cache its physical * address. */ proc0.p_md.md_pcbpaddr = (struct pcb *)ALPHA_K0SEG_TO_PHYS((vm_offset_t)&proc0paddr->u_pcb); /* * Set the kernel sp, reserving space for an (empty) trapframe, * and make proc0's trapframe pointer point to it for sanity. */ proc0paddr->u_pcb.pcb_hw.apcb_ksp = (u_int64_t)proc0paddr + USPACE - sizeof(struct trapframe); proc0.p_md.md_tf = (struct trapframe *)proc0paddr->u_pcb.pcb_hw.apcb_ksp; /* * Look at arguments passed to us and compute boothowto. */ boothowto = RB_SINGLE; #ifdef KADB boothowto |= RB_KDB; #endif /* boothowto |= RB_KDB | RB_GDB; */ for (p = bootinfo.boot_flags; p && *p != '\0'; p++) { /* * Note that we'd really like to differentiate case here, * but the Alpha AXP Architecture Reference Manual * says that we shouldn't. */ switch (*p) { case 'a': /* autoboot */ case 'A': boothowto &= ~RB_SINGLE; break; #ifdef DEBUG case 'c': /* crash dump immediately after autoconfig */ case 'C': boothowto |= RB_DUMP; break; #endif #if defined(DDB) case 'd': /* break into the kernel debugger ASAP */ case 'D': boothowto |= RB_KDB; break; case 'g': /* use kernel gdb */ case 'G': boothowto |= RB_GDB; break; #endif case 'h': /* always halt, never reboot */ case 'H': boothowto |= RB_HALT; break; #if 0 case 'm': /* mini root present in memory */ case 'M': boothowto |= RB_MINIROOT; break; #endif case 'n': /* askname */ case 'N': boothowto |= RB_ASKNAME; break; case 's': /* single-user (default, supported for sanity) */ case 'S': boothowto |= RB_SINGLE; break; case 'v': case 'V': bootverbose = 1; break; default: printf("Unrecognized boot flag '%c'.\n", *p); break; } } /* * Initialize debuggers, and break into them if appropriate. */ #ifdef DDB kdb_init(); if (boothowto & RB_KDB) Debugger("Boot flags requested debugger"); #endif /* * Figure out the number of cpus in the box, from RPB fields. * Really. We mean it. */ for (i = 0; i < hwrpb->rpb_pcs_cnt; i++) { struct pcs *pcsp; pcsp = (struct pcs *)((char *)hwrpb + hwrpb->rpb_pcs_off + (i * hwrpb->rpb_pcs_size)); if ((pcsp->pcs_flags & PCS_PP) != 0) ncpus++; } /* * Figure out our clock frequency, from RPB fields. */ hz = hwrpb->rpb_intr_freq >> 12; if (!(60 <= hz && hz <= 10240)) { hz = 1024; #ifdef DIAGNOSTIC printf("WARNING: unbelievable rpb_intr_freq: %ld (%d hz)\n", hwrpb->rpb_intr_freq, hz); #endif } alpha_pal_wrfen(0); } void bzero(void *buf, size_t len) { caddr_t p = buf; while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) { *p++ = 0; len--; } while (len >= sizeof(u_long)) { *(u_long*) p = 0; p += sizeof(u_long); len -= sizeof(u_long); } while (len) { *p++ = 0; len--; } } /* * Wait "n" microseconds. */ void DELAY(int n) { #ifndef SIMOS long N = cycles_per_usec * (n); while (N > 0) /* XXX */ N -= 3; /* XXX */ #endif } /* * The following primitives manipulate the run queues. _whichqs tells which * of the 32 queues _qs have processes in them. Setrunqueue puts processes * into queues, Remrunqueue removes them from queues. The running process is * on no queue, other processes are on a queue related to p->p_priority, * divided by 4 actually to shrink the 0-127 range of priorities into the 32 * available queues. */ #define P_FORW(p) ((struct proc*) (p)->p_procq.tqe_next) #define P_BACK(p) ((struct proc*) (p)->p_procq.tqe_prev) #define INSRQ(qs, whichqs, pri, p) \ do { \ whichqs |= (1 << pri); \ P_FORW(p) = (struct proc *)&qs[pri]; \ P_BACK(p) = qs[pri].ph_rlink; \ P_FORW(P_BACK(p)) = p; \ qs[pri].ph_rlink = p; \ } while(0) #define REMRQ(qs, whichqs, pri, p) \ do { \ if (!(whichqs & (1 << pri))) \ panic(#whichqs); \ P_FORW(P_BACK(p)) = P_FORW(p); \ P_BACK(P_FORW(p)) = P_BACK(p); \ P_BACK(p) = NULL; \ if ((struct proc *)&qs[pri] == qs[pri].ph_link) \ whichqs &= ~(1 << pri); \ } while(0) /* * setrunqueue(p) * proc *p; * * Call should be made at splclock(), and p->p_stat should be SRUN. */ void setrunqueue(p) struct proc *p; { int pri; #if 0 /* firewall: p->p_back must be NULL */ if (p->p_procq.tqe_prev != NULL) panic("setrunqueue"); #endif if (p->p_rtprio.type == RTP_PRIO_NORMAL) { /* normal priority */ pri = p->p_priority >> 2; INSRQ(qs, whichqs, pri, p); } else { /* realtime or idle */ pri = p->p_rtprio.prio; if (p->p_rtprio.type == RTP_PRIO_REALTIME #ifdef P1003_1B || p->p_rtprio.type == RTP_PRIO_FIFO #endif ) { /* realtime priority */ INSRQ(rtqs, whichrtqs, pri, p); } else { /* idle priority */ INSRQ(idqs, whichidqs, pri, p); } } } /* * remrq(p) * * Call should be made at splclock(). */ void remrq(p) struct proc *p; { int pri; if (p->p_rtprio.type == RTP_PRIO_NORMAL) { /* normal priority */ pri = p->p_priority >> 2; REMRQ(qs, whichqs, pri, p); } else { /* realtime or idle */ pri = p->p_rtprio.prio; if (p->p_rtprio.type == RTP_PRIO_REALTIME #ifdef P1003_1B || p->p_rtprio.type == RTP_PRIO_FIFO #endif ) { /* realtime priority */ REMRQ(rtqs, whichrtqs, pri, p); } else { /* idle priority */ REMRQ(rtqs, whichrtqs, pri, p); } } } /* * Send an interrupt to process. * * Stack is set up to allow sigcode stored * at top to call routine, followed by kcall * to sigreturn routine below. After sigreturn * resets the signal mask, the stack, and the * frame pointer, it returns to the user * specified pc, psl. */ void sendsig(sig_t catcher, int sig, int mask, u_long code) { struct proc *p = curproc; struct sigcontext *scp, ksc; struct trapframe *frame; struct sigacts *psp = p->p_sigacts; int oonstack, fsize, rndfsize; frame = p->p_md.md_tf; oonstack = psp->ps_sigstk.ss_flags & SS_ONSTACK; fsize = sizeof ksc; rndfsize = ((fsize + 15) / 16) * 16; /* * Allocate and validate space for the signal handler * context. Note that if the stack is in P0 space, the * call to grow() is a nop, and the useracc() check * will fail if the process has not already allocated * the space with a `brk'. */ if ((psp->ps_flags & SAS_ALTSTACK) && !oonstack && (psp->ps_sigonstack & sigmask(sig))) { scp = (struct sigcontext *)((caddr_t)psp->ps_sigstk.ss_sp + psp->ps_sigstk.ss_size - rndfsize); psp->ps_sigstk.ss_flags |= SS_ONSTACK; } else scp = (struct sigcontext *)(alpha_pal_rdusp() - rndfsize); if ((u_long)scp <= USRSTACK - ctob(p->p_vmspace->vm_ssize)) #if defined(UVM) (void)uvm_grow(p, (u_long)scp); #else (void)grow(p, (u_long)scp); #endif #ifdef DEBUG if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid) printf("sendsig(%d): sig %d ssp %p usp %p\n", p->p_pid, sig, &oonstack, scp); #endif #if defined(UVM) if (uvm_useracc((caddr_t)scp, fsize, B_WRITE) == 0) { #else if (useracc((caddr_t)scp, fsize, B_WRITE) == 0) { #endif #ifdef DEBUG if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid) printf("sendsig(%d): useracc failed on sig %d\n", p->p_pid, sig); #endif /* * Process has trashed its stack; give it an illegal * instruction to halt it in its tracks. */ SIGACTION(p, SIGILL) = SIG_DFL; sig = sigmask(SIGILL); p->p_sigignore &= ~sig; p->p_sigcatch &= ~sig; p->p_sigmask &= ~sig; psignal(p, SIGILL); return; #if !defined(UVM) /* this construct will balance braces for ctags(1) */ } #else } #endif /* * Build the signal context to be used by sigreturn. */ ksc.sc_onstack = oonstack; ksc.sc_mask = mask; ksc.sc_pc = frame->tf_regs[FRAME_PC]; ksc.sc_ps = frame->tf_regs[FRAME_PS]; /* copy the registers. */ fill_regs(p, (struct reg *)ksc.sc_regs); ksc.sc_regs[R_ZERO] = 0xACEDBADE; /* magic number */ ksc.sc_regs[R_SP] = alpha_pal_rdusp(); /* save the floating-point state, if necessary, then copy it. */ if (p == fpcurproc) { alpha_pal_wrfen(1); savefpstate(&p->p_addr->u_pcb.pcb_fp); alpha_pal_wrfen(0); fpcurproc = NULL; } ksc.sc_ownedfp = p->p_md.md_flags & MDP_FPUSED; bcopy(&p->p_addr->u_pcb.pcb_fp, (struct fpreg *)ksc.sc_fpregs, sizeof(struct fpreg)); ksc.sc_fp_control = 0; /* XXX ? */ bzero(ksc.sc_reserved, sizeof ksc.sc_reserved); /* XXX */ bzero(ksc.sc_xxx, sizeof ksc.sc_xxx); /* XXX */ #ifdef COMPAT_OSF1 /* * XXX Create an OSF/1-style sigcontext and associated goo. */ #endif /* * copy the frame out to userland. */ (void) copyout((caddr_t)&ksc, (caddr_t)scp, fsize); #ifdef DEBUG if (sigdebug & SDB_FOLLOW) printf("sendsig(%d): sig %d scp %p code %lx\n", p->p_pid, sig, scp, code); #endif /* * Set up the registers to return to sigcode. */ frame->tf_regs[FRAME_PC] = (u_int64_t)PS_STRINGS - (esigcode - sigcode); frame->tf_regs[FRAME_A0] = sig; frame->tf_regs[FRAME_A1] = code; frame->tf_regs[FRAME_A2] = (u_int64_t)scp; frame->tf_regs[FRAME_T12] = (u_int64_t)catcher; /* t12 is pv */ alpha_pal_wrusp((unsigned long)scp); #ifdef DEBUG if (sigdebug & SDB_FOLLOW) printf("sendsig(%d): pc %lx, catcher %lx\n", p->p_pid, frame->tf_regs[FRAME_PC], frame->tf_regs[FRAME_A3]); if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid) printf("sendsig(%d): sig %d returns\n", p->p_pid, sig); #endif } /* * System call to cleanup state after a signal * has been taken. Reset signal mask and * stack state from context left by sendsig (above). * Return to previous pc and psl as specified by * context left by sendsig. Check carefully to * make sure that the user has not modified the * state to gain improper privileges. */ int sigreturn(struct proc *p, struct sigreturn_args /* { struct sigcontext *sigcntxp; } */ *uap) { struct sigcontext *scp, ksc; scp = uap->sigcntxp; #ifdef DEBUG if (sigdebug & SDB_FOLLOW) printf("sigreturn: pid %d, scp %p\n", p->p_pid, scp); #endif if (ALIGN(scp) != (u_int64_t)scp) return (EINVAL); /* * Test and fetch the context structure. * We grab it all at once for speed. */ #if defined(UVM) if (uvm_useracc((caddr_t)scp, sizeof (*scp), B_WRITE) == 0 || copyin((caddr_t)scp, (caddr_t)&ksc, sizeof ksc)) return (EINVAL); #else if (useracc((caddr_t)scp, sizeof (*scp), B_WRITE) == 0 || copyin((caddr_t)scp, (caddr_t)&ksc, sizeof ksc)) return (EINVAL); #endif if (ksc.sc_regs[R_ZERO] != 0xACEDBADE) /* magic number */ return (EINVAL); /* * Restore the user-supplied information */ if (ksc.sc_onstack) p->p_sigacts->ps_sigstk.ss_flags |= SS_ONSTACK; else p->p_sigacts->ps_sigstk.ss_flags &= ~SS_ONSTACK; p->p_sigmask = ksc.sc_mask &~ sigcantmask; set_regs(p, (struct reg *)ksc.sc_regs); p->p_md.md_tf->tf_regs[FRAME_PC] = ksc.sc_pc; p->p_md.md_tf->tf_regs[FRAME_PS] = (ksc.sc_ps | ALPHA_PSL_USERSET) & ~ALPHA_PSL_USERCLR; alpha_pal_wrusp(ksc.sc_regs[R_SP]); /* XXX ksc.sc_ownedfp ? */ if (p == fpcurproc) fpcurproc = NULL; bcopy((struct fpreg *)ksc.sc_fpregs, &p->p_addr->u_pcb.pcb_fp, sizeof(struct fpreg)); /* XXX ksc.sc_fp_control ? */ #ifdef DEBUG if (sigdebug & SDB_FOLLOW) printf("sigreturn(%d): returns\n", p->p_pid); #endif return (EJUSTRETURN); } /* * Machine dependent boot() routine * * I haven't seen anything to put here yet * Possibly some stuff might be grafted back here from boot() */ void cpu_boot(int howto) { } /* * Shutdown the CPU as much as possible */ void cpu_halt(void) { alpha_pal_halt(); } /* * Turn the power off. */ void cpu_power_down(void) { alpha_pal_halt(); /* XXX */ } /* * Clear registers on exec */ void setregs(struct proc *p, u_long entry, u_long stack) { struct trapframe *tfp = p->p_md.md_tf; bzero(tfp->tf_regs, FRAME_SIZE * sizeof tfp->tf_regs[0]); bzero(&p->p_addr->u_pcb.pcb_fp, sizeof p->p_addr->u_pcb.pcb_fp); #define FP_RN 2 /* XXX */ p->p_addr->u_pcb.pcb_fp.fpr_cr = (long)FP_RN << 58; alpha_pal_wrusp(stack); tfp->tf_regs[FRAME_PS] = ALPHA_PSL_USERSET; tfp->tf_regs[FRAME_PC] = entry & ~3; tfp->tf_regs[FRAME_A0] = stack; /* a0 = sp */ tfp->tf_regs[FRAME_A1] = 0; /* a1 = rtld cleanup */ tfp->tf_regs[FRAME_A2] = 0; /* a2 = rtld object */ tfp->tf_regs[FRAME_A3] = (u_int64_t)PS_STRINGS; /* a3 = ps_strings */ tfp->tf_regs[FRAME_T12] = tfp->tf_regs[FRAME_PC]; /* a.k.a. PV */ p->p_md.md_flags &= ~MDP_FPUSED; if (fpcurproc == p) fpcurproc = NULL; } int ptrace_set_pc(struct proc *p, unsigned long addr) { struct trapframe *tp = p->p_md.md_tf; tp->tf_regs[FRAME_PC] = addr; return 0; } static int ptrace_read_int(struct proc *p, vm_offset_t addr, u_int32_t *v) { struct iovec iov; struct uio uio; iov.iov_base = (caddr_t) v; iov.iov_len = sizeof(u_int32_t); uio.uio_iov = &iov; uio.uio_iovcnt = 1; uio.uio_offset = (off_t)addr; uio.uio_resid = sizeof(u_int32_t); uio.uio_segflg = UIO_SYSSPACE; uio.uio_rw = UIO_READ; uio.uio_procp = p; return procfs_domem(curproc, p, NULL, &uio); } static int ptrace_write_int(struct proc *p, vm_offset_t addr, u_int32_t v) { struct iovec iov; struct uio uio; iov.iov_base = (caddr_t) &v; iov.iov_len = sizeof(u_int32_t); uio.uio_iov = &iov; uio.uio_iovcnt = 1; uio.uio_offset = (off_t)addr; uio.uio_resid = sizeof(u_int32_t); uio.uio_segflg = UIO_SYSSPACE; uio.uio_rw = UIO_WRITE; uio.uio_procp = p; return procfs_domem(curproc, p, NULL, &uio); } static u_int64_t ptrace_read_register(struct proc *p, int regno) { static int reg_to_frame[32] = { FRAME_V0, FRAME_T0, FRAME_T1, FRAME_T2, FRAME_T3, FRAME_T4, FRAME_T5, FRAME_T6, FRAME_T7, FRAME_S0, FRAME_S1, FRAME_S2, FRAME_S3, FRAME_S4, FRAME_S5, FRAME_S6, FRAME_A0, FRAME_A1, FRAME_A2, FRAME_A3, FRAME_A4, FRAME_A5, FRAME_T8, FRAME_T9, FRAME_T10, FRAME_T11, FRAME_RA, FRAME_T12, FRAME_AT, FRAME_GP, FRAME_SP, -1, /* zero */ }; if (regno == R_ZERO) return 0; return p->p_md.md_tf->tf_regs[reg_to_frame[regno]]; } static int ptrace_clear_bpt(struct proc *p, struct mdbpt *bpt) { return ptrace_write_int(p, bpt->addr, bpt->contents); } static int ptrace_set_bpt(struct proc *p, struct mdbpt *bpt) { int error; u_int32_t bpins = 0x00000080; error = ptrace_read_int(p, bpt->addr, &bpt->contents); if (error) return error; return ptrace_write_int(p, bpt->addr, bpins); } int ptrace_clear_single_step(struct proc *p) { if (p->p_md.md_flags & MDP_STEP2) { ptrace_clear_bpt(p, &p->p_md.md_sstep[1]); ptrace_clear_bpt(p, &p->p_md.md_sstep[0]); p->p_md.md_flags &= ~MDP_STEP2; } else if (p->p_md.md_flags & MDP_STEP1) { ptrace_clear_bpt(p, &p->p_md.md_sstep[0]); p->p_md.md_flags &= ~MDP_STEP1; } return 0; } int ptrace_single_step(struct proc *p) { int error; vm_offset_t pc = p->p_md.md_tf->tf_regs[FRAME_PC]; alpha_instruction ins; vm_offset_t addr[2]; /* places to set breakpoints */ int count = 0; /* count of breakpoints */ if (p->p_md.md_flags & (MDP_STEP1|MDP_STEP2)) panic("ptrace_single_step: step breakpoints not removed"); error = ptrace_read_int(p, pc, &ins.bits); if (error) return error; switch (ins.branch_format.opcode) { case op_j: /* Jump: target is register value */ addr[0] = ptrace_read_register(p, ins.jump_format.rs) & ~3; count = 1; break; case op_br: case op_fbeq: case op_fblt: case op_fble: case op_bsr: case op_fbne: case op_fbge: case op_fbgt: case op_blbc: case op_beq: case op_blt: case op_ble: case op_blbs: case op_bne: case op_bge: case op_bgt: /* Branch: target is pc+4+4*displacement */ addr[0] = pc + 4; addr[1] = pc + 4 + 4 * ins.branch_format.displacement; count = 2; break; default: addr[0] = pc + 4; count = 1; } p->p_md.md_sstep[0].addr = addr[0]; if (error = ptrace_set_bpt(p, &p->p_md.md_sstep[0])) return error; if (count == 2) { p->p_md.md_sstep[1].addr = addr[1]; if (error = ptrace_set_bpt(p, &p->p_md.md_sstep[1])) { ptrace_clear_bpt(p, &p->p_md.md_sstep[0]); return error; } p->p_md.md_flags |= MDP_STEP2; } else p->p_md.md_flags |= MDP_STEP1; return 0; } int ptrace_read_u_check(p, addr, len) struct proc *p; vm_offset_t addr; size_t len; { vm_offset_t gap; if ((vm_offset_t) (addr + len) < addr) return EPERM; if ((vm_offset_t) (addr + len) <= sizeof(struct user)) return 0; gap = (char *) p->p_md.md_tf - (char *) p->p_addr; if ((vm_offset_t) addr < gap) return EPERM; if ((vm_offset_t) (addr + len) <= (vm_offset_t) (gap + sizeof(struct trapframe))) return 0; return EPERM; } int ptrace_write_u(struct proc *p, vm_offset_t off, long data) { struct trapframe frame_copy; vm_offset_t min; struct trapframe *tp; /* * Privileged kernel state is scattered all over the user area. * Only allow write access to parts of regs and to fpregs. */ min = (char *)p->p_md.md_tf - (char *)p->p_addr; if (off >= min && off <= min + sizeof(struct trapframe) - sizeof(int)) { tp = p->p_md.md_tf; #if 0 frame_copy = *tp; *(int *)((char *)&frame_copy + (off - min)) = data; if (!EFLAGS_SECURE(frame_copy.tf_eflags, tp->tf_eflags) || !CS_SECURE(frame_copy.tf_cs)) return (EINVAL); #endif *(int*)((char *)p->p_addr + off) = data; return (0); } min = offsetof(struct user, u_pcb) + offsetof(struct pcb, pcb_fp); if (off >= min && off <= min + sizeof(struct fpreg) - sizeof(int)) { *(int*)((char *)p->p_addr + off) = data; return (0); } return (EFAULT); } int alpha_pa_access(vm_offset_t pa) { #if 0 int i; for (i = 0; phys_avail[i] != 0; i += 2) { if (pa < phys_avail[i]) continue; if (pa < phys_avail[i+1]) return VM_PROT_READ|VM_PROT_WRITE; } return 0; #else return VM_PROT_READ|VM_PROT_WRITE; #endif } int fill_regs(p, regs) struct proc *p; struct reg *regs; { struct pcb *pcb = &p->p_addr->u_pcb; struct trapframe *tp = p->p_md.md_tf; tp = p->p_md.md_tf; #define C(r) regs->r_regs[R_ ## r] = tp->tf_regs[FRAME_ ## r] C(V0); C(T0); C(T1); C(T2); C(T3); C(T4); C(T5); C(T6); C(T7); C(S0); C(S1); C(S2); C(S3); C(S4); C(S5); C(S6); C(A0); C(A1); C(A2); C(A3); C(A4); C(A5); C(T8); C(T9); C(T10); C(T11); C(RA); C(T12); C(AT); C(GP); #undef C regs->r_regs[R_ZERO] = tp->tf_regs[FRAME_PC]; regs->r_regs[R_SP] = pcb->pcb_hw.apcb_usp; return (0); } int set_regs(p, regs) struct proc *p; struct reg *regs; { struct pcb *pcb = &p->p_addr->u_pcb; struct trapframe *tp = p->p_md.md_tf; tp = p->p_md.md_tf; #define C(r) tp->tf_regs[FRAME_ ## r] = regs->r_regs[R_ ## r] C(V0); C(T0); C(T1); C(T2); C(T3); C(T4); C(T5); C(T6); C(T7); C(S0); C(S1); C(S2); C(S3); C(S4); C(S5); C(S6); C(A0); C(A1); C(A2); C(A3); C(A4); C(A5); C(T8); C(T9); C(T10); C(T11); C(RA); C(T12); C(AT); C(GP); #undef C tp->tf_regs[FRAME_PC] = regs->r_regs[R_ZERO]; pcb->pcb_hw.apcb_usp = regs->r_regs[R_SP]; return (0); } #ifndef DDB void Debugger(const char *msg) { printf("Debugger(\"%s\") called.\n", msg); } #endif /* no DDB */ #include /* * Determine the size of the transfer, and make sure it is * within the boundaries of the partition. Adjust transfer * if needed, and signal errors or early completion. */ int bounds_check_with_label(struct buf *bp, struct disklabel *lp, int wlabel) { #if 0 struct partition *p = lp->d_partitions + dkpart(bp->b_dev); int labelsect = lp->d_partitions[0].p_offset; int maxsz = p->p_size, sz = (bp->b_bcount + DEV_BSIZE - 1) >> DEV_BSHIFT; /* overwriting disk label ? */ /* XXX should also protect bootstrap in first 8K */ if (bp->b_blkno + p->p_offset <= LABELSECTOR + labelsect && #if LABELSECTOR != 0 bp->b_blkno + p->p_offset + sz > LABELSECTOR + labelsect && #endif (bp->b_flags & B_READ) == 0 && wlabel == 0) { bp->b_error = EROFS; goto bad; } #if defined(DOSBBSECTOR) && defined(notyet) /* overwriting master boot record? */ if (bp->b_blkno + p->p_offset <= DOSBBSECTOR && (bp->b_flags & B_READ) == 0 && wlabel == 0) { bp->b_error = EROFS; goto bad; } #endif /* beyond partition? */ if (bp->b_blkno < 0 || bp->b_blkno + sz > maxsz) { /* if exactly at end of disk, return an EOF */ if (bp->b_blkno == maxsz) { bp->b_resid = bp->b_bcount; return(0); } /* or truncate if part of it fits */ sz = maxsz - bp->b_blkno; if (sz <= 0) { bp->b_error = EINVAL; goto bad; } bp->b_bcount = sz << DEV_BSHIFT; } bp->b_pblkno = bp->b_blkno + p->p_offset; return(1); bad: bp->b_flags |= B_ERROR; #endif return(-1); +} + +void atomic_add(u_int32_t* p, u_int32_t v) +{ + u_int32_t temp; + __asm__ __volatile__ ( + "1:\tldl_l %0,%2\n\t" /* load counter value, asserting lock */ + "addl %3,%0,%0\n\t" /* add our bits */ + "stl_c %0,%1\n\t" /* attempt to store */ + "beq %0,2f\n\t" /* if the store failed, spin */ + "br 3f\n" /* it worked, exit */ + "2:\tbr 1b\n" /* *p not updated, loop */ + "3:\tmb\n" /* it worked */ + : "=&r"(temp), "=m" (*p) + : "m"(*p), "r"(v) + : "memory"); } Index: head/sys/alpha/conf/GENERIC =================================================================== --- head/sys/alpha/conf/GENERIC (revision 38214) +++ head/sys/alpha/conf/GENERIC (revision 38215) @@ -1,93 +1,99 @@ # # GENERIC -- Generic machine with WD/AHx/NCR/BTx family disks # # For more information read the handbook part System Administration -> # Configuring the FreeBSD Kernel -> The Configuration File. # The handbook is available in /usr/share/doc/handbook or online as # latest version from the FreeBSD World Wide Web server # # # An exhaustive list of options and more detailed explanations of the # device lines is present in the ./LINT configuration file. If you are # in doubt as to the purpose or necessity of a line, check first in LINT. # -# $Id: GENERIC,v 1.1 1998/06/10 10:53:56 dfr Exp $ +# $Id: GENERIC,v 1.2 1998/08/07 08:16:31 dfr Exp $ machine "alpha" +cpu "EV4" cpu "EV5" ident GENERIC maxusers 10 # Platforms supported +options "DEC_AXPPCI_33" # UDB, Multia, AXPpci33, Noname options "DEC_EB164" # EB164, PC164, PC164LX, PC164SX +options "DEC_2100_A50" # AlphaStation 200, 250, 255, 400 options "DEC_KN20AA" # AlphaStation 500, 600 +options "DEC_ST550" # Personal Workstation 433, 500, 600 options INET #InterNETworking options FFS #Berkeley Fast Filesystem options NFS #Network Filesystem options MSDOSFS #MSDOS Filesystem options "CD9660" #ISO 9660 Filesystem options "CD9660_ROOT" #CD-ROM usable as root device options FFS_ROOT #FFS usable as root device [keep this!] options NFS_ROOT #NFS usable as root device options PROCFS #Process filesystem options "COMPAT_43" #Compatible with BSD 4.3 [KEEP THIS!] options SCSI_DELAY=15 #Be pessimistic about Joe SCSI device options UCONSOLE #Allow users to grab the console options FAILSAFE #Be conservative config kernel root on sd0 # Platform chipsets controller cia0 +controller apecs0 +controller lca0 # Standard busses controller pci0 controller isa0 # A single entry for any of these controllers (ncr, ahb, ahc, amd) is # sufficient for any number of installed devices. controller ncr0 controller isp0 controller scbus0 device sd0 device od0 device st0 device cd0 # real time clock device mcclock0 at isa0 port 0x70 # syscons is the default console driver, resembling an SCO console device sc0 at isa? port "IO_KBD" irq 1 device sio0 at isa0 port "IO_COM1" irq 4 device sio1 at isa0 port "IO_COM2" irq 3 flags 0x50 # Order is important here due to intrusive probes, do *not* alphabetize # this list of network interfaces until the probes have been fixed. # Right now it appears that the ie0 must be probed before ep0. See # revision 1.20 of this file. device de0 pseudo-device loop pseudo-device ether pseudo-device sl 1 pseudo-device ppp 1 pseudo-device tun 1 pseudo-device pty 16 pseudo-device gzip # Exec gzipped a.out's # KTRACE enables the system-call tracing facility ktrace(2). # This adds 4 KB bloat to your kernel, and slightly increases # the costs of each syscall. options KTRACE #kernel tracing # This provides support for System V shared memory. # options SYSVSHM options DDB options DB_ELF_SYMBOLS Index: head/sys/alpha/conf/Makefile.alpha =================================================================== --- head/sys/alpha/conf/Makefile.alpha (revision 38214) +++ head/sys/alpha/conf/Makefile.alpha (revision 38215) @@ -1,279 +1,284 @@ # Makefile.alpha -- with config changes. # Copyright 1990 W. Jolitz # from: @(#)Makefile.alpha 7.1 5/10/91 -# $Id: Makefile.alpha,v 1.5 1998/07/22 08:23:26 dfr Exp $ +# $Id: Makefile.alpha,v 1.6 1998/07/30 08:12:14 dfr Exp $ # # Makefile for FreeBSD # # This makefile is constructed from a machine description: # config machineid # Most changes should be made in the machine description # /sys/alpha/conf/``machineid'' # after which you should do # config machineid # Generic makefile changes should be made in # /sys/alpha/conf/Makefile.alpha # after which config should be rerun for all machines. # # Which version of config(8) is required. %VERSREQ= 300005 BINFORMAT?= elf STD8X16FONT?= iso .if exists(./@/.) S= ./@ .else S= ../.. .endif ALPHA= ${S}/alpha HCC?=${CC} SIZE?=size COPTFLAGS?=-O INCLUDES= -nostdinc -I- -I. -I$S # This hack is to allow kernel compiles to succeed on machines w/out srcdist .if exists($S/../include) INCLUDES+= -I$S/../include .else INCLUDES+= -I/usr/include .endif COPTS= ${INCLUDES} ${IDENT} -DKERNEL -include opt_global.h -U__NetBSD__ CFLAGS= ${COPTFLAGS} ${CWARNFLAGS} ${DEBUG} ${COPTS} -mno-fp-regs -Wa,-mev56 LOAD_ADDRESS?= 0xfffffc0000300000 DEFINED_PROF= ${PROF} .if defined(PROF) CFLAGS+= -malign-functions=4 .if ${PROFLEVEL} >= 2 IDENT+= -DGPROF4 -DGUPROF PROF+= -mprofiler-epilogue .endif .endif NORMAL_C= ${CC} -c ${CFLAGS} ${PROF} $< NORMAL_C_C= ${CC} -c ${CFLAGS} ${PROF} ${PARAM} $< # XXX LOCORE means "don't declare C stuff" not "for locore.s". NORMAL_S= ${CC} -c -x assembler-with-cpp -DLOCORE ${COPTS} $< DRIVER_C= ${CC} -c ${CFLAGS} ${PROF} $< DRIVER_C_C= ${CC} -c ${CFLAGS} ${PROF} ${PARAM} $< DRIVER_S= ${CC} -c -x assembler-with-cpp -DLOCORE ${COPTS} $< PROFILE_C= ${CC} -c ${CFLAGS} ${PARAM} $< NORMAL_M= sh $S/kern/makedevops.sh -c $<;\ ${CC} -c ${CFLAGS} ${PROF} `basename $< .m`.c # ${ALPHA}/alpha/setdef0.c and ${ALPHA}/alpha/setdef1.c are intentionally # omitted from SYSTEM_CFILES. They depend on setdefs.h, a header which # is generated from all of ${OBJS}. We don't want to have to compile # everything just to do a make depend. SYSTEM_CFILES= ioconf.c param.c vnode_if.c config.c SYSTEM_SFILES= ${ALPHA}/alpha/locore.s SYSTEM_DEP= Makefile symbols.exclude symbols.sort ${SYSTEM_OBJS} .if ${CFLAGS:M-g} == "" SYMORDER_EXCLUDE=-x symbols.exclude .endif SYSTEM_LD_HEAD= @echo loading $@; rm -f $@ .if ${BINFORMAT} == elf SYSTEM_OBJS= locore.o setdef0.o vnode_if.o \ ${OBJS} ioconf.o param.o config.o \ - setdef1.o + setdef1.o hack.so SYSTEM_LD= @${LD} --export-dynamic -T$S/alpha/conf/kernel.script -e locorestart \ -o $@ -X ${SYSTEM_OBJS} vers.o SYSTEM_LD_TAIL= @${SIZE} $@; chmod 755 $@ .endif %BEFORE_DEPEND %OBJS %CFILES %SFILES %LOAD %CLEAN clean: rm -f *.o *.s eddep errs genassym gensetdefs kernel linterrs \ makelinks param.c setdefs.h symbols.exclude symbols.sort tags \ vers.c vnode_if.c vnode_if.h ${CLEAN} #lint: /tmp param.c # @lint -hbxn -DGENERIC -Dvolatile= ${COPTS} ${PARAM} \ # ${ALPHA}/alpha/Locore.c ${CFILES} ioconf.c param.c | \ # grep -v 'struct/union .* never defined' | \ # grep -v 'possible pointer alignment problem' symbols.exclude: Makefile echo "gcc2_compiled." >symbols.exclude echo "___gnu_compiled_c" >>symbols.exclude symbols.sort: ${ALPHA}/alpha/symbols.raw grep -v '^#' ${ALPHA}/alpha/symbols.raw \ | sed 's/^ //' | sort -u > symbols.sort locore.o: ${ALPHA}/alpha/locore.s assym.s ${NORMAL_S} + +hack.so: Makefile + echo "void __elf_kld_hack() {}" > hack.c + ${CC} -shared -nostdlib hack.c -o hack.so + rm -f hack.c setdef0.o: ${ALPHA}/alpha/setdef0.c setdefs.h ${NORMAL_C} setdef1.o: ${ALPHA}/alpha/setdef1.c setdefs.h ${NORMAL_C} setdefs.h: gensetdefs ${OBJS} @echo Generating kernel linker sets @./gensetdefs ${OBJS} >setdefs.h gensetdefs: gensetdefs.o ${HCC} -static gensetdefs.o -o $@ gensetdefs.o: ${ALPHA}/alpha/gensetdefs.c ${HCC} -c -I${INCLUDES} ${ALPHA}/alpha/gensetdefs.c # everything potentially depends on the Makefile since everything potentially # depends on the options. Some things are more dependent on the Makefile for # historical reasons. machdep.o: Makefile # the following is necessary because autoconf.o depends on #if GENERIC autoconf.o: Makefile # XXX - may no longer be needed locore.o: Makefile # depends on KDB (cons.o also depends on GENERIC) trap.o cons.o: Makefile # this rule stops ./assym.s in .depend from causing problems ./assym.s: assym.s assym.s: genassym ./genassym >assym.s # Some of the defines that genassym outputs may well depend on the # value of kernel options. genassym.o: ${ALPHA}/alpha/genassym.c Makefile opt_global.h ${HCC} -c ${COPTS} ${PARAM} -UKERNEL ${ALPHA}/alpha/genassym.c genassym: genassym.o ${HCC} -static ${COPTS} ${PARAM} genassym.o -o $@ SYSTEM_OBJS+= __divqu.o __divq.o __divlu.o __divl.o SYSTEM_OBJS+= __remqu.o __remq.o __remlu.o __reml.o CLEAN+= __divqu.S __divq.S __divlu.S __divl.S CLEAN+= __remqu.S __remq.S __remlu.S __reml.S __divqu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divqu')define(OP,\`div')define(S,\`false')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __divq.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divq')define(OP,\`div')define(S,\`true')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __divlu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divlu')define(OP,\`div')define(S,\`false')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __divl.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divl')define(OP,\`div')define(S,\`true')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __remqu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__remqu')define(OP,\`rem')define(S,\`false')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __remq.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__remq')define(OP,\`rem')define(S,\`true')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __remlu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__remlu')define(OP,\`rem')define(S,\`false')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __reml.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__reml')define(OP,\`rem')define(S,\`true')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} ${OBJS}: opt_global.h # XXX this assumes that the options for NORMAL_C* and DRIVER_C* are identical. depend: assym.s param.c vnode_if.h ${BEFORE_DEPEND} rm -f .newdep mkdep -a -f .newdep ${COPTS} ${CFILES} ${SYSTEM_CFILES} mkdep -a -f .newdep ${COPTS} ${PARAM} -UKERNEL ${ALPHA}/alpha/genassym.c MKDEP_CPP="${CC} -E -x assembler-with-cpp" ; export MKDEP_CPP ; \ mkdep -a -f .newdep -DLOCORE ${COPTS} ${SFILES} ${SYSTEM_SFILES} rm -f .depend mv -f .newdep .depend cleandepend: rm -f .depend links: egrep '#if' ${CFILES:Nswapkernel.c} | sed -f $S/conf/defines | \ sed -e 's/:.*//' -e 's/\.c/.o/' | sort -u > dontlink echo ${CFILES:Nswapkernel.c} | tr -s ' ' '\12' | sed 's/\.c/.o/' | \ sort -u | comm -23 - dontlink | \ sed 's,../.*/\(.*.o\),rm -f \1;ln -s ../GENERIC/\1 \1,' > makelinks sh makelinks && rm -f dontlink tags: @echo "see $S/kern/Makefile for tags" install: @if [ ! -f kernel ] ; then \ echo "You must first build your kernel before trying to install." ; \ exit 1 ; \ fi .if exists(${DESTDIR}/kernel) chflags noschg ${DESTDIR}/kernel mv ${DESTDIR}/kernel ${DESTDIR}/kernel.old .endif PATH=$${PATH}:/sbin:/usr/sbin; \ if [ `sysctl -n kern.bootfile` = ${DESTDIR}/kernel ] ; then \ sysctl -w kern.bootfile=${DESTDIR}/kernel.old ; \ if [ -f /var/db/kvm_kernel.db ] ; then \ mv -f /var/db/kvm_kernel.db /var/db/kvm_kernel.old.db ; \ fi \ fi install -c -m 555 -o root -g wheel -fschg kernel ${DESTDIR}/ ioconf.o: ioconf.c $S/sys/param.h $S/sys/buf.h ${CC} -c ${CFLAGS} ioconf.c param.c: $S/conf/param.c -rm -f param.c cp $S/conf/param.c . param.o: param.c Makefile ${CC} -c ${CFLAGS} ${PARAM} param.c vers.o: ${SYSTEM_DEP} ${SYSTEM_SWAP_DEP} sh $S/conf/newvers.sh ${KERN_IDENT} ${IDENT} ${CC} ${CFLAGS} -c vers.c vnode_if.c: $S/kern/vnode_if.sh $S/kern/vnode_if.src sh $S/kern/vnode_if.sh $S/kern/vnode_if.src vnode_if.h: $S/kern/vnode_if.sh $S/kern/vnode_if.src sh $S/kern/vnode_if.sh $S/kern/vnode_if.src .include %RULES # DO NOT DELETE THIS LINE -- make depend uses it Index: head/sys/alpha/conf/NOTES =================================================================== --- head/sys/alpha/conf/NOTES (revision 38214) +++ head/sys/alpha/conf/NOTES (revision 38215) @@ -1,93 +1,99 @@ # # GENERIC -- Generic machine with WD/AHx/NCR/BTx family disks # # For more information read the handbook part System Administration -> # Configuring the FreeBSD Kernel -> The Configuration File. # The handbook is available in /usr/share/doc/handbook or online as # latest version from the FreeBSD World Wide Web server # # # An exhaustive list of options and more detailed explanations of the # device lines is present in the ./LINT configuration file. If you are # in doubt as to the purpose or necessity of a line, check first in LINT. # -# $Id: GENERIC,v 1.1 1998/06/10 10:53:56 dfr Exp $ +# $Id: GENERIC,v 1.2 1998/08/07 08:16:31 dfr Exp $ machine "alpha" +cpu "EV4" cpu "EV5" ident GENERIC maxusers 10 # Platforms supported +options "DEC_AXPPCI_33" # UDB, Multia, AXPpci33, Noname options "DEC_EB164" # EB164, PC164, PC164LX, PC164SX +options "DEC_2100_A50" # AlphaStation 200, 250, 255, 400 options "DEC_KN20AA" # AlphaStation 500, 600 +options "DEC_ST550" # Personal Workstation 433, 500, 600 options INET #InterNETworking options FFS #Berkeley Fast Filesystem options NFS #Network Filesystem options MSDOSFS #MSDOS Filesystem options "CD9660" #ISO 9660 Filesystem options "CD9660_ROOT" #CD-ROM usable as root device options FFS_ROOT #FFS usable as root device [keep this!] options NFS_ROOT #NFS usable as root device options PROCFS #Process filesystem options "COMPAT_43" #Compatible with BSD 4.3 [KEEP THIS!] options SCSI_DELAY=15 #Be pessimistic about Joe SCSI device options UCONSOLE #Allow users to grab the console options FAILSAFE #Be conservative config kernel root on sd0 # Platform chipsets controller cia0 +controller apecs0 +controller lca0 # Standard busses controller pci0 controller isa0 # A single entry for any of these controllers (ncr, ahb, ahc, amd) is # sufficient for any number of installed devices. controller ncr0 controller isp0 controller scbus0 device sd0 device od0 device st0 device cd0 # real time clock device mcclock0 at isa0 port 0x70 # syscons is the default console driver, resembling an SCO console device sc0 at isa? port "IO_KBD" irq 1 device sio0 at isa0 port "IO_COM1" irq 4 device sio1 at isa0 port "IO_COM2" irq 3 flags 0x50 # Order is important here due to intrusive probes, do *not* alphabetize # this list of network interfaces until the probes have been fixed. # Right now it appears that the ie0 must be probed before ep0. See # revision 1.20 of this file. device de0 pseudo-device loop pseudo-device ether pseudo-device sl 1 pseudo-device ppp 1 pseudo-device tun 1 pseudo-device pty 16 pseudo-device gzip # Exec gzipped a.out's # KTRACE enables the system-call tracing facility ktrace(2). # This adds 4 KB bloat to your kernel, and slightly increases # the costs of each syscall. options KTRACE #kernel tracing # This provides support for System V shared memory. # options SYSVSHM options DDB options DB_ELF_SYMBOLS Index: head/sys/alpha/conf/files.alpha =================================================================== --- head/sys/alpha/conf/files.alpha (revision 38214) +++ head/sys/alpha/conf/files.alpha (revision 38215) @@ -1,125 +1,130 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # -# $Id: files.alpha,v 1.3 1998/07/12 16:26:52 dfr Exp $ +# $Id: files.alpha,v 1.4 1998/07/22 08:24:39 dfr Exp $ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # # font8x16.o optional std8x16font \ compile-with "uudecode < /usr/share/syscons/fonts/${STD8X16FONT}-8x16.fnt && file2c 'unsigned char font_16[16*256] = {' '};' < ${STD8X16FONT}-8x16 > font8x16.c && ${CC} -c ${CFLAGS} font8x16.c" \ no-implicit-rule before-depend \ clean "${STD8X16FONT}-8x16 font8x16.c" # alpha/alpha/autoconf.c standard device-driver alpha/alpha/cpuconf.c standard alpha/alpha/dec_kn8ae.c optional dec_kn8ae alpha/alpha/dec_eb164.c optional dec_eb164 alpha/alpha/dec_kn20aa.c optional dec_kn20aa +alpha/alpha/dec_2100_a50.c optional dec_2100_a50 +alpha/alpha/dec_st550.c optional dec_st550 +alpha/alpha/dec_axppci_33.c optional dec_axppci_33 alpha/alpha/mountroot.c optional slice alpha/alpha/ipl_funcs.c standard alpha/alpha/pal.s standard alpha/alpha/cons.c standard alpha/alpha/prom.c standard alpha/alpha/promcons.c standard alpha/alpha/prom_disp.s standard alpha/alpha/alpha-gdbstub.c optional ddb alpha/alpha/db_disasm.c optional ddb alpha/alpha/db_interface.c optional ddb alpha/alpha/db_trace.c optional ddb alpha/alpha/exception.s standard alpha/alpha/in_cksum.c optional inet # locore.s needs to be handled in Makefile to put it first. Otherwise it's # now normal. # alpha/alpha/locore.s standard alpha/alpha/machdep.c standard alpha/alpha/math_emulate.c optional math_emulate alpha/alpha/mem.c standard alpha/alpha/mp_machdep.c optional smp alpha/alpha/perfmon.c optional perfmon profiling-routine alpha/alpha/perfmon.c optional perfmon alpha/alpha/pmap.c standard alpha/alpha/procfs_machdep.c standard alpha/alpha/simplelock.s optional smp alpha/alpha/support.s standard alpha/alpha/swtch.s standard alpha/alpha/sys_machdep.c standard alpha/alpha/trap.c standard alpha/alpha/interrupt.c standard alpha/alpha/userconfig.c optional userconfig alpha/alpha/vm_machdep.c standard alpha/alpha/clock.c standard alpha/alpha/clock_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "clock_if.c" clock_if.h standard \ dependency "$S/kern/makedevops.sh $S/alpha/alpha/clock_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/alpha/alpha/clock_if.m" \ no-obj no-implicit-rule before-depend \ clean "clock_if.h" alpha/alpha/diskslice_machdep.c standard alpha/tlsb/tlsb.c optional tlsb alpha/tlsb/gbus.c optional gbus alpha/tlsb/kftxx.c optional kft alpha/tlsb/mcclock_tlsb.c optional gbus alpha/tlsb/zs_tlsb.c optional gbus alpha/tlsb/dwlpx.c optional dwlpx dev/dec/mcclock.c standard dev/dec/mcclock_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "mcclock_if.c" mcclock_if.h standard \ dependency "$S/kern/makedevops.sh $S/dev/dec/mcclock_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/dev/dec/mcclock_if.m" \ no-obj no-implicit-rule before-depend \ clean "mcclock_if.h" alpha/pci/cia.c optional cia alpha/pci/pci_eb164_intr.s optional cia alpha/isa/mcclock_isa.c optional cia +alpha/pci/apecs.c optional apecs +alpha/pci/lca.c optional lca alpha/pci/pcibus.c optional pci alpha/isa/isa.c optional isa kern/link_elf.c standard kern/subr_bus.c standard kern/device_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "device_if.c" device_if.h standard \ dependency "$S/kern/makedevops.sh $S/kern/device_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/kern/device_if.m" \ no-obj no-implicit-rule before-depend \ clean "device_if.h" kern/bus_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "bus_if.c" bus_if.h standard \ dependency "$S/kern/makedevops.sh $S/kern/bus_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/kern/bus_if.m" \ no-obj no-implicit-rule before-depend \ clean "bus_if.h" libkern/bcd.c standard libkern/bcmp.c standard libkern/ffs.c standard libkern/inet_ntoa.c standard libkern/index.c standard libkern/mcount.c optional profiling-routine libkern/qsort.c standard libkern/random.c standard libkern/scanc.c standard libkern/skpc.c standard libkern/strcat.c standard libkern/strcmp.c standard libkern/strcpy.c standard libkern/strlen.c standard libkern/strncmp.c standard libkern/strncpy.c standard libkern/alpha/htonl.S standard libkern/alpha/htons.S standard libkern/alpha/ntohl.S standard libkern/alpha/ntohs.S standard isa/sio.c optional sio device-driver isa/kbdio.c optional psm device-driver isa/kbdio.c optional sc device-driver isa/syscons.c optional sc device-driver Index: head/sys/alpha/conf/kernel.script =================================================================== --- head/sys/alpha/conf/kernel.script (revision 38214) +++ head/sys/alpha/conf/kernel.script (revision 38215) @@ -1,133 +1,132 @@ OUTPUT_FORMAT("elf64-alpha", "elf64-alpha", "elf64-alpha") OUTPUT_ARCH(alpha) ENTRY(__start) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/egcs/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/egcs/alphaev5-unknown-linux-gnu/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + kernel_text = 0xfffffc0000300000; SECTIONS { /* Read-only sections, merged into text segment: */ . = 0xfffffc0000300000 + SIZEOF_HEADERS; .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .gnu.version : { *(.gnu.version) } .gnu.version_d : { *(.gnu.version_d) } .gnu.version_r : { *(.gnu.version_r) } .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) } .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) } .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) } .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) } .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } .rel.init : { *(.rel.init) } .rela.init : { *(.rela.init) } .rel.fini : { *(.rel.fini) } .rela.fini : { *(.rela.fini) } .rel.bss : { *(.rel.bss) } .rela.bss : { *(.rela.bss) } .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } =0x47ff041f .text : { *(.text) *(.stub) /* .gnu.warning sections are handled specially by elf32.em. */ *(.gnu.warning) *(.gnu.linkonce.t*) } =0x47ff041f _etext = .; PROVIDE (etext = .); .fini : { *(.fini) } =0x47ff041f .rodata : { *(.rodata) *(.gnu.linkonce.r*) } .rodata1 : { *(.rodata1) } .reginfo : { *(.reginfo) } /* Adjust the address for the data segment. We want to adjust up to the same address within the page on the next page up. */ . = .; .data : { *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS } .data1 : { *(.data1) } .ctors : { *(.ctors) } .dtors : { *(.dtors) } .plt : { *(.plt) } .got : { *(.got.plt) *(.got) } .dynamic : { *(.dynamic) } /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ .sdata : { *(.sdata) } _edata = .; PROVIDE (edata = .); __bss_start = .; .sbss : { *(.sbss) *(.scommon) } .bss : { *(.dynbss) *(.bss) *(COMMON) } . = ALIGN(64 / 8); _end = . ; PROVIDE (end = .); /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } /* These must appear regardless of . */ } Index: head/sys/alpha/conf/options.alpha =================================================================== --- head/sys/alpha/conf/options.alpha (revision 38214) +++ head/sys/alpha/conf/options.alpha (revision 38215) @@ -1,36 +1,39 @@ -# $Id: options.alpha,v 1.2 1998/07/12 16:28:09 dfr Exp $ +# $Id: options.alpha,v 1.3 1998/07/22 08:24:39 dfr Exp $ EV5 opt_global.h DEC_KN8AE opt_cpu.h DEC_EB164 opt_cpu.h DEC_KN20AA opt_cpu.h +DEC_2100_A50 opt_cpu.h +DEC_ST550 opt_cpu.h +DEC_AXPPCI_33 opt_cpu.h ATAPI opt_atapi.h ATAPI_STATIC opt_atapi.h CMD640 opt_wd.h SHOW_BUSYBUFS PANIC_REBOOT_WAIT_TIME opt_panic.h AHC_TAGENABLE opt_aic7xxx.h AHC_SCBPAGING_ENABLE opt_aic7xxx.h AHC_ALLOW_MEMIO opt_aic7xxx.h AHC_SHARE_SCBS opt_aic7xxx.h SC_SPLASH_SCREEN opt_syscons.h MAXCONS opt_syscons.h SLOW_VGA opt_syscons.h STD8X16FONT opt_syscons.h SC_HISTORY_SIZE opt_syscons.h SC_DISABLE_REBOOT opt_syscons.h SC_MOUSE_CHAR opt_syscons.h PSM_HOOKAPM opt_psm.h PSM_RESETAFTERSUSPEND opt_psm.h PSM_DEBUG opt_psm.h KBD_RESETDELAY opt_kbdio.h KBD_MAXRETRY opt_kbdio.h KBD_MAXWAIT opt_kbdio.h KBDIO_DEBUG opt_kbdio.h Index: head/sys/alpha/include/chipset.h =================================================================== --- head/sys/alpha/include/chipset.h (revision 38214) +++ head/sys/alpha/include/chipset.h (revision 38215) @@ -1,100 +1,100 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: chipset.h,v 1.2 1998/07/12 16:16:22 dfr Exp $ + * $Id: chipset.h,v 1.3 1998/07/22 08:25:39 dfr Exp $ */ #ifndef _MACHINE_CHIPSET_H_ #define _MACHINE_CHIPSET_H_ typedef u_int8_t alpha_chipset_inb_t(u_int32_t port); typedef u_int16_t alpha_chipset_inw_t(u_int32_t port); typedef u_int32_t alpha_chipset_inl_t(u_int32_t port); typedef void alpha_chipset_outb_t(u_int32_t port, u_int8_t data); typedef void alpha_chipset_outw_t(u_int32_t port, u_int16_t data); typedef void alpha_chipset_outl_t(u_int32_t port, u_int32_t data); typedef u_int8_t alpha_chipset_readb_t(u_int32_t pa); typedef u_int16_t alpha_chipset_readw_t(u_int32_t pa); typedef u_int32_t alpha_chipset_readl_t(u_int32_t pa); typedef void alpha_chipset_writeb_t(u_int32_t pa, u_int8_t data); typedef void alpha_chipset_writew_t(u_int32_t pa, u_int16_t data); typedef void alpha_chipset_writel_t(u_int32_t pa, u_int32_t data); typedef int alpha_chipset_maxdevs_t(u_int bus); typedef u_int8_t alpha_chipset_cfgreadb_t(u_int, u_int, u_int, u_int); typedef u_int16_t alpha_chipset_cfgreadw_t(u_int, u_int, u_int, u_int); typedef u_int32_t alpha_chipset_cfgreadl_t(u_int, u_int, u_int, u_int); typedef void alpha_chipset_cfgwriteb_t(u_int, u_int, u_int, u_int, u_int8_t); typedef void alpha_chipset_cfgwritew_t(u_int, u_int, u_int, u_int, u_int16_t); typedef void alpha_chipset_cfgwritel_t(u_int, u_int, u_int, u_int, u_int32_t); typedef struct alpha_chipset { /* * I/O port access */ alpha_chipset_inb_t* inb; alpha_chipset_inw_t* inw; alpha_chipset_inl_t* inl; alpha_chipset_outb_t* outb; alpha_chipset_outw_t* outw; alpha_chipset_outl_t* outl; /* * Memory access */ alpha_chipset_readb_t* readb; alpha_chipset_readw_t* readw; alpha_chipset_readl_t* readl; alpha_chipset_writeb_t* writeb; alpha_chipset_writew_t* writew; alpha_chipset_writel_t* writel; /* * PCI configuration access */ alpha_chipset_maxdevs_t* maxdevs; alpha_chipset_cfgreadb_t* cfgreadb; alpha_chipset_cfgreadw_t* cfgreadw; alpha_chipset_cfgreadl_t* cfgreadl; alpha_chipset_cfgwriteb_t* cfgwriteb; alpha_chipset_cfgwritew_t* cfgwritew; alpha_chipset_cfgwritel_t* cfgwritel; /* - * PCI bridge device. + * PCI interrupt device. * (XXX hack until I change pci code to use new * device framework.) */ - void* bridge; + void* intrdev; } alpha_chipset_t; extern alpha_chipset_t chipset; #endif /* !_MACHINE_CHIPSET_H_ */ Index: head/sys/alpha/include/cpuconf.h =================================================================== --- head/sys/alpha/include/cpuconf.h (revision 38214) +++ head/sys/alpha/include/cpuconf.h (revision 38215) @@ -1,121 +1,122 @@ /* $NetBSD: cpuconf.h,v 1.7 1997/11/06 00:42:03 thorpej Exp $ */ #ifndef _ALPHA_CPUCONF_H #define _ALPHA_CPUCONF_H /* * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Christopher G. Demetriou * for the NetBSD Project. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Additional reworking by Matthew Jacob for NASA/Ames Research Center. * Copyright (c) 1997 */ #ifdef KERNEL /* * Platform Specific Information and Function Hooks. * * The tags family and model information are strings describing the platform. * * The tag iobus describes the primary iobus for the platform- primarily * to give a hint as to where to start configuring. The likely choices * are one of tcasic, lca, apecs, cia, or tlsb. * */ struct device; /* XXX */ extern struct platform { /* * Platform Information. */ const char *family; /* Family Name */ const char *model; /* Model (variant) Name */ const char *iobus; /* Primary iobus name */ /* * Platform Specific Function Hooks * cons_init - console initialization * device_register - boot configuration aid * iointr - I/O interrupt handler * clockintr - Clock Interrupt Handler * mcheck_handler - Platform Specific Machine Check Handler */ void (*cons_init) __P((void)); void (*device_register) __P((struct device *, void *)); void (*iointr) __P((void *, unsigned long)); void (*clockintr) __P((void *)); void (*mcheck_handler) __P((unsigned long, struct trapframe *, unsigned long, unsigned long)); + void (*pci_intr_init) __P((void)); void (*pci_intr_map) __P((void *)); void (*pci_intr_disable) __P((int)); void (*pci_intr_enable) __P((int)); } platform; /* * Lookup table entry for Alpha system variations. */ struct alpha_variation_table { u_int64_t avt_variation; /* variation, from HWRPB */ const char *avt_model; /* model string */ }; /* * There is an array of functions to initialize the platform structure. * * It's responsible for filling in the family, model_name and iobus * tags. It may optionally fill in the cons_init, device_register and * mcheck_handler tags. * * The iointr tag is filled in by set_iointr (in interrupt.c). * The clockintr tag is filled in by cpu_initclocks (in clock.c). * * nocpu is function to call when you can't figure what platform you're on. * There's no return from this function. */ struct cpuinit { void (*init) __P((int)); const char *option; }; #define cpu_notsupp(st) { platform_not_supported, st } #define cpu_init(fn, opt) { fn, opt } /* * Misc. support routines. */ const char *alpha_dsr_sysname __P((void)); const char *alpha_variation_name __P((u_int64_t variation, const struct alpha_variation_table *avtp)); const char *alpha_unknown_sysname __P((void)); extern struct cpuinit cpuinit[]; extern int ncpuinit; extern void platform_not_configured __P((int)); extern void platform_not_supported __P((int)); #endif /* KERNEL */ #endif /* !_ALPHA_CPUCONF_H */ Index: head/sys/alpha/include/intr.h =================================================================== --- head/sys/alpha/include/intr.h (revision 38214) +++ head/sys/alpha/include/intr.h (revision 38215) @@ -1,46 +1,46 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id$ + * $Id: intr.h,v 1.2 1998/07/12 16:09:30 dfr Exp $ */ #ifndef _MACHINE_INTR_H_ #define _MACHINE_INTR_H_ LIST_HEAD(alpha_intr_list, alpha_intr); struct alpha_intr { LIST_ENTRY(alpha_intr) list; /* chain handlers in this hash bucket */ int vector; /* vector to match */ driver_intr_t *intr; /* handler function */ void *arg; /* argument to handler */ }; struct alpha_intr *alpha_create_intr(int vector, driver_intr_t *intr, void *arg); int alpha_connect_intr(struct alpha_intr *i); -void alpha_dispatch_intr(int vector); +void alpha_dispatch_intr(void *frame, unsigned long vector); #endif /* !_MACHINE_INTR_H_ */ Index: head/sys/alpha/include/rpb.h =================================================================== --- head/sys/alpha/include/rpb.h (revision 38214) +++ head/sys/alpha/include/rpb.h (revision 38215) @@ -1,393 +1,431 @@ /* $NetBSD: rpb.h,v 1.20 1998/04/15 00:47:33 mjacob Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. * All rights reserved. * * Author: Keith Bostic, Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ /* * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, * EK-D3SYS-PM.B01. */ /* * HWRPB (Hardware Restart Parameter Block). */ #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ #ifndef ASSEMBLER struct rpb { u_int64_t rpb_phys; /* 0: HWRPB phys. address. */ char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ u_int64_t rpb_version; /* 10 */ u_int64_t rpb_size; /* 18: HWRPB size in bytes */ u_int64_t rpb_primary_cpu_id; /* 20 */ u_int64_t rpb_page_size; /* 28: (8192) */ u_int64_t rpb_phys_addr_size; /* 30: (34) */ u_int64_t rpb_max_asn; /* 38: (16) */ char rpb_ssn[16]; /* 40: only first 10 valid */ #define ST_ADU 1 /* Alpha Demo. Unit (?) */ #define ST_DEC_4000 2 /* "Cobra" (?) */ #define ST_DEC_7000 3 /* "Ruby" (?) */ #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ #define ST_DEC_3000_300 7 /* "Pelican" (TC) */ #define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */ #define ST_DEC_2100_A500 9 /* "Sable" (?) */ #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME?) */ #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */ #define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */ #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ #define ST_DEC_MUSTANG 14 /* "Mustang" (?) */ #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */ #define ST_DEC_1000 17 /* "Mikasa" (PCI/ISA?) */ #define ST_EB66 19 /* EB66 (PCI/ISA?) */ #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */ #define ST_ALPHABOOK1 21 /* Alphabook (?) */ #define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */ #define ST_DEC_EV45_PBP 23 /* "Lego" (?) */ #define ST_DEC_2100A_A500 24 /* "Lynx" (?) */ #define ST_EB164 26 /* EB164 (PCI/ISA) */ #define ST_DEC_1000A 27 /* "Noritake" (?) */ #define ST_DEC_ALPHAVME_224 28 /* "Cortex" (?) */ #define ST_DEC_EV56_PBP 32 /* "Takara" (?) */ #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME?) */ u_int64_t rpb_type; /* 50: */ #define SV_MPCAP 0x00000001 /* multiprocessor capable */ #define SV_CONSOLE 0x0000001e /* console hardware mask */ #define SV_CONSOLE_DETACHED 0x00000002 #define SV_CONSOLE_EMBEDDED 0x00000004 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */ #define SV_PF_UNITED 0x00000020 #define SV_PF_SEPARATE 0x00000040 #define SV_PF_BBACKUP 0x00000060 #define SV_PF_ACTION 0x00000100 /* powerfail restart */ #define SV_GRAPHICS 0x00000200 /* graphic engine present */ #define SV_ST_MASK 0x0000fc00 /* system type mask */ #define SV_ST_RESERVED 0x00000000 /* RESERVED */ /* * System types for the DEC 3000/500 (Flamingo) Family */ #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ /* * System types for ??? */ #define SV_ST_SABLE 0x00000400 /* Sable (???) */ /* * System types for the DEC 3000/300 (Pelican) Family */ #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ /* * System types for the AlphaStation Family */ #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */ #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */ #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */ #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */ #define SV_ST_AVANTI_4_266 0x00002000 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */ +#define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */ + +/* + * System types for the AXPvme Family + */ +#define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */ +#define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */ +#define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */ +#define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */ +#define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */ +#define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */ +#define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */ + +/* + * System types for the EB164 Family + */ +#define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */ +#define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */ +#define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */ +#define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */ +#define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */ +#define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */ +#define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */ +#define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */ +#define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */ +#define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */ +#define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */ +#define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */ +#define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */ +#define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */ +#define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */ + +/* + * System types for the Digital Personal Workstation (Miata) Family + * XXX These are not very complete! + */ +#define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */ + u_int64_t rpb_variation; /* 58 */ char rpb_revision[8]; /* 60; only first 4 valid */ u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ vm_offset_t rpb_vptb; /* 78: */ u_int64_t rpb_reserved_arch; /* 80: */ vm_offset_t rpb_tbhint_off; /* 88: */ u_int64_t rpb_pcs_cnt; /* 90: */ u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */ u_int64_t rpb_ctb_cnt; /* A8: console terminal */ u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ vm_offset_t rpb_ctb_off; /* B8: offset to ctb */ vm_offset_t rpb_crb_off; /* C0: offset to crb */ vm_offset_t rpb_memdat_off; /* C8: memory data offset */ vm_offset_t rpb_condat_off; /* D0: config data offset */ vm_offset_t rpb_fru_off; /* D8: FRU table offset */ u_int64_t rpb_save_term; /* E0: terminal save */ u_int64_t rpb_save_term_val; /* E8: */ u_int64_t rpb_rest_term; /* F0: terminal restore */ u_int64_t rpb_rest_term_val; /* F8: */ u_int64_t rpb_restart; /* 100: restart */ u_int64_t rpb_restart_val; /* 108: */ u_int64_t rpb_reserve_os; /* 110: */ u_int64_t rpb_reserve_hw; /* 118: */ u_int64_t rpb_checksum; /* 120: HWRPB checksum */ u_int64_t rpb_rxrdy; /* 128: receive ready */ u_int64_t rpb_txrdy; /* 130: transmit ready */ vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ u_int64_t rpb_tbhint[8]; /* 149: TB hint block */ }; /* * PCS: Per-CPU information. */ struct pcs { u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ #define PCS_BIP 0x000001 /* boot in progress */ #define PCS_RC 0x000002 /* restart possible */ #define PCS_PA 0x000004 /* processor available */ #define PCS_PP 0x000008 /* processor present */ #define PCS_OH 0x000010 /* user halted */ #define PCS_CV 0x000020 /* context valid */ #define PCS_PV 0x000040 /* PALcode valid */ #define PCS_PMV 0x000080 /* PALcode memory valid */ #define PCS_PL 0x000100 /* PALcode loaded */ #define PCS_HALT_REQ 0xff0000 /* halt request mask */ #define PCS_HALT_DEFAULT 0x000000 #define PCS_HALT_SAVE_EXIT 0x010000 #define PCS_HALT_COLD_BOOT 0x020000 #define PCS_HALT_WARM_BOOT 0x030000 #define PCS_HALT_STAY_HALTED 0x040000 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ u_int64_t pcs_flags; /* 80: */ u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */ vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */ struct { u_int64_t minorrev : 8, /* alphabetic char 'a' - 'z' */ majorrev : 8, /* alphabetic char 'a' - 'z' */ #define PAL_TYPE_STANDARD 0 #define PAL_TYPE_VMS 1 #define PAL_TYPE_OSF1 2 pal_type : 8, /* PALcode type: * 0 == standard * 1 == OpenVMS * 2 == OSF/1 * 3-127 DIGITAL reserv. * 128-255 non-DIGITAL reserv. */ sbz1 : 8, compatibility : 16, /* Compatibility revision */ proc_cnt : 16; /* Processor count */ } pcs_pal_rev; /* A8: */ #define pcs_minorrev pcs_pal_rev.minorrev #define pcs_majorrev pcs_pal_rev.majorrev #define pcs_pal_type pcs_pal_rev.pal_type #define pcs_compatibility pcs_pal_rev.compatibility #define pcs_proc_cnt pcs_pal_rev.proc_cnt u_int64_t pcs_proc_type; /* B0: processor type */ #define PCS_PROC_MAJOR 0x00000000ffffffff #define PCS_PROC_MAJORSHIFT 0 #define PCS_PROC_EV3 1 /* EV3 */ #define PCS_PROC_EV4 2 /* EV4: 21064 */ #define PCS_PROC_SIMULATION 3 /* Simulation */ #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ #define PCS_PROC_EV5 5 /* EV5: 21164 */ #define PCS_PROC_EV45 6 /* EV45: 21064A */ #define PCS_PROC_EV56 7 /* EV56: 21164A */ #define PCS_PROC_EV6 8 /* EV6: 21264 */ #define PCS_PROC_PCA56 9 /* PCA256: 21164PC */ #define PCS_PROC_MINOR 0xffffffff00000000 #define PCS_PROC_MINORSHIFT 32 /* Minor number interpretation is processor specific. See cpu.c. */ u_int64_t pcs_proc_var; /* B8: processor variation. */ #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */ #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */ char pcs_proc_revision[8]; /* C0: only first 4 valid */ char pcs_proc_sn[16]; /* C8: only first 10 valid */ vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */ u_int64_t pcs_machcheck_len; /* E0: length in bytes */ vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ vm_offset_t pcs_halt_pc; /* F0: halt PC */ u_int64_t pcs_halt_ps; /* F8: halt PS */ u_int64_t pcs_halt_r25; /* 100: halt argument list */ u_int64_t pcs_halt_r26; /* 108: halt return addr list */ u_int64_t pcs_halt_r27; /* 110: halt procedure value */ #define PCS_HALT_RESERVED 0 #define PCS_HALT_POWERUP 1 #define PCS_HALT_CONSOLE_HALT 2 #define PCS_HALT_CONSOLE_CRASH 3 #define PCS_HALT_KERNEL_MODE 4 #define PCS_HALT_KERNEL_STACK_INVALID 5 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 #define PCS_HALT_SCBB 7 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ u_int64_t pcs_halt_reason; /* 118: */ u_int64_t pcs_reserved_soft; /* 120: preserved software */ u_int64_t pcs_buffer[21]; /* 128: console buffers */ #define PALvar_reserved 0 #define PALvar_OpenVMS 1 #define PALvar_OSF1 2 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ }; /* * CTB: Console Terminal Block */ struct ctb { u_int64_t ctb_type; /* 0: always 4 */ u_int64_t ctb_unit; /* 8: */ u_int64_t ctb_reserved; /* 16: */ u_int64_t ctb_len; /* 24: bytes of info */ u_int64_t ctb_ipl; /* 32: console ipl level */ vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */ #define CTB_GRAPHICS 3 /* graphics device */ #define CTB_NETWORK 0xC0 /* network device */ #define CTB_PRINTERPORT 2 /* printer port on the SCC */ u_int64_t ctb_term_type; /* 56: terminal type */ u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */ vm_offset_t ctb_keybd_map; /* 80: map table addr */ u_int64_t ctb_keybd_state; /* 88: keyboard flags */ u_int64_t ctb_keybd_last; /* 96: last key entered */ vm_offset_t ctb_font_us; /* 104: US font table addr */ vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */ u_int64_t ctb_font_width; /* 120: font width, height */ u_int64_t ctb_font_height; /* 128: in pixels */ u_int64_t ctb_mon_width; /* 136: monitor width, height */ u_int64_t ctb_mon_height; /* 144: in pixels */ u_int64_t ctb_dpi; /* 152: monitor dots per inch */ u_int64_t ctb_planes; /* 160: # of planes */ u_int64_t ctb_cur_width; /* 168: cursor width, height */ u_int64_t ctb_cur_height; /* 176: in pixels */ u_int64_t ctb_head_cnt; /* 184: # of heads */ u_int64_t ctb_opwindow; /* 192: opwindow on screen */ vm_offset_t ctb_head_offset; /* 200: offset to head info */ vm_offset_t ctb_putchar; /* 208: output char to TURBO */ u_int64_t ctb_io_state; /* 216: I/O flags */ u_int64_t ctb_listen_state; /* 224: listener flags */ vm_offset_t ctb_xaddr; /* 232: extended info addr */ u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ u_int64_t ctb_server_off; /* 256: offset to server info */ u_int64_t ctb_line_off; /* 264: line parameter offset */ u_int8_t ctb_csd; /* 272: console specific data */ }; /* * CRD: Console Routine Descriptor */ struct crd { int64_t descriptor; u_int64_t entry_va; }; /* * CRB: Console Routine Block */ struct crb { struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */ struct crd *crb_v_fixup; /* 10: virtual fixup addr */ vm_offset_t crb_p_fixup; /* 18: phys fixup addr */ u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ u_int64_t crb_page_cnt; /* 28: pages to be mapped */ }; /* * MDDT: Memory Data Descriptor Table */ struct mddt { int64_t mddt_cksum; /* 0: 7-N checksum */ vm_offset_t mddt_physaddr; /* 8: bank config addr * IMPLEMENTATION SPECIFIC */ u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ struct mddt_cluster { vm_offset_t mddt_pfn; /* 0: starting PFN */ u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ u_int64_t mddt_pg_test; /* 10: tested page count */ vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */ vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */ int64_t mddt_bit_cksum; /* 28: bitmap checksum */ #define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */ #define MDDT_PALCODE 0x01 /* console and PAL only */ #define MDDT_SYSTEM 0x00 /* system software only */ #define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */ int64_t mddt_usage; /* 30: bitmap permissions */ } mddt_clusters[1]; /* variable length array */ }; /* * DSR: Dynamic System Recognition. We're interested in the sysname * offset. The data pointed to by sysname is: * * [8 bytes: length of system name][N bytes: system name string] * * The system name string is NUL-terminated. */ struct dsrdb { int64_t dsr_smm; /* 0: SMM number */ u_int64_t dsr_lurt_off; /* 8: LURT table offset */ u_int64_t dsr_sysname_off; /* 16: offset to sysname */ }; /* * The DSR appeared in version 5 of the HWRPB. */ #define HWRPB_DSRDB_MINVERS 5 #ifdef _KERNEL int cputype; #endif #endif /* ASSEMBLER */ Index: head/sys/alpha/isa/isa.c =================================================================== --- head/sys/alpha/isa/isa.c (revision 38214) +++ head/sys/alpha/isa/isa.c (revision 38215) @@ -1,324 +1,330 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: isa.c,v 1.1 1998/07/22 08:29:26 dfr Exp $ + * $Id: isa.c,v 1.2 1998/07/27 09:38:26 dfr Exp $ */ #include #include #include #include #include #include #include #include #include /* * The structure used to attach devices to the Isa. */ struct isa_device { int id_port; int id_portsize; int id_flags; int id_irq; }; #define DEVTOISA(dev) ((struct isa_device*) device_get_ivars(dev)) static devclass_t isa_devclass; /* * Device methods */ static int isa_probe(device_t dev); static int isa_attach(device_t dev); static void isa_print_child(device_t dev, device_t child); static int isa_read_ivar(device_t dev, device_t child, int which, u_long *result); static int isa_write_ivar(device_t dev, device_t child, int which, u_long result); static void *isa_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); static int isa_connect_intr(device_t dev, void *ih); static device_method_t isa_methods[] = { /* Device interface */ DEVMETHOD(device_probe, isa_probe), DEVMETHOD(device_attach, isa_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), /* Bus interface */ DEVMETHOD(bus_print_child, isa_print_child), DEVMETHOD(bus_read_ivar, isa_read_ivar), DEVMETHOD(bus_write_ivar, isa_write_ivar), DEVMETHOD(bus_create_intr, isa_create_intr), DEVMETHOD(bus_connect_intr, isa_connect_intr), { 0, 0 } }; static driver_t isa_driver = { "isa", isa_methods, DRIVER_TYPE_MISC, 1, /* no softc */ }; static void isa_add_device(device_t dev, const char *name, int unit) { struct isa_device *idev; device_t child; int t; idev = malloc(sizeof(struct isa_device), M_DEVBUF, M_NOWAIT); if (!idev) return; if (resource_int_value(name, unit, "port", &t) == 0) idev->id_port = t; else idev->id_port = 0; if (resource_int_value(name, unit, "portsize", &t) == 0) idev->id_portsize = t; else idev->id_portsize = 0; if (resource_int_value(name, unit, "flags", &t) == 0) idev->id_flags = t; else idev->id_flags = 0; if (resource_int_value(name, unit, "irq", &t) == 0) idev->id_irq = t; else idev->id_irq = -1; child = device_add_child(dev, name, unit, idev); if (!child) return; if (resource_int_value(name, unit, "disabled", &t) == 0 && t != 0) device_disable(child); } static void isa_intr_enable(int irq) { int s = splhigh(); if (irq < 8) outb(IO_ICU1+1, inb(IO_ICU1+1) & ~(1 << irq)); else outb(IO_ICU2+1, inb(IO_ICU2+1) & ~(1 << irq)); splx(s); } static void isa_intr_disable(int irq) { int s = splhigh(); if (irq < 8) outb(IO_ICU1+1, inb(IO_ICU1+1) | (1 << irq)); else outb(IO_ICU2+1, inb(IO_ICU2+1) | (1 << irq)); splx(s); } int isa_irq_pending(void) { u_char irr1; u_char irr2; irr1 = inb(IO_ICU1); irr2 = inb(IO_ICU2); return ((irr2 << 8) | irr1); } int isa_irq_mask(void) { u_char irr1; u_char irr2; irr1 = inb(IO_ICU1+1); irr2 = inb(IO_ICU2+1); return ((irr2 << 8) | irr1); } /* * At 'probe' time, we add all the devices which we know about to the * bus. The generic attach routine will probe and attach them if they * are alive. */ static int isa_probe(device_t dev) { int i; /* * Add all devices configured to be attached to isa0. */ for (i = resource_query_string(-1, "at", "isa0"); i != -1; i = resource_query_string(i, "at", "isa0")) { isa_add_device(dev, resource_query_name(i), resource_query_unit(i)); } return 0; } extern device_t isa_bus_device; static int isa_attach(device_t dev) { /* make sure chaining irq is enabled */ isa_intr_enable(2); /* * Arrange for bus_generic_attach(dev) to be called later. */ isa_bus_device = dev; return 0; } static void isa_print_child(device_t bus, device_t dev) { struct isa_device* idev = DEVTOISA(dev); printf(" at"); if (idev->id_port) printf(" 0x%x", idev->id_port); if (idev->id_portsize > 0) printf("-0x%x", idev->id_port + idev->id_portsize - 1); if (idev->id_irq >= 0) printf(" irq %d", idev->id_irq); printf(" on %s%d", device_get_name(bus), device_get_unit(bus)); } static int isa_read_ivar(device_t bus, device_t dev, int index, u_long* result) { struct isa_device* idev = DEVTOISA(dev); switch (index) { case ISA_IVAR_PORT: *result = idev->id_port; break; case ISA_IVAR_PORTSIZE: *result = idev->id_portsize; break; case ISA_IVAR_FLAGS: *result = idev->id_flags; break; case ISA_IVAR_IRQ: *result = idev->id_irq; break; } return ENOENT; } static int isa_write_ivar(device_t bus, device_t dev, int index, u_long value) { struct isa_device* idev = DEVTOISA(dev); switch (index) { case ISA_IVAR_PORT: idev->id_port = value; break; case ISA_IVAR_PORTSIZE: idev->id_portsize = value; break; case ISA_IVAR_FLAGS: idev->id_flags = value; break; case ISA_IVAR_IRQ: idev->id_irq = value; break; } return ENOENT; } struct isa_intr { void *ih; driver_intr_t *intr; void *arg; int irq; }; +/* + * Wrap ISA interrupt routines so that we can feed non-specific + * EOI to the PICs. + */ + static void isa_handle_intr(void *arg) { struct isa_intr *ii = arg; int irq = ii->irq; ii->intr(ii->arg); if (ii->irq > 7) outb(IO_ICU2, 0x20 | (irq & 7)); outb(IO_ICU1, 0x20 | (irq > 7 ? 2 : irq)); } static void * isa_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg) { struct isa_intr *ii; if (irq == 2) irq = 9; ii = malloc(sizeof(struct isa_intr), M_DEVBUF, M_NOWAIT); if (!ii) return NULL; ii->intr = intr; ii->arg = arg; ii->irq = irq; - ii->ih = BUS_CREATE_INTR(device_get_parent(dev), dev, - 0x800 + (irq << 4), - isa_handle_intr, ii); + ii->ih = alpha_create_intr(0x800 + (irq << 4), isa_handle_intr, ii); + if (!ii->ih) { free(ii, M_DEVBUF); return NULL; } return ii; } static int isa_connect_intr(device_t dev, void *ih) { struct isa_intr *ii = ih; struct alpha_intr *i = ii->ih; isa_intr_enable(ii->irq); - return BUS_CONNECT_INTR(device_get_parent(dev), ii->ih); + return alpha_connect_intr(i); } DRIVER_MODULE(isa, cia, isa_driver, isa_devclass, 0, 0); +DRIVER_MODULE(isa, apecs, isa_driver, isa_devclass, 0, 0); +DRIVER_MODULE(isa, lca, isa_driver, isa_devclass, 0, 0); Index: head/sys/alpha/pci/apecs.c =================================================================== --- head/sys/alpha/pci/apecs.c (nonexistent) +++ head/sys/alpha/pci/apecs.c (revision 38215) @@ -0,0 +1,488 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: cia.c,v 1.3 1998/07/22 08:32:17 dfr Exp $ + */ +/* + * Copyright (c) 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t apecs_devclass; +static device_t apecs0; /* XXX only one for now */ +static device_t isa0; + +struct apecs_softc { + vm_offset_t dmem_base; /* dense memory */ + vm_offset_t smem_base; /* sparse memory */ + vm_offset_t io_base; /* dense i/o */ + vm_offset_t cfg0_base; /* dense pci0 config */ + vm_offset_t cfg1_base; /* dense pci1 config */ +}; + +#define APECS_SOFTC(dev) (struct apecs_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t apecs_swiz_inb; +static alpha_chipset_inw_t apecs_swiz_inw; +static alpha_chipset_inl_t apecs_swiz_inl; +static alpha_chipset_outb_t apecs_swiz_outb; +static alpha_chipset_outw_t apecs_swiz_outw; +static alpha_chipset_outl_t apecs_swiz_outl; +static alpha_chipset_readb_t apecs_swiz_readb; +static alpha_chipset_readw_t apecs_swiz_readw; +static alpha_chipset_readl_t apecs_swiz_readl; +static alpha_chipset_writeb_t apecs_swiz_writeb; +static alpha_chipset_writew_t apecs_swiz_writew; +static alpha_chipset_writel_t apecs_swiz_writel; +static alpha_chipset_maxdevs_t apecs_swiz_maxdevs; +static alpha_chipset_cfgreadb_t apecs_swiz_cfgreadb; +static alpha_chipset_cfgreadw_t apecs_swiz_cfgreadw; +static alpha_chipset_cfgreadl_t apecs_swiz_cfgreadl; +static alpha_chipset_cfgwriteb_t apecs_swiz_cfgwriteb; +static alpha_chipset_cfgwritew_t apecs_swiz_cfgwritew; +static alpha_chipset_cfgwritel_t apecs_swiz_cfgwritel; + +static alpha_chipset_t apecs_swiz_chipset = { + apecs_swiz_inb, + apecs_swiz_inw, + apecs_swiz_inl, + apecs_swiz_outb, + apecs_swiz_outw, + apecs_swiz_outl, + apecs_swiz_readb, + apecs_swiz_readw, + apecs_swiz_readl, + apecs_swiz_writeb, + apecs_swiz_writew, + apecs_swiz_writel, + apecs_swiz_maxdevs, + apecs_swiz_cfgreadb, + apecs_swiz_cfgreadw, + apecs_swiz_cfgreadl, + apecs_swiz_cfgwriteb, + apecs_swiz_cfgwritew, + apecs_swiz_cfgwritel, +}; + +static int +apecs_swiz_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + + + +static u_int8_t +apecs_swiz_inb(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_BYTE(KV(APECS_PCI_SIO), port); +} + +static u_int16_t +apecs_swiz_inw(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_WORD(KV(APECS_PCI_SIO), port); +} + +static u_int32_t +apecs_swiz_inl(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_LONG(KV(APECS_PCI_SIO), port); +} + +static void +apecs_swiz_outb(u_int32_t port, u_int8_t data) +{ + SPARSE_WRITE_BYTE(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +apecs_swiz_outw(u_int32_t port, u_int16_t data) +{ + SPARSE_WRITE_WORD(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +apecs_swiz_outl(u_int32_t port, u_int32_t data) +{ + SPARSE_WRITE_LONG(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +/* + * Memory functions. + * + * XXX linux does 32-bit reads/writes via dense space. This doesn't + * appear to work for devices behind a ppb. I'm using sparse + * accesses & they appear to work just fine everywhere. + */ + +static u_int32_t apecs_hae_mem; + +#define REG1 (1UL << 24) +static __inline void +apecs_swiz_set_hae_mem(u_int32_t *pa) +{ + int s; + u_int32_t msb; + if(*pa >= REG1){ + msb = *pa & 0xf8000000; + *pa -= msb; + s = splhigh(); + if (msb != apecs_hae_mem) { + apecs_hae_mem = msb; + REGVAL(EPIC_HAXR1) = apecs_hae_mem; + alpha_mb(); + apecs_hae_mem = REGVAL(EPIC_HAXR1); + } + splx(s); + } +} + +static u_int8_t +apecs_swiz_readb(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_BYTE(KV(APECS_PCI_SPARSE), pa); +} + +static u_int16_t +apecs_swiz_readw(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_WORD(KV(APECS_PCI_SPARSE), pa); +} + +static u_int32_t +apecs_swiz_readl(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_LONG(KV(APECS_PCI_SPARSE), pa); +} + +static void +apecs_swiz_writeb(u_int32_t pa, u_int8_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_BYTE(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +apecs_swiz_writew(u_int32_t pa, u_int16_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_WORD(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); +} + + +static void +apecs_swiz_writel(u_int32_t pa, u_int32_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_LONG(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); + +} + + +#define APECS_SWIZ_CFGOFF(b, s, f, r) \ + (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) { \ + do { \ + (s) = splhigh(); \ + (old_haxr2) = REGVAL(EPIC_HAXR2); \ + alpha_mb(); \ + REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1; \ + alpha_mb(); \ + } while(0); \ +} + +#define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) { \ + do { \ + alpha_mb(); \ + REGVAL(EPIC_HAXR2) = (old_haxr2); \ + alpha_mb(); \ + splx((s)); \ + } while(0); \ +} + +#define SWIZ_CFGREAD(b, s, f, r, width, type) \ + type val = ~0; \ + int ipl = 0; \ + u_int32_t old_haxr2 = 0; \ + struct apecs_softc* sc = APECS_SOFTC(apecs0); \ + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + alpha_mb(); \ + APECS_TYPE1_SETUP(b,ipl,old_haxr2); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ + } \ + APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \ + return val; + +#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \ + int ipl = 0; \ + u_int32_t old_haxr2 = 0; \ + struct apecs_softc* sc = APECS_SOFTC(apecs0); \ + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + alpha_mb(); \ + APECS_TYPE1_SETUP(b,ipl,old_haxr2); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ + alpha_wmb(); \ + } \ + APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \ + return; + +#if 1 +static u_int8_t +apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t); +} + +static u_int16_t +apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t); +} + +static u_int32_t +apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t); +} + +static void +apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); +} + +static void +apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t); +} + +static void +apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t); +} + +#else +static u_int8_t +apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return ~0; + return SPARSE_READ_BYTE(sc->cfg0_base, off); +} + +static u_int16_t +apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return ~0; + return SPARSE_READ_WORD(sc->cfg0_base, off); +} + +static u_int32_t +apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return ~0; + return SPARSE_READ_LONG(sc->cfg0_base, off); +} + +static void +apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return; + SPARSE_WRITE_BYTE(sc->cfg0_base, off, data); + alpha_wmb(); +} + +static void +apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return; + SPARSE_WRITE_WORD(sc->cfg0_base, off, data); + alpha_wmb(); +} + +static void +apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return; + SPARSE_WRITE_LONG(sc->cfg0_base, off, data); + alpha_wmb(); +} +#endif + +static int apecs_probe(device_t dev); +static int apecs_attach(device_t dev); +static void *apecs_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); +static int apecs_connect_intr(device_t dev, void* ih); + +static device_method_t apecs_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, apecs_probe), + DEVMETHOD(device_attach, apecs_attach), + + /* Bus interface */ + + { 0, 0 } +}; + +static driver_t apecs_driver = { + "apecs", + apecs_methods, + DRIVER_TYPE_MISC, + sizeof(struct apecs_softc), +}; + +void +apecs_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + if (platform.pci_intr_init) + platform.pci_intr_init(); + + chipset = apecs_swiz_chipset; +} + +static int +apecs_probe(device_t dev) +{ + int memwidth; + if (apecs0) + return ENXIO; + apecs0 = dev; + memwidth = (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64; + if(memwidth == 64){ + device_set_desc(dev, "DECchip 21071 Core Logic chipset"); + } else { + device_set_desc(dev, "DECchip 21072 Core Logic chipset"); + } + apecs_hae_mem = REGVAL(EPIC_HAXR1); + + isa0 = device_add_child(dev, "isa", 0, 0); + + return 0; +} + +extern void isa_intr(void* frame, u_long vector); + +static int +apecs_attach(device_t dev) +{ + struct apecs_softc* sc = APECS_SOFTC(dev); + apecs_init(); + chipset.intrdev = isa0; + + sc->dmem_base = APECS_PCI_DENSE; + sc->smem_base = APECS_PCI_SPARSE; + sc->io_base = APECS_PCI_SIO; + sc->cfg0_base = KV(APECS_PCI_CONF); + sc->cfg1_base = NULL; + + set_iointr(alpha_dispatch_intr); + + bus_generic_attach(dev); + return 0; +} + +DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0); + Property changes on: head/sys/alpha/pci/apecs.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/pci/apecsreg.h =================================================================== --- head/sys/alpha/pci/apecsreg.h (nonexistent) +++ head/sys/alpha/pci/apecsreg.h (revision 38215) @@ -0,0 +1,343 @@ +/* $NetBSD: apecsreg.h,v 1.7 1997/06/06 23:54:24 thorpej Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * APECS Chipset registers and constants. + * + * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data + * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38. + */ + +#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) + +/* + * Base addresses + */ +#define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */ +#define EPIC_BASE 0x1a0000000L /* 21071-DA Regs */ +#define APECS_PCI_IACK 0x1b0000000L /* PCI Int. Ack. */ +#define APECS_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ +#define APECS_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ +#define APECS_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ +#define APECS_PCI_DENSE 0x300000000L /* PCI Dense Space */ + + +/* + * 21071-CA Registers + */ + +/* + * 21071-CA General Registers + */ +#define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */ +#define COMANCHE_GCR_RSVD 0xc009 +#define COMANCHE_GCR_SYSARB 0x0006 +#define COMANCHE_GCR_WIDEMEM 0x0010 +#define COMANCHE_GCR_BC_EN 0x0020 +#define COMANCHE_GCR_BC_NOALLOC 0x0040 +#define COMANCHE_GCR_BC_LONGWR 0x0080 +#define COMANCHE_GCR_BC_IGNTAG 0x0100 +#define COMANCHE_GCR_BC_FRCTAG 0x0200 +#define COMANCHE_GCR_BC_FRCD 0x0400 +#define COMANCHE_GCR_BC_FRCV 0x0800 +#define COMANCHE_GCR_BC_FRCP 0x1000 +#define COMANCHE_GCR_BC_BADAP 0x2000 + +#define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */ + +#define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */ +#define COMANCHE_ED_LOSTERR 0x0001 +#define COMANCHE_ED_BC_TAPERR 0x0002 +#define COMANCHE_ED_BC_TCPERR 0x0004 +#define COMANCHE_ED_NXMERR 0x0008 +#define COMANCHE_ED_DMACAUSE 0x0010 +#define COMANCHE_ED_VICCAUSE 0x0020 +#define COMANCHE_ED_CREQCAUSE 0x01c0 +#define COMANCHE_ED_RSVD 0x1e00 +#define COMANCHE_ED_PASS2 0x2000 +#define COMANCHE_ED_IDXLLOCK 0x4000 +#define COMANCHE_ED_WRPEND 0x8000 + +#define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */ +#define COMANCHE_TAGENB_RSVD 0x0001 + +#define COMANCHE_TAGENB_C_4G 0x0000 +#define COMANCHE_TAGENB_C_2G 0x8000 +#define COMANCHE_TAGENB_C_1G 0xc000 +#define COMANCHE_TAGENB_C_512M 0xe000 +#define COMANCHE_TAGENB_C_256M 0xf000 +#define COMANCHE_TAGENB_C_128M 0xf800 +#define COMANCHE_TAGENB_C_64M 0xfc00 +#define COMANCHE_TAGENB_C_32M 0xfe00 +#define COMANCHE_TAGENB_C_16M 0xff00 +#define COMANCHE_TAGENB_C_8M 0xff80 +#define COMANCHE_TAGENB_C_4M 0xffc0 +#define COMANCHE_TAGENB_C_2M 0xffe0 +#define COMANCHE_TAGENB_C_1M 0xfff0 +#define COMANCHE_TAGENB_C_512K 0xfff8 +#define COMANCHE_TAGENB_C_256K 0xfffc +#define COMANCHE_TAGENB_C_128K 0xfffe + +#define COMANCHE_TAGENB_M_4G 0xffff +#define COMANCHE_TAGENB_M_2G 0x7fff +#define COMANCHE_TAGENB_M_1G 0x3fff +#define COMANCHE_TAGENB_M_512M 0x1fff +#define COMANCHE_TAGENB_M_256M 0x0fff +#define COMANCHE_TAGENB_M_128M 0x07ff +#define COMANCHE_TAGENB_M_64M 0x03ff +#define COMANCHE_TAGENB_M_32M 0x01ff +#define COMANCHE_TAGENB_M_16M 0x00ff +#define COMANCHE_TAGENB_M_8M 0x007f +#define COMANCHE_TAGENB_M_4M 0x003f +#define COMANCHE_TAGENB_M_2M 0x001f +#define COMANCHE_TAGENB_M_1M 0x000e +#define COMANCHE_TAGENB_M_512K 0x0006 +#define COMANCHE_TAGENB_M_256K 0x0002 +#define COMANCHE_TAGENB_M_128K 0x0000 + +#define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */ + +#define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */ +#define COMANCHE_ERR_HI_RSVD 0xe000 + +#define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */ + +#define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */ +#define COMANCHE_LOCK_HI_RSVD 0xe000 + +/* + * 21071-CA Memory Registers + */ +#define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */ +#define COMANCHE_LOCK_HI_RSVD 0xe000 + +#define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */ + +#define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */ +#define COMANCHE_VFP_COL 0x001f +#define COMANCHE_VFP_ROW 0x3fe0 +#define COMANCHE_VFP_SUBBANK 0x4000 +#define COMANCHE_VFP_RSVD 0x8000 + +#define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */ + +#define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */ + +/* + * 21071-CA Memory banks' Base Address Register format + */ +#define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */ +#define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */ +#define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */ +#define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */ +#define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */ +#define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */ +#define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */ +#define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */ +#define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */ +#define COMANCHE_BAR_RSVD 0x001f + +/* + * 21071-CA Memory banks' Configuration Register format + */ +#define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */ +#define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */ +#define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */ +#define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */ +#define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */ +#define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */ +#define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */ +#define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */ +#define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */ +#define COMANCHE_CR_VALID 0x0001 +#define COMANCHE_CR_SIZE 0x001e +#define COMANCHE_CR_SUBENA 0x0020 +#define COMANCHE_CR_COLSEL 0x01c0 +#define COMANCHE_CR_S0_RSVD 0xfe00 +#define COMANCHE_CR_S8_CHECK 0x0200 +#define COMANCHE_CR_S8_RSVD 0xfc00 + +/* + * 21071-CA Memory banks' Timing Register A format + */ +#define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */ +#define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */ +#define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */ +#define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */ +#define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */ +#define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */ +#define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */ +#define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */ +#define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */ +#define COMANCHE_TRA_ROWSETUP 0x0003 +#define COMANCHE_TRA_ROWHOLD 0x000c +#define COMANCHE_TRA_COLSETUP 0x0070 +#define COMANCHE_TRA_COLHOLD 0x0180 +#define COMANCHE_TRA_RDLYROW 0x0e00 +#define COMANCHE_TRA_RDLYCOL 0x7000 +#define COMANCHE_TRA_RSVD 0x8000 + +/* + * 21071-CA Memory banks' Timing Register B format + */ +#define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */ +#define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */ +#define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */ +#define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */ +#define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */ +#define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */ +#define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */ +#define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */ +#define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */ +#define COMANCHE_TRB_RTCAS 0x0007 +#define COMANCHE_TRB_WTCAS 0x0038 +#define COMANCHE_TRB_TCP 0x00c0 +#define COMANCHE_TRB_WHOLD0ROW 0x0700 +#define COMANCHE_TRB_WHOLD0COL 0x3800 +#define COMANCHE_TRB_RSVD 0xc000 + + +/* + * 21071-DA Registers + */ +#define EPIC_DCSR (EPIC_BASE + 0x0000) /* Diagnostic CSR */ +#define EPIC_DCSR_TENB 0x00000001 +#define EPIC_DCSR_RSVD 0x7fc00082 +#define EPIC_DCSR_PENB 0x00000004 +#define EPIC_DCSR_DCEI 0x00000008 +#define EPIC_DCSR_DPEC 0x00000010 +#define EPIC_DCSR_IORT 0x00000020 +#define EPIC_DCSR_LOST 0x00000040 +#define EPIC_DCSR_DDPE 0x00000100 +#define EPIC_DCSR_IOPE 0x00000200 +#define EPIC_DCSR_TABT 0x00000400 +#define EPIC_DCSR_NDEV 0x00000800 +#define EPIC_DCSR_CMRD 0x00001000 +#define EPIC_DCSR_UMRD 0x00002000 +#define EPIC_DCSR_IPTL 0x00004000 +#define EPIC_DCSR_MERR 0x00008000 +#define EPIC_DCSR_DBYP 0x00030000 +#define EPIC_DCSR_PCMD 0x003c0000 +#define EPIC_DCSR_PASS2 0x80000000 + +#define EPIC_PEAR (EPIC_BASE + 0x0020) /* PCI Err Addr. */ + +#define EPIC_SEAR (EPIC_BASE + 0x0040) /* sysBus Err Addr. */ +#define EPIC_SEAR_RSVD 0x0000000f +#define EPIC_SEAR_SYS_ERR 0xfffffff0 + +#define EPIC_DUMMY_1 (EPIC_BASE + 0x0060) /* Dummy 1 */ +#define EPIC_DUMMY_2 (EPIC_BASE + 0x0080) /* Dummy 2 */ +#define EPIC_DUMMY_3 (EPIC_BASE + 0x00a0) /* Dummy 3 */ + +#define EPIC_TBASE_1 (EPIC_BASE + 0x00c0) /* Trans. Base 1 */ +#define EPIC_TBASE_2 (EPIC_BASE + 0x00e0) /* Trans. Base 2 */ +#define EPIC_TBASE_RSVD 0x000001ff +#define EPIC_TBASE_T_BASE 0xfffffe00 +#define EPIC_TBASE_SHIFT 1 + +#define EPIC_PCI_BASE_1 (EPIC_BASE + 0x0100) /* PCI Base 1 */ +#define EPIC_PCI_BASE_2 (EPIC_BASE + 0x0120) /* PCI Base 2 */ +#define EPIC_PCI_BASE_RSVD 0x0003ffff +#define EPIC_PCI_BASE_SGEN 0x00040000 +#define EPIC_PCI_BASE_WENB 0x00080000 +#define EPIC_PCI_BASE_PCI_BASE 0xfff00000 + +#define EPIC_PCI_MASK_1 (EPIC_BASE + 0x0140) /* PCI Mask 1 */ +#define EPIC_PCI_MASK_2 (EPIC_BASE + 0x0160) /* PCI Mask 2 */ +#define EPIC_PCI_MASK_RSVD 0x000fffff +#define EPIC_PCI_MASK_PCI_MASK 0xfff00000 +#define EPIC_PCI_MASK_1M 0x00000000 +#define EPIC_PCI_MASK_2M 0x00100000 +#define EPIC_PCI_MASK_4M 0x00300000 +#define EPIC_PCI_MASK_8M 0x00700000 +#define EPIC_PCI_MASK_16M 0x00f00000 +#define EPIC_PCI_MASK_32M 0x01f00000 +#define EPIC_PCI_MASK_64M 0x03f00000 +#define EPIC_PCI_MASK_128M 0x07f00000 +#define EPIC_PCI_MASK_256M 0x0ff00000 +#define EPIC_PCI_MASK_512M 0x1ff00000 +#define EPIC_PCI_MASK_1G 0x3ff00000 +#define EPIC_PCI_MASK_2G 0x7ff00000 +#define EPIC_PCI_MASK_4G 0xfff00000 + +#define EPIC_HAXR0 (EPIC_BASE + 0x0180) /* Host Addr Extn 0 */ + +#define EPIC_HAXR1 (EPIC_BASE + 0x01a0) /* Host Addr Extn 1 */ +#define EPIC_HAXR1_RSVD 0x07ffffff +#define EPIC_HAXR1_EADDR 0xf8000000 + +#define EPIC_HAXR2 (EPIC_BASE + 0x01c0) /* Host Addr Extn 2 */ +#define EPIC_HAXR2_CONF_TYPE 0x00000003 +#define EPIC_HAXR2_CONF_TYPO0 0x00000000 +#define EPIC_HAXR2_CONF_TYPE1 0x00000001 +#define EPIC_HAXR2_RSVD 0x00fffffc +#define EPIC_HAXR2_EADDR 0xff000000 + +#define EPIC_PMLT (EPIC_BASE + 0x01e0) /* PCI Mstr Lat Tmr */ +#define EPIC_PMLT_PMLC 0x000000ff +#define EPIC_PMLT_RSVD 0xffffff00 + +#define EPIC_TLB_TAG_0 (EPIC_BASE + 0x0200) /* TLB Tag 0 */ +#define EPIC_TLB_TAG_1 (EPIC_BASE + 0x0220) /* TLB Tag 1 */ +#define EPIC_TLB_TAG_2 (EPIC_BASE + 0x0240) /* TLB Tag 2 */ +#define EPIC_TLB_TAG_3 (EPIC_BASE + 0x0260) /* TLB Tag 3 */ +#define EPIC_TLB_TAG_4 (EPIC_BASE + 0x0280) /* TLB Tag 4 */ +#define EPIC_TLB_TAG_5 (EPIC_BASE + 0x02a0) /* TLB Tag 5 */ +#define EPIC_TLB_TAG_6 (EPIC_BASE + 0x02c0) /* TLB Tag 6 */ +#define EPIC_TLB_TAG_7 (EPIC_BASE + 0x02e0) /* TLB Tag 7 */ +#define EPIC_TLB_TAG_RSVD 0x00000fff +#define EPIC_TLB_TAG_EVAL 0x00001000 +#define EPIC_TLB_TAG_PCI_PAGE 0xffffe000 + +#define EPIC_TLB_DATA_0 (EPIC_BASE + 0x0300) /* TLB Data 0 */ +#define EPIC_TLB_DATA_1 (EPIC_BASE + 0x0320) /* TLB Data 1 */ +#define EPIC_TLB_DATA_2 (EPIC_BASE + 0x0340) /* TLB Data 2 */ +#define EPIC_TLB_DATA_3 (EPIC_BASE + 0x0360) /* TLB Data 3 */ +#define EPIC_TLB_DATA_4 (EPIC_BASE + 0x0380) /* TLB Data 4 */ +#define EPIC_TLB_DATA_5 (EPIC_BASE + 0x03a0) /* TLB Data 5 */ +#define EPIC_TLB_DATA_6 (EPIC_BASE + 0x03c0) /* TLB Data 6 */ +#define EPIC_TLB_DATA_7 (EPIC_BASE + 0x03e0) /* TLB Data 7 */ +#define EPIC_TLB_DATA_RSVD 0xffe00001 +#define EPIC_TLB_DATA_CPU_PAGE 0x001ffffe + +#define EPIC_TBIA (EPIC_BASE + 0x0400) /* TLB Invl All */ + +/* + * EPIC Scatter-Gather Map Entries + */ + +struct sgmapent { + u_int64_t val; +}; +#define SGMAPENT_EVAL 0x0000000000000001L +#define SGMAPENT_PFN 0x00000000001ffffeL +#define SGMAPENT_RSVD 0xffffffffffe00000L + +#define SGMAP_MAKEENTRY(pfn) (SGMAPENT_EVAL | ((pfn) << 1)) Property changes on: head/sys/alpha/pci/apecsreg.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/pci/apecsvar.h =================================================================== --- head/sys/alpha/pci/apecsvar.h (nonexistent) +++ head/sys/alpha/pci/apecsvar.h (revision 38215) @@ -0,0 +1,30 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: ciavar.h,v 1.1 1998/07/05 12:16:15 dfr Exp $ + */ + +extern void apecs_init(void); + Property changes on: head/sys/alpha/pci/apecsvar.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/pci/cia.c =================================================================== --- head/sys/alpha/pci/cia.c (revision 38214) +++ head/sys/alpha/pci/cia.c (revision 38215) @@ -1,592 +1,567 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: cia.c,v 1.4 1998/07/31 09:17:51 dfr Exp $ + * $Id: cia.c,v 1.5 1998/08/07 08:18:44 dfr Exp $ */ #include #include #include #include #include #include #include #include #include #include #include #define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) static devclass_t cia_devclass; static device_t cia0; /* XXX only one for now */ static u_int32_t cia_hae_mem; -extern void eb164_intr_enable(int irq); -extern void eb164_intr_disable(int irq); -static void cia_intr(void* frame, u_long vector); - struct cia_softc { - vm_offset_t dmem_base; /* dense memory */ - vm_offset_t smem_base; /* sparse memory */ - vm_offset_t io_base; /* dense i/o */ - vm_offset_t cfg0_base; /* dense pci0 config */ - vm_offset_t cfg1_base; /* dense pci1 config */ + int junk; /* no softc */ }; #define CIA_SOFTC(dev) (struct cia_softc*) device_get_softc(dev) static alpha_chipset_inb_t cia_bwx_inb, cia_swiz_inb; static alpha_chipset_inw_t cia_bwx_inw, cia_swiz_inw; static alpha_chipset_inl_t cia_bwx_inl, cia_swiz_inl; static alpha_chipset_outb_t cia_bwx_outb, cia_swiz_outb; static alpha_chipset_outw_t cia_bwx_outw, cia_swiz_outw; static alpha_chipset_outl_t cia_bwx_outl, cia_swiz_outl; static alpha_chipset_readb_t cia_bwx_readb, cia_swiz_readb; static alpha_chipset_readw_t cia_bwx_readw, cia_swiz_readw; static alpha_chipset_readl_t cia_bwx_readl, cia_swiz_readl; static alpha_chipset_writeb_t cia_bwx_writeb, cia_swiz_writeb; static alpha_chipset_writew_t cia_bwx_writew, cia_swiz_writew; static alpha_chipset_writel_t cia_bwx_writel, cia_swiz_writel; static alpha_chipset_maxdevs_t cia_bwx_maxdevs, cia_swiz_maxdevs; static alpha_chipset_cfgreadb_t cia_bwx_cfgreadb, cia_swiz_cfgreadb; static alpha_chipset_cfgreadw_t cia_bwx_cfgreadw, cia_swiz_cfgreadw; static alpha_chipset_cfgreadl_t cia_bwx_cfgreadl, cia_swiz_cfgreadl; static alpha_chipset_cfgwriteb_t cia_bwx_cfgwriteb, cia_swiz_cfgwriteb; static alpha_chipset_cfgwritew_t cia_bwx_cfgwritew, cia_swiz_cfgwritew; static alpha_chipset_cfgwritel_t cia_bwx_cfgwritel, cia_swiz_cfgwritel; static alpha_chipset_t cia_bwx_chipset = { cia_bwx_inb, cia_bwx_inw, cia_bwx_inl, cia_bwx_outb, cia_bwx_outw, cia_bwx_outl, cia_bwx_readb, cia_bwx_readw, cia_bwx_readl, cia_bwx_writeb, cia_bwx_writew, cia_bwx_writel, cia_bwx_maxdevs, cia_bwx_cfgreadb, cia_bwx_cfgreadw, cia_bwx_cfgreadl, cia_bwx_cfgwriteb, cia_bwx_cfgwritew, cia_bwx_cfgwritel, }; static alpha_chipset_t cia_swiz_chipset = { cia_swiz_inb, cia_swiz_inw, cia_swiz_inl, cia_swiz_outb, cia_swiz_outw, cia_swiz_outl, cia_swiz_readb, cia_swiz_readw, cia_swiz_readl, cia_swiz_writeb, cia_swiz_writew, cia_swiz_writel, cia_swiz_maxdevs, cia_swiz_cfgreadb, cia_swiz_cfgreadw, cia_swiz_cfgreadl, cia_swiz_cfgwriteb, cia_swiz_cfgwritew, cia_swiz_cfgwritel, }; static u_int8_t cia_bwx_inb(u_int32_t port) { alpha_mb(); return ldbu(KV(CIA_EV56_BWIO+BWX_EV56_INT1 + port)); } static u_int16_t cia_bwx_inw(u_int32_t port) { alpha_mb(); return ldwu(KV(CIA_EV56_BWIO+BWX_EV56_INT2 + port)); } static u_int32_t cia_bwx_inl(u_int32_t port) { alpha_mb(); return ldl(KV(CIA_EV56_BWIO+BWX_EV56_INT4 + port)); } static void cia_bwx_outb(u_int32_t port, u_int8_t data) { stb(KV(CIA_EV56_BWIO+BWX_EV56_INT1 + port), data); alpha_wmb(); } static void cia_bwx_outw(u_int32_t port, u_int16_t data) { stw(KV(CIA_EV56_BWIO+BWX_EV56_INT2 + port), data); alpha_wmb(); } static void cia_bwx_outl(u_int32_t port, u_int32_t data) { stl(KV(CIA_EV56_BWIO+BWX_EV56_INT4 + port), data); alpha_wmb(); } static u_int8_t cia_bwx_readb(u_int32_t pa) { alpha_mb(); return ldbu(KV(CIA_EV56_BWMEM+BWX_EV56_INT1 + pa)); } static u_int16_t cia_bwx_readw(u_int32_t pa) { alpha_mb(); return ldwu(KV(CIA_EV56_BWMEM+BWX_EV56_INT2 + pa)); } static u_int32_t cia_bwx_readl(u_int32_t pa) { alpha_mb(); return ldl(KV(CIA_EV56_BWMEM+BWX_EV56_INT4 + pa)); } static void cia_bwx_writeb(u_int32_t pa, u_int8_t data) { stb(KV(CIA_EV56_BWMEM+BWX_EV56_INT1 + pa), data); alpha_wmb(); } static void cia_bwx_writew(u_int32_t pa, u_int16_t data) { stw(KV(CIA_EV56_BWMEM+BWX_EV56_INT2 + pa), data); alpha_wmb(); } static void cia_bwx_writel(u_int32_t pa, u_int32_t data) { stl(KV(CIA_EV56_BWMEM+BWX_EV56_INT4 + pa), data); alpha_wmb(); } static int cia_bwx_maxdevs(u_int b) { return 12; /* XXX */ } #define CIA_BWX_CFGADDR(b, s, f, r) \ KV(((b) ? CIA_EV56_BWCONF1 : CIA_EV56_BWCONF0) \ | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) static u_int8_t cia_bwx_cfgreadb(u_int b, u_int s, u_int f, u_int r) { vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r); alpha_mb(); if (badaddr((caddr_t)va, 1)) return ~0; return ldbu(va+BWX_EV56_INT1); } static u_int16_t cia_bwx_cfgreadw(u_int b, u_int s, u_int f, u_int r) { vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r); alpha_mb(); if (badaddr((caddr_t)va, 2)) return ~0; return ldwu(va+BWX_EV56_INT2); } static u_int32_t cia_bwx_cfgreadl(u_int b, u_int s, u_int f, u_int r) { vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r); alpha_mb(); if (badaddr((caddr_t)va, 4)) return ~0; return ldl(va+BWX_EV56_INT4); } static void cia_bwx_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) { vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r); if (badaddr((caddr_t)va, 1)) return; stb(va+BWX_EV56_INT1, data); alpha_wmb(); } static void cia_bwx_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) { vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r); if (badaddr((caddr_t)va, 2)) return; stw(va+BWX_EV56_INT2, data); alpha_wmb(); } static void cia_bwx_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) { vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r); if (badaddr((caddr_t)va, 4)) return; stl(va+BWX_EV56_INT4, data); alpha_wmb(); } static u_int8_t cia_swiz_inb(u_int32_t port) { alpha_mb(); return SPARSE_READ_BYTE(KV(CIA_PCI_SIO1), port); } static u_int16_t cia_swiz_inw(u_int32_t port) { alpha_mb(); return SPARSE_READ_WORD(KV(CIA_PCI_SIO1), port); } static u_int32_t cia_swiz_inl(u_int32_t port) { alpha_mb(); return SPARSE_READ_LONG(KV(CIA_PCI_SIO1), port); } static void cia_swiz_outb(u_int32_t port, u_int8_t data) { SPARSE_WRITE_BYTE(KV(CIA_PCI_SIO1), port, data); alpha_wmb(); } static void cia_swiz_outw(u_int32_t port, u_int16_t data) { SPARSE_WRITE_WORD(KV(CIA_PCI_SIO1), port, data); alpha_wmb(); } static void cia_swiz_outl(u_int32_t port, u_int32_t data) { SPARSE_WRITE_LONG(KV(CIA_PCI_SIO1), port, data); alpha_wmb(); } static __inline void cia_swiz_set_hae_mem(u_int32_t pa) { /* Only bother with region 1 */ #define REG1 (7 << 29) if ((cia_hae_mem & REG1) != (pa & REG1)) { /* * Seems fairly paranoid but this is what Linux does... */ int s = splhigh(); cia_hae_mem = (cia_hae_mem & ~REG1) | (pa & REG1); REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem; alpha_mb(); cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM); splx(s); } } static u_int8_t cia_swiz_readb(u_int32_t pa) { alpha_mb(); cia_swiz_set_hae_mem(pa); return SPARSE_READ_BYTE(KV(CIA_PCI_SMEM1), pa); } static u_int16_t cia_swiz_readw(u_int32_t pa) { alpha_mb(); cia_swiz_set_hae_mem(pa); return SPARSE_READ_WORD(KV(CIA_PCI_SMEM1), pa); } static u_int32_t cia_swiz_readl(u_int32_t pa) { alpha_mb(); cia_swiz_set_hae_mem(pa); return SPARSE_READ_LONG(KV(CIA_PCI_SMEM1), pa); } static void cia_swiz_writeb(u_int32_t pa, u_int8_t data) { cia_swiz_set_hae_mem(pa); SPARSE_WRITE_BYTE(KV(CIA_PCI_SMEM1), pa, data); alpha_wmb(); } static void cia_swiz_writew(u_int32_t pa, u_int16_t data) { cia_swiz_set_hae_mem(pa); SPARSE_WRITE_WORD(KV(CIA_PCI_SMEM1), pa, data); alpha_wmb(); } static void cia_swiz_writel(u_int32_t pa, u_int32_t data) { cia_swiz_set_hae_mem(pa); SPARSE_WRITE_LONG(KV(CIA_PCI_SMEM1), pa, data); alpha_wmb(); } static int cia_swiz_maxdevs(u_int b) { return 12; /* XXX */ } #define CIA_SWIZ_CFGOFF(b, s, f, r) \ (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) /* when doing a type 1 pci configuration space access, we * must set a bit in the CIA_CSR_CFG register & clear it * when we're done */ #define CIA_TYPE1_SETUP(b,s,old_cfg) if((b)) { \ do { \ (s) = splhigh(); \ (old_cfg) = REGVAL(CIA_CSR_CFG); \ alpha_mb(); \ REGVAL(CIA_CSR_CFG) = (old_cfg) | 0x1; \ alpha_mb(); \ } while(0); \ } #define CIA_TYPE1_TEARDOWN(b,s,old_cfg) if((b)) { \ do { \ alpha_mb(); \ REGVAL(CIA_CSR_CFG) = (old_cfg); \ alpha_mb(); \ splx((s)); \ } while(0); \ } #define SWIZ_CFGREAD(b, s, f, r, width, type) \ type val = ~0; \ int ipl = 0; \ u_int32_t old_cfg = 0; \ - struct cia_softc* sc = CIA_SOFTC(cia0); \ vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \ - vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(CIA_PCI_CONF, off); \ alpha_mb(); \ CIA_TYPE1_SETUP(b,ipl,old_cfg); \ if (!badaddr((caddr_t)kv, sizeof(type))) { \ val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ } \ CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \ return val; #define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \ int ipl = 0; \ u_int32_t old_cfg = 0; \ - struct cia_softc* sc = CIA_SOFTC(cia0); \ vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \ - vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(CIA_PCI_CONF, off); \ alpha_mb(); \ CIA_TYPE1_SETUP(b,ipl,old_cfg); \ if (!badaddr((caddr_t)kv, sizeof(type))) { \ SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ alpha_wmb(); \ } \ CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \ return; static u_int8_t cia_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) { SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t); } static u_int16_t cia_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) { SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t); } static u_int32_t cia_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) { SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t); } static void cia_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) { SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); } static void cia_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) { SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t); } static void cia_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) { SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t); } static int cia_probe(device_t dev); static int cia_attach(device_t dev); static void *cia_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); static int cia_connect_intr(device_t dev, void* ih); static device_method_t cia_methods[] = { /* Device interface */ DEVMETHOD(device_probe, cia_probe), DEVMETHOD(device_attach, cia_attach), /* Bus interface */ DEVMETHOD(bus_create_intr, cia_create_intr), DEVMETHOD(bus_connect_intr, cia_connect_intr), { 0, 0 } }; static driver_t cia_driver = { "cia", cia_methods, DRIVER_TYPE_MISC, sizeof(struct cia_softc), }; void cia_init() { static int initted = 0; if (initted) return; initted = 1; if (alpha_implver() != ALPHA_IMPLVER_EV5 || alpha_amask(ALPHA_AMASK_BWX)) chipset = cia_swiz_chipset; else chipset = cia_bwx_chipset; cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM); + +#if 0 + chipset = cia_swiz_chipset; /* XXX */ +#endif + + if (platform.pci_intr_init) + platform.pci_intr_init(); } static int cia_probe(device_t dev) { if (cia0) return ENXIO; cia0 = dev; device_set_desc(dev, "2117x PCI adapter"); /* XXX */ device_add_child(dev, "isa", 0, 0); return 0; } static int cia_attach(device_t dev) { struct cia_softc* sc = CIA_SOFTC(dev); cia_init(); - chipset.bridge = dev; + chipset.intrdev = dev; - if (alpha_amask(ALPHA_AMASK_BWX) == 0) { - sc->dmem_base = CIA_EV56_BWMEM; - sc->smem_base = CIA_PCI_SMEM1; - sc->io_base = CIA_EV56_BWIO; - sc->cfg0_base = CIA_EV56_BWCONF0; - sc->cfg1_base = CIA_EV56_BWCONF1; - } else { - sc->dmem_base = CIA_PCI_DENSE; - sc->smem_base = CIA_PCI_SMEM1; - sc->io_base = CIA_PCI_SIO1; - sc->cfg0_base = KV(CIA_PCI_CONF); - sc->cfg1_base = NULL; - } - set_iointr(cia_intr); + if (!platform.iointr) /* XXX */ + set_iointr(alpha_dispatch_intr); bus_generic_attach(dev); return 0; } static void * cia_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg) { - return alpha_create_intr(irq, intr, arg); + return alpha_create_intr(0x900 + (irq << 4), intr, arg); } static int cia_connect_intr(device_t dev, void* ih) { struct alpha_intr *i = ih; int s = splhigh(); int error = alpha_connect_intr(i); if (!error) { - if (i->vector > 0x900) - /* PCI interrupt */ - platform.pci_intr_enable((i->vector - 0x900) >> 4); - else if (i->vector > 0x800) - /* ISA interrupt chained to PCI interrupt 4 */ - platform.pci_intr_enable(4);/* XXX */ + /* Enable PCI interrupt */ + platform.pci_intr_enable((i->vector - 0x900) >> 4); } splx(s); return error; -} - -static void -cia_intr(void* frame, u_long vector) -{ - alpha_dispatch_intr(vector); } DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0); Index: head/sys/alpha/pci/lca.c =================================================================== --- head/sys/alpha/pci/lca.c (nonexistent) +++ head/sys/alpha/pci/lca.c (revision 38215) @@ -0,0 +1,371 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t lca_devclass; +static device_t lca0; /* XXX only one for now */ +static device_t isa0; + +struct lca_softc { + int junk; +}; + +#define LCA_SOFTC(dev) (struct lca_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t lca_inb; +static alpha_chipset_inw_t lca_inw; +static alpha_chipset_inl_t lca_inl; +static alpha_chipset_outb_t lca_outb; +static alpha_chipset_outw_t lca_outw; +static alpha_chipset_outl_t lca_outl; +static alpha_chipset_readb_t lca_readb; +static alpha_chipset_readw_t lca_readw; +static alpha_chipset_readl_t lca_readl; +static alpha_chipset_writeb_t lca_writeb; +static alpha_chipset_writew_t lca_writew; +static alpha_chipset_writel_t lca_writel; +static alpha_chipset_maxdevs_t lca_maxdevs; +static alpha_chipset_cfgreadb_t lca_cfgreadb; +static alpha_chipset_cfgreadw_t lca_cfgreadw; +static alpha_chipset_cfgreadl_t lca_cfgreadl; +static alpha_chipset_cfgwriteb_t lca_cfgwriteb; +static alpha_chipset_cfgwritew_t lca_cfgwritew; +static alpha_chipset_cfgwritel_t lca_cfgwritel; + +static alpha_chipset_t lca_chipset = { + lca_inb, + lca_inw, + lca_inl, + lca_outb, + lca_outw, + lca_outl, + lca_readb, + lca_readw, + lca_readl, + lca_writeb, + lca_writew, + lca_writel, + lca_maxdevs, + lca_cfgreadb, + lca_cfgreadw, + lca_cfgreadl, + lca_cfgwriteb, + lca_cfgwritew, + lca_cfgwritel, +}; + +static u_int8_t +lca_inb(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_BYTE(KV(LCA_PCI_SIO), port); +} + +static u_int16_t +lca_inw(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_WORD(KV(LCA_PCI_SIO), port); +} + +static u_int32_t +lca_inl(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_LONG(KV(LCA_PCI_SIO), port); +} + +static void +lca_outb(u_int32_t port, u_int8_t data) +{ + SPARSE_WRITE_BYTE(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +lca_outw(u_int32_t port, u_int16_t data) +{ + SPARSE_WRITE_WORD(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +lca_outl(u_int32_t port, u_int32_t data) +{ + SPARSE_WRITE_LONG(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +/* + * The LCA HAE is write-only. According to NetBSD, this is where it starts. + */ +static u_int32_t lca_hae_mem = 0x80000000; + +/* + * The first 16Mb ignores the HAE. The next 112Mb uses the HAE to set + * the high bits of the PCI address. + */ +#define REG1 (1UL << 24) + +static __inline void +lca_set_hae_mem(u_int32_t *pa) +{ + int s; + u_int32_t msb; + if(*pa >= REG1){ + msb = *pa & 0xf8000000; + *pa -= msb; + s = splhigh(); + if (msb != lca_hae_mem) { + lca_hae_mem = msb; + REGVAL(LCA_IOC_HAE) = lca_hae_mem; + alpha_mb(); + alpha_mb(); + } + splx(s); + } +} + +static u_int8_t +lca_readb(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_BYTE(KV(LCA_PCI_SPARSE), pa); +} + +static u_int16_t +lca_readw(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_WORD(KV(LCA_PCI_SPARSE), pa); +} + +static u_int32_t +lca_readl(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_LONG(KV(LCA_PCI_SPARSE), pa); +} + +static void +lca_writeb(u_int32_t pa, u_int8_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_BYTE(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +lca_writew(u_int32_t pa, u_int16_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_WORD(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +lca_writel(u_int32_t pa, u_int32_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_LONG(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static int +lca_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + +#define LCA_CFGOFF(b, s, f, r) \ + (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define LCA_TYPE1_SETUP(b,s) if ((b)) { \ + do { \ + (s) = splhigh(); \ + alpha_mb(); \ + REGVAL(LCA_IOC_CONF) = 1; \ + alpha_mb(); \ + } while(0); \ +} + +#define LCA_TYPE1_TEARDOWN(b,s) if ((b)) { \ + do { \ + alpha_mb(); \ + REGVAL(LCA_IOC_CONF) = 0; \ + alpha_mb(); \ + splx((s)); \ + } while(0); \ +} + +#define CFGREAD(b, s, f, r, width, type) \ + type val = ~0; \ + int ipl = 0; \ + vm_offset_t off = LCA_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(LCA_PCI_CONF, off); \ + alpha_mb(); \ + LCA_TYPE1_SETUP(b,ipl); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ + } \ + LCA_TYPE1_TEARDOWN(b,ipl); \ + return val + +#define CFGWRITE(b, s, f, r, data, width, type) \ + int ipl = 0; \ + vm_offset_t off = LCA_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(LCA_PCI_CONF, off); \ + alpha_mb(); \ + LCA_TYPE1_SETUP(b,ipl); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ + alpha_wmb(); \ + } \ + LCA_TYPE1_TEARDOWN(b,ipl); \ + return + +static u_int8_t +lca_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, BYTE, u_int8_t); +} + +static u_int16_t +lca_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, WORD, u_int16_t); +} + +static u_int32_t +lca_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, LONG, u_int32_t); +} + +static void +lca_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); +} + +static void +lca_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + CFGWRITE(b, s, f, r, data, WORD, u_int16_t); +} + +static void +lca_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + CFGWRITE(b, s, f, r, data, LONG, u_int16_t); +} + +static int lca_probe(device_t dev); +static int lca_attach(device_t dev); +static void *lca_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); +static int lca_connect_intr(device_t dev, void* ih); + +static device_method_t lca_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lca_probe), + DEVMETHOD(device_attach, lca_attach), + + /* Bus interface */ + + { 0, 0 } +}; + +static driver_t lca_driver = { + "lca", + lca_methods, + DRIVER_TYPE_MISC, + sizeof(struct lca_softc), +}; + +void +lca_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + /* Type 0 PCI conf access. */ + REGVAL64(LCA_IOC_CONF) = 0; + + if (platform.pci_intr_init) + platform.pci_intr_init(); + + chipset = lca_chipset; +} + +static int +lca_probe(device_t dev) +{ + if (lca0) + return ENXIO; + lca0 = dev; + device_set_desc(dev, "21066 PCI adapter"); /* XXX */ + + isa0 = device_add_child(dev, "isa", 0, 0); + + return 0; +} + +static int +lca_attach(device_t dev) +{ + struct lca_softc* sc = LCA_SOFTC(dev); + + lca_init(); + chipset.intrdev = isa0; + + set_iointr(alpha_dispatch_intr); + + bus_generic_attach(dev); + return 0; +} + +DRIVER_MODULE(lca, root, lca_driver, lca_devclass, 0, 0); + Property changes on: head/sys/alpha/pci/lca.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/pci/lcareg.h =================================================================== --- head/sys/alpha/pci/lcareg.h (nonexistent) +++ head/sys/alpha/pci/lcareg.h (revision 38215) @@ -0,0 +1,95 @@ +/* $NetBSD: lcareg.h,v 1.8 1997/09/05 02:14:31 thorpej Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Authors: Jeffrey Hsu, Jason R. Thorpe + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * 21066 chip registers + */ + +#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) +#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r)) + +/* + * Base addresses + */ +#define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */ +#define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ +#define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ +#define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ +#define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */ + +#define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */ +#define IOC_HAE_ADDREXT 0x00000000f8000000UL +#define IOC_HAE_RSVSD 0xffffffff07ffffffUL + +#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */ + +#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */ +#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */ +#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */ +#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */ +#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */ +#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */ +#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */ +#define IOC_STAT0_CODESHIFT 8 +#define IOC_STAT0_P_NBR 0x00000000ffffe000UL /* page number mask */ + +#define LCA_IOC_STAT1 (LCA_IOC_BASE + 0x060) /* Status 1 */ +#define IOC_STAT1_ADDR 0x00000000ffffffffUL /* PCI address mask */ + +#define LCA_IOC_TBIA (LCA_IOC_BASE + 0x080) /* TLB Invalidate All */ +#define LCA_IOC_TB_ENA (LCA_IOC_BASE + 0x0a0) /* TLB Enable */ +#define IOC_TB_ENA_TEN 0x0000000000000080UL + +#define LCA_IOC_W_BASE0 (LCA_IOC_BASE + 0x100) /* Window Base */ +#define LCA_IOC_W_MASK0 (LCA_IOC_BASE + 0x140) /* Window Mask */ +#define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */ + +#define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120) /* Window Base */ +#define LCA_IOC_W_MASK1 (LCA_IOC_BASE + 0x160) /* Window Mask */ +#define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */ + +#define IOC_W_BASE_W_BASE 0x00000000fff00000UL /* Window base value */ +#define IOC_W_BASE_SG 0x0000000100000000UL /* Window uses SGMAPs */ +#define IOC_W_BASE_WEN 0x0000000200000000UL /* Window enable */ + +#define IOC_W_MASK_1M 0x0000000000000000UL /* 1MB window */ +#define IOC_W_MASK_2M 0x0000000000100000UL /* 2MB window */ +#define IOC_W_MASK_4M 0x0000000000300000UL /* 4MB window */ +#define IOC_W_MASK_8M 0x0000000000700000UL /* 8MB window */ +#define IOC_W_MASK_16M 0x0000000000f00000UL /* 16MB window */ +#define IOC_W_MASK_32M 0x0000000001f00000UL /* 32MB window */ +#define IOC_W_MASK_64M 0x0000000003f00000UL /* 64MB window */ +#define IOC_W_MASK_128M 0x0000000007f00000UL /* 128M window */ +#define IOC_W_MASK_256M 0x000000000ff00000UL /* 256M window */ +#define IOC_W_MASK_512M 0x000000001ff00000UL /* 512M window */ +#define IOC_W_MASK_1G 0x000000003ff00000UL /* 1GB window */ +#define IOC_W_MASK_2G 0x000000007ff00000UL /* 2GB window */ +#define IOC_W_MASK_4G 0x00000000fff00000UL /* 4GB window */ + +#define IOC_W_T_BASE 0x00000000fffffc00UL /* page table base */ Property changes on: head/sys/alpha/pci/lcareg.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/pci/lcavar.h =================================================================== --- head/sys/alpha/pci/lcavar.h (nonexistent) +++ head/sys/alpha/pci/lcavar.h (revision 38215) @@ -0,0 +1,29 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + */ + +extern void lca_init(void); Property changes on: head/sys/alpha/pci/lcavar.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/alpha/pci/pcibus.c =================================================================== --- head/sys/alpha/pci/pcibus.c (revision 38214) +++ head/sys/alpha/pci/pcibus.c (revision 38215) @@ -1,202 +1,201 @@ /* * Copyright (c) 1997, Stefan Esser * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pcibus.c,v 1.2 1998/07/12 16:16:20 dfr Exp $ + * $Id: pcibus.c,v 1.3 1998/07/22 08:33:30 dfr Exp $ * */ #include #include #include #include #include #include #include #include #include static int cfgmech; static int devmax; #ifdef notyet /* return max number of devices on the bus */ int pci_maxdevs(pcicfgregs *cfg) { return chipset.maxdevs(cfg->bus); } #endif /* read configuration space register */ int pci_cfgread(pcicfgregs *cfg, int reg, int bytes) { switch (bytes) { case 1: return chipset.cfgreadb(cfg->bus, cfg->slot, cfg->func, reg); case 2: return chipset.cfgreadw(cfg->bus, cfg->slot, cfg->func, reg); case 4: return chipset.cfgreadl(cfg->bus, cfg->slot, cfg->func, reg); } return ~0; } /* write configuration space register */ void pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes) { switch (bytes) { case 1: return chipset.cfgwriteb(cfg->bus, cfg->slot, cfg->func, reg, data); case 2: return chipset.cfgwritew(cfg->bus, cfg->slot, cfg->func, reg, data); case 4: return chipset.cfgwritel(cfg->bus, cfg->slot, cfg->func, reg, data); } } int pci_cfgopen(void) { return 1; } /* * These can disappear when I update the pci code to use the new * device framework. */ struct intrec * intr_create(void *dev_instance, int irq, inthand2_t handler, void *arg, intrmask_t *maskptr, int flags) { - device_t pcib = chipset.bridge; + device_t pcib = chipset.intrdev; if (pcib) - return BUS_CREATE_INTR(pcib, pcib, - 0x900 + (irq << 4), + return BUS_CREATE_INTR(pcib, pcib, irq, (driver_intr_t*) handler, arg); else return 0; } int intr_connect(struct intrec *idesc) { - device_t pcib = chipset.bridge; + device_t pcib = chipset.intrdev; if (pcib) return BUS_CONNECT_INTR(pcib, idesc); else return EINVAL; } void alpha_platform_assign_pciintr(pcicfgregs *cfg) { if(platform.pci_intr_map) platform.pci_intr_map((void *)cfg); } void memcpy_fromio(void *d, u_int32_t s, size_t size) { char *cp = d; while (size--) *cp++ = readb(s++); } void memcpy_toio(u_int32_t d, void *s, size_t size) { char *cp = s; while (size--) writeb(d++, *cp++); } void memset_io(u_int32_t d, int val, size_t size) { while (size--) writeb(d++, val); } #include "opt_ddb.h" #ifdef DDB #include DB_COMMAND(in, db_in) { int c; int size; u_int32_t val; if (!have_addr) return; size = -1; while (c = *modif++) { switch (c) { case 'b': size = 1; break; case 'w': size = 2; break; case 'l': size = 4; break; } } if (size < 0) { db_printf("bad size\n"); return; } if (count <= 0) count = 1; while (--count >= 0) { db_printf("%08x:\t", addr); switch (size) { case 1: db_printf("%02x\n", inb(addr)); break; case 2: db_printf("%04x\n", inw(addr)); break; case 4: db_printf("%08x\n", inl(addr)); break; } } } #endif Index: head/sys/alpha/tlsb/dwlpx.c =================================================================== --- head/sys/alpha/tlsb/dwlpx.c (revision 38214) +++ head/sys/alpha/tlsb/dwlpx.c (revision 38215) @@ -1,302 +1,302 @@ /*- * Copyright (c) 1998 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: dwlpx.c,v 1.3 1998/07/12 16:23:13 dfr Exp $ + * $Id: dwlpx.c,v 1.4 1998/07/16 13:38:35 dfr Exp $ */ #include "opt_simos.h" #include #include #include #include #include #include #include #include #include #define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) #define DWLPX_BASE(n, h) ((((u_long)(n) - 4) << 36) \ | ((u_long)(h) << 34) \ | (1L << 39)) static devclass_t dwlpx_devclass; static device_t dwlpx0; /* XXX only one for now */ struct dwlpx_softc { vm_offset_t dmem_base; /* dense memory */ vm_offset_t smem_base; /* sparse memory */ vm_offset_t io_base; /* sparse i/o */ vm_offset_t cfg_base; /* sparse pci config */ }; #define DWLPX_SOFTC(dev) (struct dwlpx_softc*) device_get_softc(dev) #define SPARSE_READ(kv) (*(u_int32_t*) (kv)) #define SPARSE_WRITE(kv, d) (*(u_int32_t*) (kv) = (d)) #define SPARSE_BYTE_OFFSET(o) (((o) << 5) | ((o) & 3)) #define SPARSE_WORD_OFFSET(o) (((o) << 5) | ((o) & 2) | 0x8) #define SPARSE_LONG_OFFSET(o) (((o) << 5) | 0x18) #define SPARSE_BYTE_ADDRESS(base, o) ((base) + SPARSE_BYTE_OFFSET(o)) #define SPARSE_WORD_ADDRESS(base, o) ((base) + SPARSE_WORD_OFFSET(o)) #define SPARSE_LONG_ADDRESS(base, o) ((base) + SPARSE_LONG_OFFSET(o)) #define SPARSE_BYTE_EXTRACT(o, d) ((d) >> (8*((o) & 3))) #define SPARSE_WORD_EXTRACT(o, d) ((d) >> (8*((o) & 2))) #define SPARSE_LONG_EXTRACT(o, d) (d) #define SPARSE_BYTE_INSERT(o, d) ((d) << (8*((o) & 3))) #define SPARSE_WORD_INSERT(o, d) ((d) << (8*((o) & 2))) #define SPARSE_LONG_INSERT(o, d) (d) #define SPARSE_READ_BYTE(base, o) \ SPARSE_BYTE_EXTRACT(o, SPARSE_READ(SPARSE_BYTE_ADDRESS(base, o))) #define SPARSE_READ_WORD(base, o) \ SPARSE_WORD_EXTRACT(o, SPARSE_READ(SPARSE_WORD_ADDRESS(base, o))) #define SPARSE_READ_LONG(base, o) \ SPARSE_READ(SPARSE_LONG_ADDRESS(base, o)) #define SPARSE_WRITE_BYTE(base, o, d) \ SPARSE_WRITE(SPARSE_BYTE_ADDRESS(base, o), SPARSE_BYTE_INSERT(o, d)) #define SPARSE_WRITE_WORD(base, o, d) \ SPARSE_WRITE(SPARSE_WORD_ADDRESS(base, o), SPARSE_WORD_INSERT(o, d)) #define SPARSE_WRITE_LONG(base, o, d) \ SPARSE_WRITE(SPARSE_LONG_ADDRESS(base, o), d) static alpha_chipset_inb_t dwlpx_inb; static alpha_chipset_inw_t dwlpx_inw; static alpha_chipset_inl_t dwlpx_inl; static alpha_chipset_outb_t dwlpx_outb; static alpha_chipset_outw_t dwlpx_outw; static alpha_chipset_outl_t dwlpx_outl; static alpha_chipset_maxdevs_t dwlpx_maxdevs; static alpha_chipset_cfgreadb_t dwlpx_cfgreadb; static alpha_chipset_cfgreadw_t dwlpx_cfgreadw; static alpha_chipset_cfgreadl_t dwlpx_cfgreadl; static alpha_chipset_cfgwriteb_t dwlpx_cfgwriteb; static alpha_chipset_cfgwritew_t dwlpx_cfgwritew; static alpha_chipset_cfgwritel_t dwlpx_cfgwritel; static alpha_chipset_t dwlpx_chipset = { dwlpx_inb, dwlpx_inw, dwlpx_inl, dwlpx_outb, dwlpx_outw, dwlpx_outl, dwlpx_maxdevs, dwlpx_cfgreadb, dwlpx_cfgreadw, dwlpx_cfgreadl, dwlpx_cfgwriteb, dwlpx_cfgwritew, dwlpx_cfgwritel, }; /* * For supporting multiple busses, we will encode the dwlpx unit number into * the port address as Linux does. */ static u_int8_t dwlpx_inb(u_int32_t port) { struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); return SPARSE_READ_BYTE(sc->io_base, port); } static u_int16_t dwlpx_inw(u_int32_t port) { struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); return SPARSE_READ_WORD(sc->io_base, port); } static u_int32_t dwlpx_inl(u_int32_t port) { struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); return SPARSE_READ_LONG(sc->io_base, port); } static void dwlpx_outb(u_int32_t port, u_int8_t data) { struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); SPARSE_WRITE_BYTE(sc->io_base, port, data); } static void dwlpx_outw(u_int32_t port, u_int16_t data) { struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); SPARSE_WRITE_WORD(sc->io_base, port, data); } static void dwlpx_outl(u_int32_t port, u_int32_t data) { struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); SPARSE_WRITE_LONG(sc->io_base, port, data); } static int dwlpx_maxdevs(u_int b) { return 12; /* XXX */ } /* XXX only support bus 0 */ #define DWLPX_CFGOFF(b, s, f, r) \ (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) #define CFGREAD(b, s, f, r, width) \ struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); \ vm_offset_t off = DWLPX_CFGOFF(b, s, f, r); \ vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg_base, off); \ if (badaddr((caddr_t)kv, 4)) return ~0; \ return SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)) #define CFGWRITE(b, s, f, r, data, width) \ struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); \ vm_offset_t off = DWLPX_CFGOFF(b, s, f, r); \ vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg_base, off); \ if (badaddr((caddr_t)kv, 4)) return; \ SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)) static u_int8_t dwlpx_cfgreadb(u_int b, u_int s, u_int f, u_int r) { CFGREAD(b, s, f, r, BYTE); } static u_int16_t dwlpx_cfgreadw(u_int b, u_int s, u_int f, u_int r) { CFGREAD(b, s, f, r, WORD); } static u_int32_t dwlpx_cfgreadl(u_int b, u_int s, u_int f, u_int r) { CFGREAD(b, s, f, r, LONG); } static void dwlpx_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) { CFGWRITE(b, s, f, r, data, BYTE); } static void dwlpx_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) { CFGWRITE(b, s, f, r, data, WORD); } static void dwlpx_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) { CFGWRITE(b, s, f, r, data, LONG); } static int dwlpx_probe(device_t dev); static int dwlpx_attach(device_t dev); static driver_intr_t dwlpx_intr; static device_method_t dwlpx_methods[] = { /* Device interface */ DEVMETHOD(device_probe, dwlpx_probe), DEVMETHOD(device_attach, dwlpx_attach), { 0, 0 } }; static driver_t dwlpx_driver = { "dwlpx", dwlpx_methods, DRIVER_TYPE_MISC, sizeof(struct dwlpx_softc), }; static int dwlpx_probe(device_t dev) { if (dwlpx0) return ENXIO; dwlpx0 = dev; device_set_desc(dev, "DWLPA or DWLPB PCI adapter"); return 0; } static int dwlpx_attach(device_t dev) { struct dwlpx_softc* sc = DWLPX_SOFTC(dev); device_t parent = device_get_parent(dev); vm_offset_t regs; dwlpx0 = dev; chipset = dwlpx_chipset; - chipset.bridge = dev; + chipset.intrdev = dev; regs = KV(DWLPX_BASE(kft_get_node(dev), kft_get_hosenum(dev))); sc->dmem_base = regs + (0L << 32); sc->smem_base = regs + (1L << 32); sc->io_base = regs + (2L << 32); sc->cfg_base = regs + (3L << 32); *(u_int32_t*) (regs + PCIA_CTL(0)) = 1; /* Type1 config cycles */ BUS_CONNECT_INTR(parent, BUS_CREATE_INTR(parent, dev, 0, dwlpx_intr, 0)); return 0; } static void dwlpx_intr(void* arg) { #ifdef SIMOS extern void simos_intr(int); simos_intr(0); #endif } DRIVER_MODULE(dwlpx, kft, dwlpx_driver, dwlpx_devclass, 0, 0); Index: head/sys/conf/Makefile.alpha =================================================================== --- head/sys/conf/Makefile.alpha (revision 38214) +++ head/sys/conf/Makefile.alpha (revision 38215) @@ -1,279 +1,284 @@ # Makefile.alpha -- with config changes. # Copyright 1990 W. Jolitz # from: @(#)Makefile.alpha 7.1 5/10/91 -# $Id: Makefile.alpha,v 1.5 1998/07/22 08:23:26 dfr Exp $ +# $Id: Makefile.alpha,v 1.6 1998/07/30 08:12:14 dfr Exp $ # # Makefile for FreeBSD # # This makefile is constructed from a machine description: # config machineid # Most changes should be made in the machine description # /sys/alpha/conf/``machineid'' # after which you should do # config machineid # Generic makefile changes should be made in # /sys/alpha/conf/Makefile.alpha # after which config should be rerun for all machines. # # Which version of config(8) is required. %VERSREQ= 300005 BINFORMAT?= elf STD8X16FONT?= iso .if exists(./@/.) S= ./@ .else S= ../.. .endif ALPHA= ${S}/alpha HCC?=${CC} SIZE?=size COPTFLAGS?=-O INCLUDES= -nostdinc -I- -I. -I$S # This hack is to allow kernel compiles to succeed on machines w/out srcdist .if exists($S/../include) INCLUDES+= -I$S/../include .else INCLUDES+= -I/usr/include .endif COPTS= ${INCLUDES} ${IDENT} -DKERNEL -include opt_global.h -U__NetBSD__ CFLAGS= ${COPTFLAGS} ${CWARNFLAGS} ${DEBUG} ${COPTS} -mno-fp-regs -Wa,-mev56 LOAD_ADDRESS?= 0xfffffc0000300000 DEFINED_PROF= ${PROF} .if defined(PROF) CFLAGS+= -malign-functions=4 .if ${PROFLEVEL} >= 2 IDENT+= -DGPROF4 -DGUPROF PROF+= -mprofiler-epilogue .endif .endif NORMAL_C= ${CC} -c ${CFLAGS} ${PROF} $< NORMAL_C_C= ${CC} -c ${CFLAGS} ${PROF} ${PARAM} $< # XXX LOCORE means "don't declare C stuff" not "for locore.s". NORMAL_S= ${CC} -c -x assembler-with-cpp -DLOCORE ${COPTS} $< DRIVER_C= ${CC} -c ${CFLAGS} ${PROF} $< DRIVER_C_C= ${CC} -c ${CFLAGS} ${PROF} ${PARAM} $< DRIVER_S= ${CC} -c -x assembler-with-cpp -DLOCORE ${COPTS} $< PROFILE_C= ${CC} -c ${CFLAGS} ${PARAM} $< NORMAL_M= sh $S/kern/makedevops.sh -c $<;\ ${CC} -c ${CFLAGS} ${PROF} `basename $< .m`.c # ${ALPHA}/alpha/setdef0.c and ${ALPHA}/alpha/setdef1.c are intentionally # omitted from SYSTEM_CFILES. They depend on setdefs.h, a header which # is generated from all of ${OBJS}. We don't want to have to compile # everything just to do a make depend. SYSTEM_CFILES= ioconf.c param.c vnode_if.c config.c SYSTEM_SFILES= ${ALPHA}/alpha/locore.s SYSTEM_DEP= Makefile symbols.exclude symbols.sort ${SYSTEM_OBJS} .if ${CFLAGS:M-g} == "" SYMORDER_EXCLUDE=-x symbols.exclude .endif SYSTEM_LD_HEAD= @echo loading $@; rm -f $@ .if ${BINFORMAT} == elf SYSTEM_OBJS= locore.o setdef0.o vnode_if.o \ ${OBJS} ioconf.o param.o config.o \ - setdef1.o + setdef1.o hack.so SYSTEM_LD= @${LD} --export-dynamic -T$S/alpha/conf/kernel.script -e locorestart \ -o $@ -X ${SYSTEM_OBJS} vers.o SYSTEM_LD_TAIL= @${SIZE} $@; chmod 755 $@ .endif %BEFORE_DEPEND %OBJS %CFILES %SFILES %LOAD %CLEAN clean: rm -f *.o *.s eddep errs genassym gensetdefs kernel linterrs \ makelinks param.c setdefs.h symbols.exclude symbols.sort tags \ vers.c vnode_if.c vnode_if.h ${CLEAN} #lint: /tmp param.c # @lint -hbxn -DGENERIC -Dvolatile= ${COPTS} ${PARAM} \ # ${ALPHA}/alpha/Locore.c ${CFILES} ioconf.c param.c | \ # grep -v 'struct/union .* never defined' | \ # grep -v 'possible pointer alignment problem' symbols.exclude: Makefile echo "gcc2_compiled." >symbols.exclude echo "___gnu_compiled_c" >>symbols.exclude symbols.sort: ${ALPHA}/alpha/symbols.raw grep -v '^#' ${ALPHA}/alpha/symbols.raw \ | sed 's/^ //' | sort -u > symbols.sort locore.o: ${ALPHA}/alpha/locore.s assym.s ${NORMAL_S} + +hack.so: Makefile + echo "void __elf_kld_hack() {}" > hack.c + ${CC} -shared -nostdlib hack.c -o hack.so + rm -f hack.c setdef0.o: ${ALPHA}/alpha/setdef0.c setdefs.h ${NORMAL_C} setdef1.o: ${ALPHA}/alpha/setdef1.c setdefs.h ${NORMAL_C} setdefs.h: gensetdefs ${OBJS} @echo Generating kernel linker sets @./gensetdefs ${OBJS} >setdefs.h gensetdefs: gensetdefs.o ${HCC} -static gensetdefs.o -o $@ gensetdefs.o: ${ALPHA}/alpha/gensetdefs.c ${HCC} -c -I${INCLUDES} ${ALPHA}/alpha/gensetdefs.c # everything potentially depends on the Makefile since everything potentially # depends on the options. Some things are more dependent on the Makefile for # historical reasons. machdep.o: Makefile # the following is necessary because autoconf.o depends on #if GENERIC autoconf.o: Makefile # XXX - may no longer be needed locore.o: Makefile # depends on KDB (cons.o also depends on GENERIC) trap.o cons.o: Makefile # this rule stops ./assym.s in .depend from causing problems ./assym.s: assym.s assym.s: genassym ./genassym >assym.s # Some of the defines that genassym outputs may well depend on the # value of kernel options. genassym.o: ${ALPHA}/alpha/genassym.c Makefile opt_global.h ${HCC} -c ${COPTS} ${PARAM} -UKERNEL ${ALPHA}/alpha/genassym.c genassym: genassym.o ${HCC} -static ${COPTS} ${PARAM} genassym.o -o $@ SYSTEM_OBJS+= __divqu.o __divq.o __divlu.o __divl.o SYSTEM_OBJS+= __remqu.o __remq.o __remlu.o __reml.o CLEAN+= __divqu.S __divq.S __divlu.S __divl.S CLEAN+= __remqu.S __remq.S __remlu.S __reml.S __divqu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divqu')define(OP,\`div')define(S,\`false')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __divq.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divq')define(OP,\`div')define(S,\`true')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __divlu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divlu')define(OP,\`div')define(S,\`false')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __divl.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__divl')define(OP,\`div')define(S,\`true')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __remqu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__remqu')define(OP,\`rem')define(S,\`false')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __remq.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__remq')define(OP,\`rem')define(S,\`true')"; \ echo "define(WORDSIZE,64)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __remlu.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__remlu')define(OP,\`rem')define(S,\`false')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} __reml.S: ${S}/alpha/alpha/divrem.m4 @echo 'building ${.TARGET} from ${.ALLSRC}' @(echo "define(NAME,\`__reml')define(OP,\`rem')define(S,\`true')"; \ echo "define(WORDSIZE,32)"; cat ${.ALLSRC}) | m4 > ${.TARGET} ${OBJS}: opt_global.h # XXX this assumes that the options for NORMAL_C* and DRIVER_C* are identical. depend: assym.s param.c vnode_if.h ${BEFORE_DEPEND} rm -f .newdep mkdep -a -f .newdep ${COPTS} ${CFILES} ${SYSTEM_CFILES} mkdep -a -f .newdep ${COPTS} ${PARAM} -UKERNEL ${ALPHA}/alpha/genassym.c MKDEP_CPP="${CC} -E -x assembler-with-cpp" ; export MKDEP_CPP ; \ mkdep -a -f .newdep -DLOCORE ${COPTS} ${SFILES} ${SYSTEM_SFILES} rm -f .depend mv -f .newdep .depend cleandepend: rm -f .depend links: egrep '#if' ${CFILES:Nswapkernel.c} | sed -f $S/conf/defines | \ sed -e 's/:.*//' -e 's/\.c/.o/' | sort -u > dontlink echo ${CFILES:Nswapkernel.c} | tr -s ' ' '\12' | sed 's/\.c/.o/' | \ sort -u | comm -23 - dontlink | \ sed 's,../.*/\(.*.o\),rm -f \1;ln -s ../GENERIC/\1 \1,' > makelinks sh makelinks && rm -f dontlink tags: @echo "see $S/kern/Makefile for tags" install: @if [ ! -f kernel ] ; then \ echo "You must first build your kernel before trying to install." ; \ exit 1 ; \ fi .if exists(${DESTDIR}/kernel) chflags noschg ${DESTDIR}/kernel mv ${DESTDIR}/kernel ${DESTDIR}/kernel.old .endif PATH=$${PATH}:/sbin:/usr/sbin; \ if [ `sysctl -n kern.bootfile` = ${DESTDIR}/kernel ] ; then \ sysctl -w kern.bootfile=${DESTDIR}/kernel.old ; \ if [ -f /var/db/kvm_kernel.db ] ; then \ mv -f /var/db/kvm_kernel.db /var/db/kvm_kernel.old.db ; \ fi \ fi install -c -m 555 -o root -g wheel -fschg kernel ${DESTDIR}/ ioconf.o: ioconf.c $S/sys/param.h $S/sys/buf.h ${CC} -c ${CFLAGS} ioconf.c param.c: $S/conf/param.c -rm -f param.c cp $S/conf/param.c . param.o: param.c Makefile ${CC} -c ${CFLAGS} ${PARAM} param.c vers.o: ${SYSTEM_DEP} ${SYSTEM_SWAP_DEP} sh $S/conf/newvers.sh ${KERN_IDENT} ${IDENT} ${CC} ${CFLAGS} -c vers.c vnode_if.c: $S/kern/vnode_if.sh $S/kern/vnode_if.src sh $S/kern/vnode_if.sh $S/kern/vnode_if.src vnode_if.h: $S/kern/vnode_if.sh $S/kern/vnode_if.src sh $S/kern/vnode_if.sh $S/kern/vnode_if.src .include %RULES # DO NOT DELETE THIS LINE -- make depend uses it Index: head/sys/conf/files.alpha =================================================================== --- head/sys/conf/files.alpha (revision 38214) +++ head/sys/conf/files.alpha (revision 38215) @@ -1,125 +1,130 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # -# $Id: files.alpha,v 1.3 1998/07/12 16:26:52 dfr Exp $ +# $Id: files.alpha,v 1.4 1998/07/22 08:24:39 dfr Exp $ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # # font8x16.o optional std8x16font \ compile-with "uudecode < /usr/share/syscons/fonts/${STD8X16FONT}-8x16.fnt && file2c 'unsigned char font_16[16*256] = {' '};' < ${STD8X16FONT}-8x16 > font8x16.c && ${CC} -c ${CFLAGS} font8x16.c" \ no-implicit-rule before-depend \ clean "${STD8X16FONT}-8x16 font8x16.c" # alpha/alpha/autoconf.c standard device-driver alpha/alpha/cpuconf.c standard alpha/alpha/dec_kn8ae.c optional dec_kn8ae alpha/alpha/dec_eb164.c optional dec_eb164 alpha/alpha/dec_kn20aa.c optional dec_kn20aa +alpha/alpha/dec_2100_a50.c optional dec_2100_a50 +alpha/alpha/dec_st550.c optional dec_st550 +alpha/alpha/dec_axppci_33.c optional dec_axppci_33 alpha/alpha/mountroot.c optional slice alpha/alpha/ipl_funcs.c standard alpha/alpha/pal.s standard alpha/alpha/cons.c standard alpha/alpha/prom.c standard alpha/alpha/promcons.c standard alpha/alpha/prom_disp.s standard alpha/alpha/alpha-gdbstub.c optional ddb alpha/alpha/db_disasm.c optional ddb alpha/alpha/db_interface.c optional ddb alpha/alpha/db_trace.c optional ddb alpha/alpha/exception.s standard alpha/alpha/in_cksum.c optional inet # locore.s needs to be handled in Makefile to put it first. Otherwise it's # now normal. # alpha/alpha/locore.s standard alpha/alpha/machdep.c standard alpha/alpha/math_emulate.c optional math_emulate alpha/alpha/mem.c standard alpha/alpha/mp_machdep.c optional smp alpha/alpha/perfmon.c optional perfmon profiling-routine alpha/alpha/perfmon.c optional perfmon alpha/alpha/pmap.c standard alpha/alpha/procfs_machdep.c standard alpha/alpha/simplelock.s optional smp alpha/alpha/support.s standard alpha/alpha/swtch.s standard alpha/alpha/sys_machdep.c standard alpha/alpha/trap.c standard alpha/alpha/interrupt.c standard alpha/alpha/userconfig.c optional userconfig alpha/alpha/vm_machdep.c standard alpha/alpha/clock.c standard alpha/alpha/clock_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "clock_if.c" clock_if.h standard \ dependency "$S/kern/makedevops.sh $S/alpha/alpha/clock_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/alpha/alpha/clock_if.m" \ no-obj no-implicit-rule before-depend \ clean "clock_if.h" alpha/alpha/diskslice_machdep.c standard alpha/tlsb/tlsb.c optional tlsb alpha/tlsb/gbus.c optional gbus alpha/tlsb/kftxx.c optional kft alpha/tlsb/mcclock_tlsb.c optional gbus alpha/tlsb/zs_tlsb.c optional gbus alpha/tlsb/dwlpx.c optional dwlpx dev/dec/mcclock.c standard dev/dec/mcclock_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "mcclock_if.c" mcclock_if.h standard \ dependency "$S/kern/makedevops.sh $S/dev/dec/mcclock_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/dev/dec/mcclock_if.m" \ no-obj no-implicit-rule before-depend \ clean "mcclock_if.h" alpha/pci/cia.c optional cia alpha/pci/pci_eb164_intr.s optional cia alpha/isa/mcclock_isa.c optional cia +alpha/pci/apecs.c optional apecs +alpha/pci/lca.c optional lca alpha/pci/pcibus.c optional pci alpha/isa/isa.c optional isa kern/link_elf.c standard kern/subr_bus.c standard kern/device_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "device_if.c" device_if.h standard \ dependency "$S/kern/makedevops.sh $S/kern/device_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/kern/device_if.m" \ no-obj no-implicit-rule before-depend \ clean "device_if.h" kern/bus_if.m standard \ dependency "$S/kern/makedevops.sh" \ clean "bus_if.c" bus_if.h standard \ dependency "$S/kern/makedevops.sh $S/kern/bus_if.m" \ compile-with "sh $S/kern/makedevops.sh -h $S/kern/bus_if.m" \ no-obj no-implicit-rule before-depend \ clean "bus_if.h" libkern/bcd.c standard libkern/bcmp.c standard libkern/ffs.c standard libkern/inet_ntoa.c standard libkern/index.c standard libkern/mcount.c optional profiling-routine libkern/qsort.c standard libkern/random.c standard libkern/scanc.c standard libkern/skpc.c standard libkern/strcat.c standard libkern/strcmp.c standard libkern/strcpy.c standard libkern/strlen.c standard libkern/strncmp.c standard libkern/strncpy.c standard libkern/alpha/htonl.S standard libkern/alpha/htons.S standard libkern/alpha/ntohl.S standard libkern/alpha/ntohs.S standard isa/sio.c optional sio device-driver isa/kbdio.c optional psm device-driver isa/kbdio.c optional sc device-driver isa/syscons.c optional sc device-driver Index: head/sys/conf/ldscript.alpha =================================================================== --- head/sys/conf/ldscript.alpha (revision 38214) +++ head/sys/conf/ldscript.alpha (revision 38215) @@ -1,133 +1,132 @@ OUTPUT_FORMAT("elf64-alpha", "elf64-alpha", "elf64-alpha") OUTPUT_ARCH(alpha) ENTRY(__start) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/egcs/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/egcs/alphaev5-unknown-linux-gnu/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + kernel_text = 0xfffffc0000300000; SECTIONS { /* Read-only sections, merged into text segment: */ . = 0xfffffc0000300000 + SIZEOF_HEADERS; .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .gnu.version : { *(.gnu.version) } .gnu.version_d : { *(.gnu.version_d) } .gnu.version_r : { *(.gnu.version_r) } .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) } .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) } .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) } .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) } .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } .rel.init : { *(.rel.init) } .rela.init : { *(.rela.init) } .rel.fini : { *(.rel.fini) } .rela.fini : { *(.rela.fini) } .rel.bss : { *(.rel.bss) } .rela.bss : { *(.rela.bss) } .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } =0x47ff041f .text : { *(.text) *(.stub) /* .gnu.warning sections are handled specially by elf32.em. */ *(.gnu.warning) *(.gnu.linkonce.t*) } =0x47ff041f _etext = .; PROVIDE (etext = .); .fini : { *(.fini) } =0x47ff041f .rodata : { *(.rodata) *(.gnu.linkonce.r*) } .rodata1 : { *(.rodata1) } .reginfo : { *(.reginfo) } /* Adjust the address for the data segment. We want to adjust up to the same address within the page on the next page up. */ . = .; .data : { *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS } .data1 : { *(.data1) } .ctors : { *(.ctors) } .dtors : { *(.dtors) } .plt : { *(.plt) } .got : { *(.got.plt) *(.got) } .dynamic : { *(.dynamic) } /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ .sdata : { *(.sdata) } _edata = .; PROVIDE (edata = .); __bss_start = .; .sbss : { *(.sbss) *(.scommon) } .bss : { *(.dynbss) *(.bss) *(COMMON) } . = ALIGN(64 / 8); _end = . ; PROVIDE (end = .); /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } /* These must appear regardless of . */ } Index: head/sys/conf/ldscript.powerpc =================================================================== --- head/sys/conf/ldscript.powerpc (revision 38214) +++ head/sys/conf/ldscript.powerpc (revision 38215) @@ -1,133 +1,132 @@ OUTPUT_FORMAT("elf64-alpha", "elf64-alpha", "elf64-alpha") OUTPUT_ARCH(alpha) ENTRY(__start) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/egcs/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/egcs/alphaev5-unknown-linux-gnu/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + kernel_text = 0xfffffc0000300000; SECTIONS { /* Read-only sections, merged into text segment: */ . = 0xfffffc0000300000 + SIZEOF_HEADERS; .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .gnu.version : { *(.gnu.version) } .gnu.version_d : { *(.gnu.version_d) } .gnu.version_r : { *(.gnu.version_r) } .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) } .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) } .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) } .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) } .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } .rel.init : { *(.rel.init) } .rela.init : { *(.rela.init) } .rel.fini : { *(.rel.fini) } .rela.fini : { *(.rela.fini) } .rel.bss : { *(.rel.bss) } .rela.bss : { *(.rela.bss) } .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } =0x47ff041f .text : { *(.text) *(.stub) /* .gnu.warning sections are handled specially by elf32.em. */ *(.gnu.warning) *(.gnu.linkonce.t*) } =0x47ff041f _etext = .; PROVIDE (etext = .); .fini : { *(.fini) } =0x47ff041f .rodata : { *(.rodata) *(.gnu.linkonce.r*) } .rodata1 : { *(.rodata1) } .reginfo : { *(.reginfo) } /* Adjust the address for the data segment. We want to adjust up to the same address within the page on the next page up. */ . = .; .data : { *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS } .data1 : { *(.data1) } .ctors : { *(.ctors) } .dtors : { *(.dtors) } .plt : { *(.plt) } .got : { *(.got.plt) *(.got) } .dynamic : { *(.dynamic) } /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ .sdata : { *(.sdata) } _edata = .; PROVIDE (edata = .); __bss_start = .; .sbss : { *(.sbss) *(.scommon) } .bss : { *(.dynbss) *(.bss) *(COMMON) } . = ALIGN(64 / 8); _end = . ; PROVIDE (end = .); /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } /* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. */ /* DWARF 1 */ .debug 0 : { *(.debug) } .line 0 : { *(.line) } /* GNU DWARF 1 extensions */ .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } /* DWARF 1.1 and DWARF 2 */ .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } /* DWARF 2 */ .debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } /* SGI/MIPS DWARF 2 extensions */ .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } /* These must appear regardless of . */ } Index: head/sys/conf/options.alpha =================================================================== --- head/sys/conf/options.alpha (revision 38214) +++ head/sys/conf/options.alpha (revision 38215) @@ -1,36 +1,39 @@ -# $Id: options.alpha,v 1.2 1998/07/12 16:28:09 dfr Exp $ +# $Id: options.alpha,v 1.3 1998/07/22 08:24:39 dfr Exp $ EV5 opt_global.h DEC_KN8AE opt_cpu.h DEC_EB164 opt_cpu.h DEC_KN20AA opt_cpu.h +DEC_2100_A50 opt_cpu.h +DEC_ST550 opt_cpu.h +DEC_AXPPCI_33 opt_cpu.h ATAPI opt_atapi.h ATAPI_STATIC opt_atapi.h CMD640 opt_wd.h SHOW_BUSYBUFS PANIC_REBOOT_WAIT_TIME opt_panic.h AHC_TAGENABLE opt_aic7xxx.h AHC_SCBPAGING_ENABLE opt_aic7xxx.h AHC_ALLOW_MEMIO opt_aic7xxx.h AHC_SHARE_SCBS opt_aic7xxx.h SC_SPLASH_SCREEN opt_syscons.h MAXCONS opt_syscons.h SLOW_VGA opt_syscons.h STD8X16FONT opt_syscons.h SC_HISTORY_SIZE opt_syscons.h SC_DISABLE_REBOOT opt_syscons.h SC_MOUSE_CHAR opt_syscons.h PSM_HOOKAPM opt_psm.h PSM_RESETAFTERSUSPEND opt_psm.h PSM_DEBUG opt_psm.h KBD_RESETDELAY opt_kbdio.h KBD_MAXRETRY opt_kbdio.h KBD_MAXWAIT opt_kbdio.h KBDIO_DEBUG opt_kbdio.h