Index: stable/12/sys/dev/qat/qat_c2xxxreg.h
===================================================================
--- stable/12/sys/dev/qat/qat_c2xxxreg.h	(revision 368303)
+++ stable/12/sys/dev/qat/qat_c2xxxreg.h	(revision 368304)
@@ -1,177 +1,177 @@
 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
 /*	$NetBSD: qat_c2xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
 
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
 /*
  *   Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
  *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 /* $FreeBSD$ */
 
 #ifndef _DEV_PCI_QAT_C2XXXREG_H_
 #define _DEV_PCI_QAT_C2XXXREG_H_
 
 /* PCI revision IDs */
 #define QAT_REVID_C2XXX_A0		0x00
 #define QAT_REVID_C2XXX_B0		0x02
 #define QAT_REVID_C2XXX_C0		0x03
 
 /* Max number of accelerators and engines */
 #define MAX_ACCEL_C2XXX			1
 #define MAX_AE_C2XXX			2
 
 /* PCIe BAR index */
 #define BAR_SRAM_ID_C2XXX		NO_PCI_REG
 #define BAR_PMISC_ID_C2XXX		0
 #define BAR_ETR_ID_C2XXX		1
 
 #define ACCEL_MASK_C2XXX		0x1
 #define AE_MASK_C2XXX			0x3
 
 #define MSIX_AE_VEC_GAP_C2XXX		8
 
 /* PCIe configuration space registers */
 /* PESRAM: 512K eSRAM */
 #define BAR_PESRAM_C2XXX		NO_PCI_REG
 #define BAR_PESRAM_SIZE_C2XXX		0
 
 /*
  * PMISC: 16K CAP, 16K Scratch, 32K SSU(QATs),
  *        32K AE CSRs and transfer registers, 8K CHAP/PMU,
  *        4K EP CSRs, 4K MSI-X Tables
  */
 #define BAR_PMISC_C2XXX			0x18
 #define BAR_PMISC_SIZE_C2XXX		0x20000	/* 128K */
 
 /* PETRINGCSR: 8K 16 bundles of ET Ring CSRs */
 #define BAR_PETRINGCSR_C2XXX		0x20
 #define BAR_PETRINGCSR_SIZE_C2XXX	0x4000	/* 16K */
 
 /* Fuse Control */
 #define FUSECTL_C2XXX_PKE_DISABLE	(1 << 6)
 #define FUSECTL_C2XXX_ATH_DISABLE	(1 << 5)
 #define FUSECTL_C2XXX_CPH_DISABLE	(1 << 4)
 #define FUSECTL_C2XXX_LOW_SKU		(1 << 3)
 #define FUSECTL_C2XXX_MID_SKU		(1 << 2)
 #define FUSECTL_C2XXX_AE1_DISABLE	(1 << 1)
 
 /* SINT: Signal Target Raw Interrupt Register */
 #define EP_SINTPF_C2XXX			0x1A024
 
 /* SMIA: Signal Target IA Mask Register */
 #define EP_SMIA_C2XXX				0x1A028
 #define EP_SMIA_BUNDLES_IRQ_MASK_C2XXX		0xFF
 #define EP_SMIA_AE_IRQ_MASK_C2XXX		0x10000
 #define EP_SMIA_MASK_C2XXX			\
 	(EP_SMIA_BUNDLES_IRQ_MASK_C2XXX | EP_SMIA_AE_IRQ_MASK_C2XXX)
 
 #define EP_RIMISCCTL_C2XXX		0x1A0C4
 #define EP_RIMISCCTL_MASK_C2XXX		0x40000000
 
 #define PFCGCIOSFPRIR_REG_C2XXX			0x2C0
 #define PFCGCIOSFPRIR_MASK_C2XXX		0XFFFF7FFF
 
 /* BAR sub-regions */
 #define PESRAM_BAR_C2XXX		NO_PCI_REG
 #define PESRAM_OFFSET_C2XXX		0x0
 #define PESRAM_SIZE_C2XXX		0x0
 #define CAP_GLOBAL_BAR_C2XXX		BAR_PMISC_C2XXX
 #define CAP_GLOBAL_OFFSET_C2XXX		0x00000
 #define CAP_GLOBAL_SIZE_C2XXX		0x04000
 #define CAP_HASH_OFFSET			0x900
 #define SCRATCH_BAR_C2XXX		NO_PCI_REG
 #define SCRATCH_OFFSET_C2XXX		NO_REG_OFFSET
 #define SCRATCH_SIZE_C2XXX		0x0
 #define SSU_BAR_C2XXX			BAR_PMISC_C2XXX
 #define SSU_OFFSET_C2XXX		0x08000
 #define SSU_SIZE_C2XXX			0x08000
 #define AE_BAR_C2XXX			BAR_PMISC_C2XXX
 #define AE_OFFSET_C2XXX			0x10000
 #define AE_LOCAL_OFFSET_C2XXX		0x10800
 #define PMU_BAR_C2XXX			NO_PCI_REG
 #define PMU_OFFSET_C2XXX		NO_REG_OFFSET
 #define PMU_SIZE_C2XXX			0x0
 #define EP_BAR_C2XXX			BAR_PMISC_C2XXX
 #define EP_OFFSET_C2XXX			0x1A000
 #define EP_SIZE_C2XXX			0x01000
 #define MSIX_TAB_BAR_C2XXX		NO_PCI_REG	/* mapped by pci(9) */
 #define MSIX_TAB_OFFSET_C2XXX		0x1B000
 #define MSIX_TAB_SIZE_C2XXX		0x01000
 #define PETRINGCSR_BAR_C2XXX		BAR_PETRINGCSR_C2XXX
 #define PETRINGCSR_OFFSET_C2XXX		0x0
 #define PETRINGCSR_SIZE_C2XXX		0x0	/* use size of BAR */
 
 /* ETR */
 #define ETR_MAX_BANKS_C2XXX		8
 #define ETR_MAX_ET_RINGS_C2XXX		\
 	(ETR_MAX_BANKS_C2XXX * ETR_MAX_RINGS_PER_BANK_C2XXX)
 #define ETR_MAX_AP_BANKS_C2XXX		4
 
 #define ETR_TX_RX_GAP_C2XXX		1
 #define ETR_TX_RINGS_MASK_C2XXX		0x51
 
 #define ETR_BUNDLE_SIZE_C2XXX		0x0200
 
 /* Initial bank Interrupt Source mask */
 #define ETR_INT_SRCSEL_MASK_0_C2XXX	0x4444444CUL
 #define ETR_INT_SRCSEL_MASK_X_C2XXX	0x44444444UL
 
 /* AE firmware */
 #define AE_FW_PROD_TYPE_C2XXX			0x00800000
-#define AE_FW_MOF_NAME_C2XXX		"mof_firmware_c2xxx"
+#define AE_FW_MOF_NAME_C2XXX		"qat_c2xxxfw"
 #define AE_FW_MMP_NAME_C2XXX		"mmp_firmware_c2xxx"
 #define AE_FW_UOF_NAME_C2XXX_A0		"icp_qat_nae.uof"
 #define AE_FW_UOF_NAME_C2XXX_B0		"icp_qat_nae_b0.uof"
 
 #endif
Index: stable/12/sys/dev/qat/qat_c3xxxreg.h
===================================================================
--- stable/12/sys/dev/qat/qat_c3xxxreg.h	(revision 368303)
+++ stable/12/sys/dev/qat/qat_c3xxxreg.h	(revision 368304)
@@ -1,178 +1,178 @@
 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
 /*	$NetBSD: qat_c3xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
 
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
 /*
  *   Copyright(c) 2014 Intel Corporation.
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
  *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 /* $FreeBSD$ */
 
 #ifndef _DEV_PCI_QAT_C3XXXREG_H_
 #define _DEV_PCI_QAT_C3XXXREG_H_
 
 /* Max number of accelerators and engines */
 #define MAX_ACCEL_C3XXX			3
 #define MAX_AE_C3XXX			6
 
 /* PCIe BAR index */
 #define BAR_SRAM_ID_C3XXX		NO_PCI_REG
 #define BAR_PMISC_ID_C3XXX		0
 #define BAR_ETR_ID_C3XXX		1
 
 /* BAR PMISC sub-regions */
 #define AE_OFFSET_C3XXX			0x20000
 #define AE_LOCAL_OFFSET_C3XXX		0x20800
 #define CAP_GLOBAL_OFFSET_C3XXX		0x30000
 
 #define SOFTSTRAP_REG_C3XXX			0x2EC
 #define SOFTSTRAP_SS_POWERGATE_CY_C3XXX		__BIT(23)
 #define SOFTSTRAP_SS_POWERGATE_PKE_C3XXX	__BIT(24)
 
 #define ACCEL_REG_OFFSET_C3XXX		16
 #define ACCEL_MASK_C3XXX		0x7
 #define AE_MASK_C3XXX			0x3F
 
 #define SMIAPF0_C3XXX			0x3A028
 #define SMIAPF1_C3XXX			0x3A030
 #define SMIA0_MASK_C3XXX		0xFFFF
 #define SMIA1_MASK_C3XXX		0x1
 
 /* Error detection and correction */
 #define AE_CTX_ENABLES_C3XXX(i)		((i) * 0x1000 + 0x20818)
 #define AE_MISC_CONTROL_C3XXX(i)	((i) * 0x1000 + 0x20960)
 #define ENABLE_AE_ECC_ERR_C3XXX		__BIT(28)
 #define ENABLE_AE_ECC_PARITY_CORR_C3XXX	(__BIT(24) | __BIT(12))
 #define ERRSSMSH_EN_C3XXX		__BIT(3)
 /* BIT(2) enables the logging of push/pull data errors. */
 #define PPERR_EN_C3XXX			(__BIT(2))
 
 /* Mask for VF2PF interrupts */
 #define VF2PF1_16_C3XXX			(0xFFFF << 9)
 #define ERRSOU3_VF2PF_C3XXX(errsou3)	(((errsou3) & 0x01FFFE00) >> 9)
 #define ERRMSK3_VF2PF_C3XXX(vf_mask)	(((vf_mask) & 0xFFFF) << 9)
 
 /* Masks for correctable error interrupts. */
 #define ERRMSK0_CERR_C3XXX		(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
 #define ERRMSK1_CERR_C3XXX		(__BIT(8) | __BIT(0))
 #define ERRMSK5_CERR_C3XXX		(0)
 
 /* Masks for uncorrectable error interrupts. */
 #define ERRMSK0_UERR_C3XXX		(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
 #define ERRMSK1_UERR_C3XXX		(__BIT(9) | __BIT(1))
 #define ERRMSK3_UERR_C3XXX		(__BIT(6) | __BIT(5) | __BIT(4) | __BIT(3) | \
 					 __BIT(2) | __BIT(0))
 #define ERRMSK5_UERR_C3XXX		(__BIT(16))
 
 /* RI CPP control */
 #define RICPPINTCTL_C3XXX		(0x3A000 + 0x110)
 /*
  * BIT(2) enables error detection and reporting on the RI Parity Error.
  * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
  * BIT(0) enables error detection and reporting on the RI CPP Push interface.
  */
 #define RICPP_EN_C3XXX			(__BIT(2) | __BIT(1) | __BIT(0))
 
 /* TI CPP control */
 #define TICPPINTCTL_C3XXX		(0x3A400 + 0x138)
 /*
  * BIT(3) enables error detection and reporting on the ETR Parity Error.
  * BIT(2) enables error detection and reporting on the TI Parity Error.
  * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
  * BIT(0) enables error detection and reporting on the TI CPP Push interface.
  */
 #define TICPP_EN_C3XXX		\
 	(__BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
 
 /* CFC Uncorrectable Errors */
 #define CPP_CFC_ERR_CTRL_C3XXX	(0x30000 + 0xC00)
 /*
  * BIT(1) enables interrupt.
  * BIT(0) enables detecting and logging of push/pull data errors.
  */
 #define CPP_CFC_UE_C3XXX		(__BIT(1) | __BIT(0))
 
 #define SLICEPWRDOWN_C3XXX(i)	((i) * 0x4000 + 0x2C)
 /* Enabling PKE4-PKE0. */
 #define MMP_PWR_UP_MSK_C3XXX		\
 	(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
 
 /* CPM Uncorrectable Errors */
 #define INTMASKSSM_C3XXX(i)		((i) * 0x4000 + 0x0)
 /* Disabling interrupts for correctable errors. */
 #define INTMASKSSM_UERR_C3XXX	\
 	(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
 
 /* MMP */
 /* BIT(3) enables correction. */
 #define CERRSSMMMP_EN_C3XXX		(__BIT(3))
 
 /* BIT(3) enables logging. */
 #define UERRSSMMMP_EN_C3XXX		(__BIT(3))
 
 /* ETR */
 #define ETR_MAX_BANKS_C3XXX		16
 #define ETR_TX_RX_GAP_C3XXX		8
 #define ETR_TX_RINGS_MASK_C3XXX		0xFF
 #define ETR_BUNDLE_SIZE_C3XXX		0x1000
 
 /* AE firmware */
 #define AE_FW_PROD_TYPE_C3XXX		0x02000000
-#define AE_FW_MOF_NAME_C3XXX	"qat_c3xxx"
+#define AE_FW_MOF_NAME_C3XXX	"qat_c3xxxfw"
 #define AE_FW_MMP_NAME_C3XXX	"qat_c3xxx_mmp"
 #define AE_FW_UOF_NAME_C3XXX	"icp_qat_ae.suof"
 
 /* Clock frequency */
 #define CLOCK_PER_SEC_C3XXX		(685 * 1000000 / 16)
 
 #endif
Index: stable/12/sys/dev/qat/qat_c62xreg.h
===================================================================
--- stable/12/sys/dev/qat/qat_c62xreg.h	(revision 368303)
+++ stable/12/sys/dev/qat/qat_c62xreg.h	(revision 368304)
@@ -1,201 +1,201 @@
 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
 /*	$NetBSD: qat_c62xreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
 
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
 /*
  *   Copyright(c) 2014 Intel Corporation.
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
  *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 /* $FreeBSD$ */
 
 #ifndef _DEV_PCI_QAT_C62XREG_H_
 #define _DEV_PCI_QAT_C62XREG_H_
 
 /* Max number of accelerators and engines */
 #define MAX_ACCEL_C62X			5
 #define MAX_AE_C62X			10
 
 /* PCIe BAR index */
 #define BAR_SRAM_ID_C62X		0
 #define BAR_PMISC_ID_C62X		1
 #define BAR_ETR_ID_C62X			2
 
 /* BAR PMISC sub-regions */
 #define AE_OFFSET_C62X			0x20000
 #define AE_LOCAL_OFFSET_C62X		0x20800
 #define CAP_GLOBAL_OFFSET_C62X		0x30000
 
 #define SOFTSTRAP_REG_C62X			0x2EC
 #define SOFTSTRAP_SS_POWERGATE_CY_C62X		__BIT(23)
 #define SOFTSTRAP_SS_POWERGATE_PKE_C62X		__BIT(24)
 
 #define ACCEL_REG_OFFSET_C62X		16
 #define ACCEL_MASK_C62X			0x1F
 #define AE_MASK_C62X			0x3FF
 
 #define SMIAPF0_C62X			0x3A028
 #define SMIAPF1_C62X			0x3A030
 #define SMIA0_MASK_C62X			0xFFFF
 #define SMIA1_MASK_C62X			0x1
 
 /* Error detection and correction */
 #define AE_CTX_ENABLES_C62X(i)		((i) * 0x1000 + 0x20818)
 #define AE_MISC_CONTROL_C62X(i)		((i) * 0x1000 + 0x20960)
 #define ENABLE_AE_ECC_ERR_C62X		__BIT(28)
 #define ENABLE_AE_ECC_PARITY_CORR_C62X	(__BIT(24) | __BIT(12))
 #define ERRSSMSH_EN_C62X		__BIT(3)
 /* BIT(2) enables the logging of push/pull data errors. */
 #define PPERR_EN_C62X			(__BIT(2))
 
 /* Mask for VF2PF interrupts */
 #define VF2PF1_16_C62X			(0xFFFF << 9)
 #define ERRSOU3_VF2PF_C62X(errsou3)	(((errsou3) & 0x01FFFE00) >> 9)
 #define ERRMSK3_VF2PF_C62X(vf_mask)	(((vf_mask) & 0xFFFF) << 9)
 
 /* Masks for correctable error interrupts. */
 #define ERRMSK0_CERR_C62X	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
 #define ERRMSK1_CERR_C62X	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
 #define ERRMSK3_CERR_C62X	(__BIT(7))
 #define ERRMSK4_CERR_C62X	(__BIT(8) | __BIT(0))
 #define ERRMSK5_CERR_C62X	(0)
 
 /* Masks for uncorrectable error interrupts. */
 #define ERRMSK0_UERR_C62X	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
 #define ERRMSK1_UERR_C62X	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
 #define ERRMSK3_UERR_C62X	(__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
 				 __BIT(3) | __BIT(2) | __BIT(0))
 #define ERRMSK4_UERR_C62X	(__BIT(9) | __BIT(1))
 #define ERRMSK5_UERR_C62X	(__BIT(18) | __BIT(17) | __BIT(16))
 
 /* RI CPP control */
 #define RICPPINTCTL_C62X		(0x3A000 + 0x110)
 /*
  * BIT(2) enables error detection and reporting on the RI Parity Error.
  * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
  * BIT(0) enables error detection and reporting on the RI CPP Push interface.
  */
 #define RICPP_EN_C62X			(__BIT(2) | __BIT(1) | __BIT(0))
 
 /* TI CPP control */
 #define TICPPINTCTL_C62X		(0x3A400 + 0x138)
 /*
  * BIT(3) enables error detection and reporting on the ETR Parity Error.
  * BIT(2) enables error detection and reporting on the TI Parity Error.
  * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
  * BIT(0) enables error detection and reporting on the TI CPP Push interface.
  */
 #define TICPP_EN_C62X		\
 	(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
 
 /* CFC Uncorrectable Errors */
 #define CPP_CFC_ERR_CTRL_C62X	(0x30000 + 0xC00)
 /*
  * BIT(1) enables interrupt.
  * BIT(0) enables detecting and logging of push/pull data errors.
  */
 #define CPP_CFC_UE_C62X		(__BIT(1) | __BIT(0))
 
 /* Correctable SecureRAM Error Reg */
 #define SECRAMCERR_C62X			(0x3AC00 + 0x00)
 /* BIT(3) enables fixing and logging of correctable errors. */
 #define SECRAM_CERR_C62X		(__BIT(3))
 
 /* Uncorrectable SecureRAM Error Reg */
 /*
  * BIT(17) enables interrupt.
  * BIT(3) enables detecting and logging of uncorrectable errors.
  */
 #define SECRAM_UERR_C62X		(__BIT(17) | __BIT(3))
 
 /* Miscellaneous Memory Target Errors Register */
 /*
  * BIT(3) enables detecting and logging push/pull data errors.
  * BIT(2) enables interrupt.
  */
 #define TGT_UERR_C62X			(__BIT(3) | __BIT(2))
 
 
 #define SLICEPWRDOWN_C62X(i)	((i) * 0x4000 + 0x2C)
 /* Enabling PKE4-PKE0. */
 #define MMP_PWR_UP_MSK_C62X		\
 	(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
 
 /* CPM Uncorrectable Errors */
 #define INTMASKSSM_C62X(i)		((i) * 0x4000 + 0x0)
 /* Disabling interrupts for correctable errors. */
 #define INTMASKSSM_UERR_C62X	\
 	(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
 
 /* MMP */
 /* BIT(3) enables correction. */
 #define CERRSSMMMP_EN_C62X		(__BIT(3))
 
 /* BIT(3) enables logging. */
 #define UERRSSMMMP_EN_C62X		(__BIT(3))
 
 /* ETR */
 #define ETR_MAX_BANKS_C62X		16
 #define ETR_TX_RX_GAP_C62X		8
 #define ETR_TX_RINGS_MASK_C62X		0xFF
 #define ETR_BUNDLE_SIZE_C62X		0x1000
 
 /* AE firmware */
 #define AE_FW_PROD_TYPE_C62X		0x01000000
-#define AE_FW_MOF_NAME_C62X	"qat_c62x"
+#define AE_FW_MOF_NAME_C62X	"qat_c62xfw"
 #define AE_FW_MMP_NAME_C62X	"qat_c62x_mmp"
 #define AE_FW_UOF_NAME_C62X	"icp_qat_ae.suof"
 
 /* Clock frequency */
 #define CLOCK_PER_SEC_C62X		(685 * 1000000 / 16)
 
 #endif
Index: stable/12/sys/dev/qat/qat_d15xxreg.h
===================================================================
--- stable/12/sys/dev/qat/qat_d15xxreg.h	(revision 368303)
+++ stable/12/sys/dev/qat/qat_d15xxreg.h	(revision 368304)
@@ -1,201 +1,201 @@
 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
 /*	$NetBSD: qat_d15xxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
 
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
 /*
  *   Copyright(c) 2014 Intel Corporation.
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
  *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 /* $FreeBSD$ */
 
 #ifndef _DEV_PCI_QAT_D15XXREG_H_
 #define _DEV_PCI_QAT_D15XXREG_H_
 
 /* Max number of accelerators and engines */
 #define MAX_ACCEL_D15XX			5
 #define MAX_AE_D15XX			10
 
 /* PCIe BAR index */
 #define BAR_SRAM_ID_D15XX		0
 #define BAR_PMISC_ID_D15XX		1
 #define BAR_ETR_ID_D15XX		2
 
 /* BAR PMISC sub-regions */
 #define AE_OFFSET_D15XX			0x20000
 #define AE_LOCAL_OFFSET_D15XX		0x20800
 #define CAP_GLOBAL_OFFSET_D15XX		0x30000
 
 #define SOFTSTRAP_REG_D15XX			0x2EC
 #define SOFTSTRAP_SS_POWERGATE_CY_D15XX		__BIT(23)
 #define SOFTSTRAP_SS_POWERGATE_PKE_D15XX	__BIT(24)
 
 #define ACCEL_REG_OFFSET_D15XX		16
 #define ACCEL_MASK_D15XX		0x1F
 #define AE_MASK_D15XX			0x3FF
 
 #define SMIAPF0_D15XX			0x3A028
 #define SMIAPF1_D15XX			0x3A030
 #define SMIA0_MASK_D15XX		0xFFFF
 #define SMIA1_MASK_D15XX		0x1
 
 /* Error detection and correction */
 #define AE_CTX_ENABLES_D15XX(i)		((i) * 0x1000 + 0x20818)
 #define AE_MISC_CONTROL_D15XX(i)		((i) * 0x1000 + 0x20960)
 #define ENABLE_AE_ECC_ERR_D15XX		__BIT(28)
 #define ENABLE_AE_ECC_PARITY_CORR_D15XX	(__BIT(24) | __BIT(12))
 #define ERRSSMSH_EN_D15XX		__BIT(3)
 /* BIT(2) enables the logging of push/pull data errors. */
 #define PPERR_EN_D15XX			(__BIT(2))
 
 /* Mask for VF2PF interrupts */
 #define VF2PF1_16_D15XX			(0xFFFF << 9)
 #define ERRSOU3_VF2PF_D15XX(errsou3)	(((errsou3) & 0x01FFFE00) >> 9)
 #define ERRMSK3_VF2PF_D15XX(vf_mask)	(((vf_mask) & 0xFFFF) << 9)
 
 /* Masks for correctable error interrupts. */
 #define ERRMSK0_CERR_D15XX	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
 #define ERRMSK1_CERR_D15XX	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
 #define ERRMSK3_CERR_D15XX	(__BIT(7))
 #define ERRMSK4_CERR_D15XX	(__BIT(8) | __BIT(0))
 #define ERRMSK5_CERR_D15XX	(0)
 
 /* Masks for uncorrectable error interrupts. */
 #define ERRMSK0_UERR_D15XX	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
 #define ERRMSK1_UERR_D15XX	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
 #define ERRMSK3_UERR_D15XX	(__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
 				 __BIT(3) | __BIT(2) | __BIT(0))
 #define ERRMSK4_UERR_D15XX	(__BIT(9) | __BIT(1))
 #define ERRMSK5_UERR_D15XX	(__BIT(18) | __BIT(17) | __BIT(16))
 
 /* RI CPP control */
 #define RICPPINTCTL_D15XX		(0x3A000 + 0x110)
 /*
  * BIT(2) enables error detection and reporting on the RI Parity Error.
  * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
  * BIT(0) enables error detection and reporting on the RI CPP Push interface.
  */
 #define RICPP_EN_D15XX			(__BIT(2) | __BIT(1) | __BIT(0))
 
 /* TI CPP control */
 #define TICPPINTCTL_D15XX		(0x3A400 + 0x138)
 /*
  * BIT(3) enables error detection and reporting on the ETR Parity Error.
  * BIT(2) enables error detection and reporting on the TI Parity Error.
  * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
  * BIT(0) enables error detection and reporting on the TI CPP Push interface.
  */
 #define TICPP_EN_D15XX		\
 	(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
 
 /* CFC Uncorrectable Errors */
 #define CPP_CFC_ERR_CTRL_D15XX	(0x30000 + 0xC00)
 /*
  * BIT(1) enables interrupt.
  * BIT(0) enables detecting and logging of push/pull data errors.
  */
 #define CPP_CFC_UE_D15XX		(__BIT(1) | __BIT(0))
 
 /* Correctable SecureRAM Error Reg */
 #define SECRAMCERR_D15XX			(0x3AC00 + 0x00)
 /* BIT(3) enables fixing and logging of correctable errors. */
 #define SECRAM_CERR_D15XX		(__BIT(3))
 
 /* Uncorrectable SecureRAM Error Reg */
 /*
  * BIT(17) enables interrupt.
  * BIT(3) enables detecting and logging of uncorrectable errors.
  */
 #define SECRAM_UERR_D15XX		(__BIT(17) | __BIT(3))
 
 /* Miscellaneous Memory Target Errors Register */
 /*
  * BIT(3) enables detecting and logging push/pull data errors.
  * BIT(2) enables interrupt.
  */
 #define TGT_UERR_D15XX			(__BIT(3) | __BIT(2))
 
 
 #define SLICEPWRDOWN_D15XX(i)	((i) * 0x4000 + 0x2C)
 /* Enabling PKE4-PKE0. */
 #define MMP_PWR_UP_MSK_D15XX		\
 	(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
 
 /* CPM Uncorrectable Errors */
 #define INTMASKSSM_D15XX(i)		((i) * 0x4000 + 0x0)
 /* Disabling interrupts for correctable errors. */
 #define INTMASKSSM_UERR_D15XX	\
 	(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
 
 /* MMP */
 /* BIT(3) enables correction. */
 #define CERRSSMMMP_EN_D15XX		(__BIT(3))
 
 /* BIT(3) enables logging. */
 #define UERRSSMMMP_EN_D15XX		(__BIT(3))
 
 /* ETR */
 #define ETR_MAX_BANKS_D15XX		16
 #define ETR_TX_RX_GAP_D15XX		8
 #define ETR_TX_RINGS_MASK_D15XX		0xFF
 #define ETR_BUNDLE_SIZE_D15XX		0x1000
 
 /* AE firmware */
 #define AE_FW_PROD_TYPE_D15XX	0x01000000
-#define AE_FW_MOF_NAME_D15XX	"qat_d15xx"
+#define AE_FW_MOF_NAME_D15XX	"qat_d15xxfw"
 #define AE_FW_MMP_NAME_D15XX	"qat_d15xx_mmp"
 #define AE_FW_UOF_NAME_D15XX	"icp_qat_ae.suof"
 
 /* Clock frequency */
 #define CLOCK_PER_SEC_D15XX		(685 * 1000000 / 16)
 
 #endif
Index: stable/12/sys/dev/qat/qat_dh895xccreg.h
===================================================================
--- stable/12/sys/dev/qat/qat_dh895xccreg.h	(revision 368303)
+++ stable/12/sys/dev/qat/qat_dh895xccreg.h	(revision 368304)
@@ -1,119 +1,119 @@
 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
 
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
 /*
  *   Copyright(c) 2014-2020 Intel Corporation.
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
  *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 /* $FreeBSD$ */
 
 #ifndef _DEV_PCI_QAT_DH895XCCREG_H_
 #define _DEV_PCI_QAT_DH895XCCREG_H_
 
 /* Max number of accelerators and engines */
 #define MAX_ACCEL_DH895XCC		6
 #define MAX_AE_DH895XCC			12
 
 /* PCIe BAR index */
 #define BAR_SRAM_ID_DH895XCC		0
 #define BAR_PMISC_ID_DH895XCC		1
 #define BAR_ETR_ID_DH895XCC		2
 
 /* BAR PMISC sub-regions */
 #define AE_OFFSET_DH895XCC		0x20000
 #define AE_LOCAL_OFFSET_DH895XCC	0x20800
 #define CAP_GLOBAL_OFFSET_DH895XCC	0x30000
 
 #define SOFTSTRAP_REG_DH895XCC			0x2EC
 
 #define	FUSECTL_SKU_MASK_DH895XCC	0x300000
 #define	FUSECTL_SKU_SHIFT_DH895XCC	20
 #define	FUSECTL_SKU_1_DH895XCC		0
 #define	FUSECTL_SKU_2_DH895XCC		1
 #define	FUSECTL_SKU_3_DH895XCC		2
 #define	FUSECTL_SKU_4_DH895XCC		3
 
 #define ACCEL_REG_OFFSET_DH895XCC	13
 #define ACCEL_MASK_DH895XCC		0x3F
 #define AE_MASK_DH895XCC		0xFFF
 
 #define SMIAPF0_DH895XCC		0x3A028
 #define SMIAPF1_DH895XCC		0x3A030
 #define SMIA0_MASK_DH895XCC		0xFFFFFFFF
 #define SMIA1_MASK_DH895XCC		0x1
 
 /* Error detection and correction */
 #define AE_CTX_ENABLES_DH895XCC(i)	((i) * 0x1000 + 0x20818)
 #define AE_MISC_CONTROL_DH895XCC(i)	((i) * 0x1000 + 0x20960)
 #define ENABLE_AE_ECC_ERR_DH895XCC	__BIT(28)
 #define ENABLE_AE_ECC_PARITY_CORR_DH895XCC (__BIT(24) | __BIT(12))
 #define ERRSSMSH_EN_DH895XCC		__BIT(3)
 /* BIT(2) enables the logging of push/pull data errors. */
 #define PPERR_EN_DH895XCC		(__BIT(2))
 
 /* ETR */
 #define ETR_MAX_BANKS_DH895XCC		32
 #define ETR_TX_RX_GAP_DH895XCC		8
 #define ETR_TX_RINGS_MASK_DH895XCC	0xFF
 #define ETR_BUNDLE_SIZE_DH895XCC	0x1000
 
 /* AE firmware */
 #define AE_FW_PROD_TYPE_DH895XCC	0x00400000
-#define AE_FW_MOF_NAME_DH895XCC		"qat_895xcc"
+#define AE_FW_MOF_NAME_DH895XCC		"qat_895xccfw"
 #define AE_FW_MMP_NAME_DH895XCC		"qat_895xcc_mmp"
 #define AE_FW_UOF_NAME_DH895XCC		"icp_qat_ae.uof"
 
 /* Clock frequency */
 #define CLOCK_PER_SEC_DH895XCC		(685 * 1000000 / 16)
 
 #endif
Index: stable/12/sys/modules/qatfw/qat_c2xxx/Makefile
===================================================================
--- stable/12/sys/modules/qatfw/qat_c2xxx/Makefile	(revision 368303)
+++ stable/12/sys/modules/qatfw/qat_c2xxx/Makefile	(revision 368304)
@@ -1,11 +1,11 @@
 # $FreeBSD$
 
 .PATH: ${SRCTOP}/sys/contrib/dev/qat
 
 KMOD=	qat_c2xxxfw
 IMG1=	mmp_firmware_c2xxx
 IMG2=	mof_firmware_c2xxx
 
-FIRMWS=	${IMG1}.bin:${IMG1}:111 ${IMG2}.bin:${IMG2}:111
+FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
 
 .include <bsd.kmod.mk>
Index: stable/12/sys/modules/qatfw/qat_c3xxx/Makefile
===================================================================
--- stable/12/sys/modules/qatfw/qat_c3xxx/Makefile	(revision 368303)
+++ stable/12/sys/modules/qatfw/qat_c3xxx/Makefile	(revision 368304)
@@ -1,11 +1,11 @@
 # $FreeBSD$
 
 .PATH: ${SRCTOP}/sys/contrib/dev/qat
 
 KMOD=	qat_c3xxxfw
 IMG1=	qat_c3xxx
 IMG2=	qat_c3xxx_mmp
 
-FIRMWS=	${IMG1}.bin:${IMG1}:111 ${IMG2}.bin:${IMG2}:111
+FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
 
 .include <bsd.kmod.mk>
Index: stable/12/sys/modules/qatfw/qat_c62x/Makefile
===================================================================
--- stable/12/sys/modules/qatfw/qat_c62x/Makefile	(revision 368303)
+++ stable/12/sys/modules/qatfw/qat_c62x/Makefile	(revision 368304)
@@ -1,11 +1,11 @@
 # $FreeBSD$
 
 .PATH: ${SRCTOP}/sys/contrib/dev/qat
 
 KMOD=	qat_c62xfw
 IMG1=	qat_c62x
 IMG2=	qat_c62x_mmp
 
-FIRMWS=	${IMG1}.bin:${IMG1}:111 ${IMG2}.bin:${IMG2}:111
+FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
 
 .include <bsd.kmod.mk>
Index: stable/12/sys/modules/qatfw/qat_d15xx/Makefile
===================================================================
--- stable/12/sys/modules/qatfw/qat_d15xx/Makefile	(revision 368303)
+++ stable/12/sys/modules/qatfw/qat_d15xx/Makefile	(revision 368304)
@@ -1,11 +1,11 @@
 # $FreeBSD$
 
 .PATH: ${SRCTOP}/sys/contrib/dev/qat
 
 KMOD=	qat_d15xxfw
 IMG1=	qat_d15xx
 IMG2=	qat_d15xx_mmp
 
-FIRMWS=	${IMG1}.bin:${IMG1}:111 ${IMG2}.bin:${IMG2}:111
+FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
 
 .include <bsd.kmod.mk>
Index: stable/12/sys/modules/qatfw/qat_dh895xcc/Makefile
===================================================================
--- stable/12/sys/modules/qatfw/qat_dh895xcc/Makefile	(revision 368303)
+++ stable/12/sys/modules/qatfw/qat_dh895xcc/Makefile	(revision 368304)
@@ -1,11 +1,11 @@
 # $FreeBSD$
 
 .PATH: ${SRCTOP}/sys/contrib/dev/qat
 
 KMOD=	qat_dh895xccfw
 IMG1=	qat_895xcc
 IMG2=	qat_895xcc_mmp
 
-FIRMWS=	${IMG1}.bin:${IMG1}:111 ${IMG2}.bin:${IMG2}:111
+FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
 
 .include <bsd.kmod.mk>
Index: stable/12
===================================================================
--- stable/12	(revision 368303)
+++ stable/12	(revision 368304)

Property changes on: stable/12
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head:r368193