Index: head/sys/arm/arm/cpufunc_asm_sheeva.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_sheeva.S (revision 368153) +++ head/sys/arm/arm/cpufunc_asm_sheeva.S (nonexistent) @@ -1,424 +0,0 @@ -/*- - * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. - * All rights reserved. - * - * Developed by Semihalf. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of MARVELL nor the names of contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include - -#ifndef ELF_TRAMPOLINE -.Lsheeva_cache_line_size: - .word _C_LABEL(arm_pdcache_line_size) -.Lsheeva_asm_page_mask: - .word _C_LABEL(PAGE_MASK) - -ENTRY(sheeva_setttb) - /* Disable irqs */ - mrs r2, cpsr - orr r3, r2, #PSR_I | PSR_F - msr cpsr_c, r3 - - mov r1, #0 - mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */ -1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ - bne 1b /* More to do? */ - - mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */ - mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */ - - /* Reenable irqs */ - msr cpsr_c, r2 - - mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ - - mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ - - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ - RET -END(sheeva_setttb) - -ENTRY(sheeva_dcache_wbinv_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ - mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - add r0, r0, ip - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_dcache_wbinv_range) - -ENTRY(sheeva_idcache_wbinv_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ - mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - /* Invalidate and clean icache line by line */ - ldr r3, .Lsheeva_cache_line_size - ldr r3, [r3] -2: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, r3 - cmp r2, r0 - bhi 2b - - add r0, r2, #1 - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_idcache_wbinv_range) - -ENTRY(sheeva_dcache_inv_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */ - mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - add r0, r0, ip - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_dcache_inv_range) - -ENTRY(sheeva_dcache_wb_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 5, r0, c15, c13, 0 /* Clean zone start address */ - mcr p15, 5, r2, c15, c13, 1 /* Clean zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - add r0, r0, ip - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_dcache_wb_range) - -ENTRY(sheeva_l2cache_wbinv_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */ - mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */ - mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */ - mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - add r0, r0, ip - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_l2cache_wbinv_range) - -ENTRY(sheeva_l2cache_inv_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */ - mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - add r0, r0, ip - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_l2cache_inv_range) - -ENTRY(sheeva_l2cache_wb_range) - str lr, [sp, #-4]! - mrs lr, cpsr - /* Start with cache line aligned address */ - ldr ip, .Lsheeva_cache_line_size - ldr ip, [ip] - sub ip, ip, #1 - and r2, r0, ip - add r1, r1, r2 - add r1, r1, ip - bics r1, r1, ip - bics r0, r0, ip - - ldr ip, .Lsheeva_asm_page_mask - and r2, r0, ip - rsb r2, r2, #PAGE_SIZE - cmp r1, r2 - movcc ip, r1 - movcs ip, r2 -1: - add r3, r0, ip - sub r2, r3, #1 - /* Disable irqs */ - orr r3, lr, #PSR_I | PSR_F - msr cpsr_c, r3 - mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */ - mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */ - /* Enable irqs */ - msr cpsr_c, lr - - add r0, r0, ip - sub r1, r1, ip - cmp r1, #PAGE_SIZE - movcc ip, r1 - movcs ip, #PAGE_SIZE - cmp r1, #0 - bne 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - ldr lr, [sp], #4 - RET -END(sheeva_l2cache_wb_range) -#endif /* !ELF_TRAMPOLINE */ - -ENTRY(sheeva_l2cache_wbinv_all) - /* Disable irqs */ - mrs r1, cpsr - orr r2, r1, #PSR_I | PSR_F - msr cpsr_c, r2 - - mov r0, #0 - mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */ - mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */ - - msr cpsr_c, r1 /* Reenable irqs */ - - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(sheeva_l2cache_wbinv_all) - -#ifndef ELF_TRAMPOLINE -/* This function modifies register value as follows: - * - * arg1 arg EFFECT (bit value saved into register) - * 0 0 not changed - * 0 1 negated - * 1 0 cleared - * 1 1 set - */ -ENTRY(sheeva_control_ext) - mrc p15, 1, r3, c15, c1, 0 /* Read the control register */ - bic r2, r3, r0 /* Clear bits */ - eor r2, r2, r1 /* XOR bits */ - - teq r2, r3 /* Only write if there is a change */ - mcrne p15, 1, r2, c15, c1, 0 /* Write new control register */ - mov r0, r3 /* Return old value */ - RET -END(sheeva_control_ext) - -ENTRY(sheeva_cpu_sleep) - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ - mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */ - mov pc, lr -END(sheeva_cpu_sleep) -#endif /* !ELF_TRAMPOLINE */ Property changes on: head/sys/arm/arm/cpufunc_asm_sheeva.S ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/arm/cpufunc_asm_armv5_ec.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_armv5_ec.S (revision 368153) +++ head/sys/arm/arm/cpufunc_asm_armv5_ec.S (nonexistent) @@ -1,217 +0,0 @@ -/* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.1 2007/01/06 00:50:54 christos Exp $ */ - -/* - * Copyright (c) 2002, 2005 ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARMv5 assembly functions for manipulating caches. - * These routines can be used by any core that supports both the set/index - * operations and the test and clean operations for efficiently cleaning the - * entire DCache. If a core does not have the test and clean operations, but - * does have the set/index operations, use the routines in cpufunc_asm_armv5.S. - * This source was derived from that file. - */ - -#include -__FBSDID("$FreeBSD$"); - -#ifndef ELF_TRAMPOLINE -/* - * Functions to set the MMU Translation Table Base register - * - * We need to clean and flush the cache as it uses virtual - * addresses that are about to change. - */ -ENTRY(armv5_ec_setttb) - /* - * Some other ARM ports save registers on the stack, call the - * idcache_wbinv_all function and then restore the registers from the - * stack before setting the TTB. I observed that this caused a - * problem when the old and new translation table entries' buffering - * bits were different. If I saved the registers in other registers - * or invalidated the caches when I returned from idcache_wbinv_all, - * it worked fine. If not, I ended up executing at an invalid PC. - * For armv5_ec_settb, the idcache_wbinv_all is simple enough, I just - * do it directly and entirely avoid the problem. - */ - mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ -1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ - bne 1b /* More to do? */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - - mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ - - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ - RET -END(armv5_ec_setttb) - -/* - * Cache operations. For the entire cache we use the enhanced cache - * operations. - */ - -ENTRY_NP(armv5_ec_icache_sync_range) - ldr ip, .Larmv5_ec_line_size - cmp r1, #0x4000 - bcs .Larmv5_ec_icache_sync_all - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -1: - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET - -.Larmv5_ec_icache_sync_all: - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache cleaning code. - */ - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - /* Fall through to clean Dcache. */ - -.Larmv5_ec_dcache_wb: -1: - mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */ - bne 1b /* More to do? */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv5_ec_icache_sync_range) - -.Larmv5_ec_line_size: - .word _C_LABEL(arm_pdcache_line_size) - -ENTRY(armv5_ec_dcache_wb_range) - ldr ip, .Larmv5_ec_line_size - cmp r1, #0x4000 - bcs .Larmv5_ec_dcache_wb - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -1: - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv5_ec_dcache_wb_range) - -ENTRY(armv5_ec_dcache_wbinv_range) - ldr ip, .Larmv5_ec_line_size - cmp r1, #0x4000 - bcs .Larmv5_ec_dcache_wbinv_all - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -1: - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv5_ec_dcache_wbinv_range) - -/* - * Note, we must not invalidate everything. If the range is too big we - * must use wb-inv of the entire cache. - */ -ENTRY(armv5_ec_dcache_inv_range) - ldr ip, .Larmv5_ec_line_size - cmp r1, #0x4000 - bcs .Larmv5_ec_dcache_wbinv_all - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -1: - mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv5_ec_dcache_inv_range) - -ENTRY(armv5_ec_idcache_wbinv_range) - ldr ip, .Larmv5_ec_line_size - cmp r1, #0x4000 - bcs .Larmv5_ec_idcache_wbinv_all - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -1: - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv5_ec_idcache_wbinv_range) -#endif /* !ELF_TRAMPOLINE */ - -ENTRY_NP(armv5_ec_idcache_wbinv_all) -.Larmv5_ec_idcache_wbinv_all: - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache purging code. - */ - mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ - /* Fall through to purge Dcache. */ -END(armv5_ec_idcache_wbinv_all) - -#ifndef ELF_TRAMPOLINE -ENTRY(armv5_ec_dcache_wbinv_all) -.Larmv5_ec_dcache_wbinv_all: -1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ - bne 1b /* More to do? */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv5_ec_dcache_wbinv_all) -#endif Property changes on: head/sys/arm/arm/cpufunc_asm_armv5_ec.S ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/arm/arm/cpufunc_asm_armv4.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_armv4.S (revision 368153) +++ head/sys/arm/arm/cpufunc_asm_armv4.S (nonexistent) @@ -1,74 +0,0 @@ -/* $NetBSD: cpufunc_asm_armv4.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */ - -/*- - * Copyright (c) 2001 ARM Limited - * Copyright (c) 1997,1998 Mark Brinicombe. - * Copyright (c) 1997 Causality Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Causality Limited. - * 4. The name of Causality Limited may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARM9 assembly functions for CPU / MMU / TLB specific operations - * - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * TLB functions - */ -ENTRY(armv4_tlb_flushID) - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ - RET -END(armv4_tlb_flushID) - -ENTRY(armv4_tlb_flushD) - mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ - RET -END(armv4_tlb_flushD) - -ENTRY(armv4_tlb_flushD_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - RET -END(armv4_tlb_flushD_SE) - -/* - * Other functions - */ -ENTRY(armv4_drain_writebuf) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - RET -END(armv4_drain_writebuf) - -ENTRY(armv4_idcache_inv_all) - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */ - RET -END(armv4_idcache_inv_all) - Property changes on: head/sys/arm/arm/cpufunc_asm_armv4.S ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/arm/arm/cpufunc_asm_arm9.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_arm9.S (revision 368153) +++ head/sys/arm/arm/cpufunc_asm_arm9.S (nonexistent) @@ -1,69 +0,0 @@ -/* $NetBSD: cpufunc_asm_arm9.S,v 1.3 2004/01/26 15:54:16 rearnsha Exp $ */ - -/* - * Copyright (c) 2001, 2004 ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARM9 assembly functions for CPU / MMU / TLB specific operations - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * TLB functions - */ -ENTRY(arm9_tlb_flushID_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ - mov pc, lr -END(arm9_tlb_flushID_SE) - -/* - * Context switch. - * - * These is the CPU-specific parts of the context switcher cpu_switch() - * These functions actually perform the TTB reload. - * - * NOTE: Special calling convention - * r1, r4-r13 must be preserved - */ -ENTRY(arm9_context_switch) - /* - * We can assume that the caches will only contain kernel addresses - * at this point. So no need to flush them again. - */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ - - /* Paranoia -- make sure the pipeline is empty. */ - nop - nop - nop - mov pc, lr -END(arm9_context_switch) Property changes on: head/sys/arm/arm/cpufunc_asm_arm9.S ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/arm/arm/cpufunc.c =================================================================== --- head/sys/arm/arm/cpufunc.c (revision 368153) +++ head/sys/arm/arm/cpufunc.c (revision 368154) @@ -1,586 +1,407 @@ /* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */ /*- * SPDX-License-Identifier: BSD-4-Clause * * arm9 support code Copyright (C) 2001 ARM Ltd * Copyright (c) 1997 Mark Brinicombe. * Copyright (c) 1997 Causality Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Causality Limited. * 4. The name of Causality Limited may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * cpufuncs.c * * C functions for supporting CPU / MMU / TLB specific operations. * * Created : 30/01/97 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include /* PRIMARY CACHE VARIABLES */ int arm_picache_size; int arm_picache_line_size; int arm_picache_ways; int arm_pdcache_size; /* and unified */ int arm_pdcache_line_size; int arm_pdcache_ways; int arm_pcache_type; int arm_pcache_unified; int arm_dcache_align; int arm_dcache_align_mask; u_int arm_cache_level; u_int arm_cache_type[14]; u_int arm_cache_loc; -#if defined(CPU_ARM9E) -static void arm10_setup(void); -#endif #ifdef CPU_MV_PJ4B static void pj4bv7_setup(void); #endif #if defined(CPU_ARM1176) static void arm11x6_setup(void); #endif #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) static void cortexa_setup(void); #endif -#if defined(CPU_ARM9E) -struct cpu_functions armv5_ec_cpufuncs = { - /* CPU functions */ - - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - armv5_ec_setttb, /* Setttb */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - arm9_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - armv5_ec_icache_sync_range, /* icache_sync_range */ - - armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ - armv5_ec_dcache_wbinv_range, /* dcache_wbinv_range */ - armv5_ec_dcache_inv_range, /* dcache_inv_range */ - armv5_ec_dcache_wb_range, /* dcache_wb_range */ - - armv4_idcache_inv_all, /* idcache_inv_all */ - armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ - armv5_ec_idcache_wbinv_range, /* idcache_wbinv_range */ - - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ - - /* Other functions */ - - armv4_drain_writebuf, /* drain_writebuf */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - arm9_context_switch, /* context_switch */ - - arm10_setup /* cpu setup */ - -}; - -struct cpu_functions sheeva_cpufuncs = { - /* CPU functions */ - - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - sheeva_setttb, /* Setttb */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - arm9_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - armv5_ec_icache_sync_range, /* icache_sync_range */ - - armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ - sheeva_dcache_wbinv_range, /* dcache_wbinv_range */ - sheeva_dcache_inv_range, /* dcache_inv_range */ - sheeva_dcache_wb_range, /* dcache_wb_range */ - - armv4_idcache_inv_all, /* idcache_inv_all */ - armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ - sheeva_idcache_wbinv_range, /* idcache_wbinv_all */ - - sheeva_l2cache_wbinv_all, /* l2cache_wbinv_all */ - sheeva_l2cache_wbinv_range, /* l2cache_wbinv_range */ - sheeva_l2cache_inv_range, /* l2cache_inv_range */ - sheeva_l2cache_wb_range, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ - - /* Other functions */ - - armv4_drain_writebuf, /* drain_writebuf */ - - sheeva_cpu_sleep, /* sleep */ - - /* Soft functions */ - - arm9_context_switch, /* context_switch */ - - arm10_setup /* cpu setup */ -}; -#endif /* CPU_ARM9E */ - #ifdef CPU_MV_PJ4B struct cpu_functions pj4bv7_cpufuncs = { /* Cache operations */ .cf_l2cache_wbinv_all = (void *)cpufunc_nullop, .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, .cf_l2cache_inv_range = (void *)cpufunc_nullop, .cf_l2cache_wb_range = (void *)cpufunc_nullop, .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, /* Other functions */ .cf_sleep = (void *)cpufunc_nullop, /* Soft functions */ .cf_setup = pj4bv7_setup }; #endif /* CPU_MV_PJ4B */ #if defined(CPU_ARM1176) struct cpu_functions arm1176_cpufuncs = { /* Cache operations */ .cf_l2cache_wbinv_all = (void *)cpufunc_nullop, .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, .cf_l2cache_inv_range = (void *)cpufunc_nullop, .cf_l2cache_wb_range = (void *)cpufunc_nullop, .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, /* Other functions */ .cf_sleep = arm11x6_sleep, /* Soft functions */ .cf_setup = arm11x6_setup }; #endif /*CPU_ARM1176 */ #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) struct cpu_functions cortexa_cpufuncs = { /* Cache operations */ /* * Note: For CPUs using the PL310 the L2 ops are filled in when the * L2 cache controller is actually enabled. */ .cf_l2cache_wbinv_all = cpufunc_nullop, .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, .cf_l2cache_inv_range = (void *)cpufunc_nullop, .cf_l2cache_wb_range = (void *)cpufunc_nullop, .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, /* Other functions */ .cf_sleep = armv7_cpu_sleep, /* Soft functions */ .cf_setup = cortexa_setup }; #endif /* CPU_CORTEXA || CPU_KRAIT */ /* * Global constants also used by locore.s */ struct cpu_functions cpufuncs; u_int cputype; -#if defined (CPU_ARM9E) || \ - defined(CPU_ARM1176) || \ - defined(CPU_MV_PJ4B) || \ - defined(CPU_CORTEXA) || defined(CPU_KRAIT) - static void get_cachetype_cp15(void); /* Additional cache information local to this file. Log2 of some of the above numbers. */ static int arm_dcache_l2_nsets; static int arm_dcache_l2_assoc; static int arm_dcache_l2_linesize; static void get_cachetype_cp15(void) { u_int ctype, isize, dsize, cpuid; u_int clevel, csize, i, sel; u_int multiplier; u_char type; ctype = cp15_ctr_get(); cpuid = cp15_midr_get(); /* * ...and thus spake the ARM ARM: * * If an value corresponding to an unimplemented or * reserved ID register is encountered, the System Control * processor returns the value of the main ID register. */ if (ctype == cpuid) goto out; if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) { __asm __volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (clevel)); arm_cache_level = clevel; arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level); i = 0; while ((type = (clevel & 0x7)) && i < 7) { if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || type == CACHE_SEP_CACHE) { sel = i << 1; __asm __volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (sel)); __asm __volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csize)); arm_cache_type[sel] = csize; arm_dcache_align = 1 << (CPUV7_CT_xSIZE_LEN(csize) + 4); arm_dcache_align_mask = arm_dcache_align - 1; } if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { sel = (i << 1) | 1; __asm __volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (sel)); __asm __volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csize)); arm_cache_type[sel] = csize; } i++; clevel >>= 3; } } else { if ((ctype & CPU_CT_S) == 0) arm_pcache_unified = 1; /* * If you want to know how this code works, go read the ARM ARM. */ arm_pcache_type = CPU_CT_CTYPE(ctype); if (arm_pcache_unified == 0) { isize = CPU_CT_ISIZE(ctype); multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); if (CPU_CT_xSIZE_ASSOC(isize) == 0) { if (isize & CPU_CT_xSIZE_M) arm_picache_line_size = 0; /* not present */ else arm_picache_ways = 1; } else { arm_picache_ways = multiplier << (CPU_CT_xSIZE_ASSOC(isize) - 1); } arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); } dsize = CPU_CT_DSIZE(ctype); multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { if (dsize & CPU_CT_xSIZE_M) arm_pdcache_line_size = 0; /* not present */ else arm_pdcache_ways = 1; } else { arm_pdcache_ways = multiplier << (CPU_CT_xSIZE_ASSOC(dsize) - 1); } arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); arm_dcache_align = arm_pdcache_line_size; arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2; arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3; arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) - CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize); out: arm_dcache_align_mask = arm_dcache_align - 1; } } -#endif /* ARM9 || XSCALE */ /* * Cannot panic here as we may not have a console yet ... */ int set_cpufuncs(void) { cputype = cp15_midr_get(); cputype &= CPU_ID_CPU_MASK; -#if defined(CPU_ARM9E) - if (cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD || - cputype == CPU_ID_MV88FR571_41) { - uint32_t sheeva_ctrl; - - sheeva_ctrl = (MV_DC_STREAM_ENABLE | MV_BTB_DISABLE | - MV_L2_ENABLE); - /* - * Workaround for Marvell MV78100 CPU: Cache prefetch - * mechanism may affect the cache coherency validity, - * so it needs to be disabled. - * - * Refer to errata document MV-S501058-00C.pdf (p. 3.1 - * L2 Prefetching Mechanism) for details. - */ - if (cputype == CPU_ID_MV88FR571_VD || - cputype == CPU_ID_MV88FR571_41) - sheeva_ctrl |= MV_L2_PREFETCH_DISABLE; - - sheeva_control_ext(0xffffffff & ~MV_WA_ENABLE, sheeva_ctrl); - - cpufuncs = sheeva_cpufuncs; - get_cachetype_cp15(); - pmap_pte_init_generic(); - goto out; - } else if (cputype == CPU_ID_ARM926EJS) { - cpufuncs = armv5_ec_cpufuncs; - get_cachetype_cp15(); - pmap_pte_init_generic(); - goto out; - } -#endif /* CPU_ARM9E */ #if defined(CPU_ARM1176) if (cputype == CPU_ID_ARM1176JZS) { cpufuncs = arm1176_cpufuncs; get_cachetype_cp15(); goto out; } #endif /* CPU_ARM1176 */ #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) switch(cputype & CPU_ID_SCHEME_MASK) { case CPU_ID_CORTEXA5: case CPU_ID_CORTEXA7: case CPU_ID_CORTEXA8: case CPU_ID_CORTEXA9: case CPU_ID_CORTEXA12: case CPU_ID_CORTEXA15: case CPU_ID_CORTEXA53: case CPU_ID_CORTEXA57: case CPU_ID_CORTEXA72: case CPU_ID_KRAIT300: cpufuncs = cortexa_cpufuncs; get_cachetype_cp15(); goto out; default: break; } #endif /* CPU_CORTEXA || CPU_KRAIT */ #if defined(CPU_MV_PJ4B) if (cputype == CPU_ID_MV88SV581X_V7 || cputype == CPU_ID_MV88SV584X_V7 || cputype == CPU_ID_ARM_88SV581X_V7) { cpufuncs = pj4bv7_cpufuncs; get_cachetype_cp15(); goto out; } #endif /* CPU_MV_PJ4B */ /* * Bzzzz. And the answer was ... */ panic("No support for this CPU type (%08x) in kernel", cputype); return(ARCHITECTURE_NOT_PRESENT); out: uma_set_align(arm_dcache_align_mask); return (0); } /* * CPU Setup code */ -#if defined(CPU_ARM9E) -static void -arm10_setup(void) -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_BPRD_ENABLE - | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; - -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Now really make sure they are clean. */ - __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); - - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - - /* Set the control register */ - cpu_control(0xffffffff, cpuctrl); - - /* And again. */ - cpu_idcache_wbinv_all(); -} -#endif /* CPU_ARM9E || CPU_ARM10 */ #if defined(CPU_ARM1176) \ || defined(CPU_MV_PJ4B) \ || defined(CPU_CORTEXA) || defined(CPU_KRAIT) static __inline void cpu_scc_setup_ccnt(void) { /* This is how you give userland access to the CCNT and PMCn * registers. * BEWARE! This gives write access also, which may not be what * you want! */ #ifdef _PMC_USER_READ_WRITE_ /* Set PMUSERENR[0] to allow userland access */ cp15_pmuserenr_set(1); #endif #if defined(CPU_ARM1176) /* Set PMCR[2,0] to enable counters and reset CCNT */ cp15_pmcr_set(5); #else /* Set up the PMCCNTR register as a cyclecounter: * Set PMINTENCLR to 0xFFFFFFFF to block interrupts * Set PMCR[2,0] to enable counters and reset CCNT * Set PMCNTENSET to 0x80000000 to enable CCNT */ cp15_pminten_clr(0xFFFFFFFF); cp15_pmcr_set(5); cp15_pmcnten_set(0x80000000); #endif } #endif #if defined(CPU_ARM1176) static void arm11x6_setup(void) { uint32_t auxctrl, auxctrl_wax; uint32_t tmp, tmp2; uint32_t cpuid; cpuid = cp15_midr_get(); auxctrl = 0; auxctrl_wax = ~0; /* * Enable an errata workaround */ if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1176JZS) { /* ARM1176JZSr0 */ auxctrl = ARM1176_AUXCTL_PHD; auxctrl_wax = ~ARM1176_AUXCTL_PHD; } tmp = cp15_actlr_get(); tmp2 = tmp; tmp &= auxctrl_wax; tmp |= auxctrl; if (tmp != tmp2) cp15_actlr_set(tmp); cpu_scc_setup_ccnt(); } #endif /* CPU_ARM1176 */ #ifdef CPU_MV_PJ4B static void pj4bv7_setup(void) { pj4b_config(); cpu_scc_setup_ccnt(); } #endif /* CPU_MV_PJ4B */ #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) static void cortexa_setup(void) { cpu_scc_setup_ccnt(); } #endif /* CPU_CORTEXA || CPU_KRAIT */ Index: head/sys/arm/include/cpufunc.h =================================================================== --- head/sys/arm/include/cpufunc.h (revision 368153) +++ head/sys/arm/include/cpufunc.h (revision 368154) @@ -1,312 +1,275 @@ /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 1997 Mark Brinicombe. * Copyright (c) 1997 Causality Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Causality Limited. * 4. The name of Causality Limited may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * cpufunc.h * * Prototypes for cpu, mmu and tlb related functions. * * $FreeBSD$ */ #ifndef _MACHINE_CPUFUNC_H_ #define _MACHINE_CPUFUNC_H_ #ifdef _KERNEL #include #include static __inline void breakpoint(void) { __asm("udf 0xffff"); } struct cpu_functions { /* CPU functions */ void (*cf_l2cache_wbinv_all) (void); void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); void (*cf_l2cache_drain_writebuf) (void); /* Other functions */ void (*cf_sleep) (int mode); void (*cf_setup) (void); }; extern struct cpu_functions cpufuncs; extern u_int cputype; #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() #define cpu_sleep(m) cpufuncs.cf_sleep(m) #define cpu_setup() cpufuncs.cf_setup() int set_cpufuncs (void); #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ void cpufunc_nullop (void); u_int cpufunc_control (u_int clear, u_int bic); void cpu_domains (u_int domains); -#if defined(CPU_ARM9E) -void arm9_tlb_flushID_SE (u_int va); -void arm9_context_switch (void); -u_int sheeva_control_ext (u_int, u_int); -void sheeva_cpu_sleep (int); -void sheeva_setttb (u_int); -void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); -void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); -void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); -void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); - -void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); -void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); -void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); -void sheeva_l2cache_wbinv_all (void); -#endif - #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) void armv7_cpu_sleep (int); #endif #if defined(CPU_MV_PJ4B) void pj4b_config (void); #endif #if defined(CPU_ARM1176) void arm11x6_sleep (int); /* no ref. for errata */ #endif -#if defined(CPU_ARM9E) -void armv5_ec_setttb(u_int); - -void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); - -void armv5_ec_dcache_wbinv_all(void); -void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); -void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); -void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); - -void armv5_ec_idcache_wbinv_all(void); -void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); - -void armv4_tlb_flushID (void); -void armv4_tlb_flushD (void); -void armv4_tlb_flushD_SE (u_int va); - -void armv4_drain_writebuf (void); -void armv4_idcache_inv_all (void); -#endif /* * Macros for manipulating CPU interrupts */ #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) static __inline uint32_t __set_cpsr(uint32_t bic, uint32_t eor) { uint32_t tmp, ret; __asm __volatile( "mrs %0, cpsr\n" /* Get the CPSR */ "bic %1, %0, %2\n" /* Clear bits */ "eor %1, %1, %3\n" /* XOR bits */ "msr cpsr_xc, %1\n" /* Set the CPSR */ : "=&r" (ret), "=&r" (tmp) : "r" (bic), "r" (eor) : "memory"); return ret; } static __inline uint32_t disable_interrupts(uint32_t mask) { return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); } static __inline uint32_t enable_interrupts(uint32_t mask) { return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); } static __inline uint32_t restore_interrupts(uint32_t old_cpsr) { return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); } static __inline register_t intr_disable(void) { return (disable_interrupts(PSR_I | PSR_F)); } static __inline void intr_restore(register_t s) { restore_interrupts(s); } #undef __ARM_INTR_BITS /* * Functions to manipulate cpu r13 * (in arm/arm32/setstack.S) */ void set_stackptr (u_int mode, u_int address); u_int get_stackptr (u_int mode); /* * CPU functions from locore.S */ void cpu_reset (void) __attribute__((__noreturn__)); /* * Cache info variables. */ /* PRIMARY CACHE VARIABLES */ extern int arm_picache_size; extern int arm_picache_line_size; extern int arm_picache_ways; extern int arm_pdcache_size; /* and unified */ extern int arm_pdcache_line_size; extern int arm_pdcache_ways; extern int arm_pcache_type; extern int arm_pcache_unified; extern int arm_dcache_align; extern int arm_dcache_align_mask; extern u_int arm_cache_level; extern u_int arm_cache_loc; extern u_int arm_cache_type[14]; #define HAVE_INLINE_FFS static __inline __pure2 int ffs(int mask) { return (__builtin_ffs(mask)); } #define HAVE_INLINE_FFSL static __inline __pure2 int ffsl(long mask) { return (__builtin_ffsl(mask)); } #define HAVE_INLINE_FFSLL static __inline __pure2 int ffsll(long long mask) { return (__builtin_ffsll(mask)); } #define HAVE_INLINE_FLS static __inline __pure2 int fls(int mask) { return (mask == 0 ? 0 : 8 * sizeof(mask) - __builtin_clz((u_int)mask)); } #define HAVE_INLINE_FLSL static __inline __pure2 int flsl(long mask) { return (mask == 0 ? 0 : 8 * sizeof(mask) - __builtin_clzl((u_long)mask)); } #define HAVE_INLINE_FLSLL static __inline __pure2 int flsll(long long mask) { return (mask == 0 ? 0 : 8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask)); } #else /* !_KERNEL */ static __inline void breakpoint(void) { /* * This matches the instruction used by GDB for software * breakpoints. */ __asm("udf 0xfdee"); } #endif /* _KERNEL */ #endif /* _MACHINE_CPUFUNC_H_ */ /* End of cpufunc.h */ Index: head/sys/arm/include/md_var.h =================================================================== --- head/sys/arm/include/md_var.h (revision 368153) +++ head/sys/arm/include/md_var.h (revision 368154) @@ -1,77 +1,71 @@ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1995 Bruce D. Evans. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the author nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: FreeBSD: src/sys/i386/include/md_var.h,v 1.40 2001/07/12 * $FreeBSD$ */ #ifndef _MACHINE_MD_VAR_H_ #define _MACHINE_MD_VAR_H_ extern long Maxmem; extern char sigcode[]; extern int szsigcode; extern u_long elf_hwcap; extern u_long elf_hwcap2; extern vm_paddr_t arm_physmem_kernaddr; extern int (*_arm_memcpy)(void *, void *, int, int); extern int (*_arm_bzero)(void *, int, int); extern int _min_memcpy_size; extern int _min_bzero_size; #define DST_IS_USER 0x1 #define SRC_IS_USER 0x2 #define IS_PHYSICAL 0x4 enum cpu_class { CPU_CLASS_NONE, - CPU_CLASS_ARM9TDMI, - CPU_CLASS_ARM9ES, - CPU_CLASS_ARM9EJS, - CPU_CLASS_ARM10E, - CPU_CLASS_ARM10EJ, CPU_CLASS_CORTEXA, CPU_CLASS_KRAIT, - CPU_CLASS_XSCALE, CPU_CLASS_ARM11J, CPU_CLASS_MARVELL }; extern enum cpu_class cpu_class; struct dumperinfo; extern int busdma_swi_pending; void busdma_swi(void); int minidumpsys(struct dumperinfo *); extern uint32_t initial_fpscr; #endif /* !_MACHINE_MD_VAR_H_ */ Index: head/sys/arm/mv/std.mv =================================================================== --- head/sys/arm/mv/std.mv (revision 368153) +++ head/sys/arm/mv/std.mv (nonexistent) @@ -1,7 +0,0 @@ -# $FreeBSD$ - -files "../mv/files.mv" -cpu CPU_ARM9E -machine arm -makeoptions CONF_CFLAGS="-march=armv5te" -options FREEBSD_BOOT_LOADER Property changes on: head/sys/arm/mv/std.mv ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/conf/files.arm =================================================================== --- head/sys/conf/files.arm (revision 368153) +++ head/sys/conf/files.arm (revision 368154) @@ -1,158 +1,154 @@ # $FreeBSD$ arm/arm/autoconf.c standard arm/arm/bcopy_page.S standard arm/arm/bcopyinout.S standard arm/arm/blockio.S standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_base.c optional fdt arm/arm/bus_space_generic.c standard arm/arm/busdma_machdep.c standard arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard -arm/arm/cpufunc_asm_arm9.S optional cpu_arm9e arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 -arm/arm/cpufunc_asm_armv4.S optional cpu_arm9e -arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b -arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S standard arm/arm/db_disasm.c optional ddb arm/arm/db_interface.c optional ddb arm/arm/db_trace.c optional ddb arm/arm/debug_monitor.c optional ddb armv6 arm/arm/debug_monitor.c optional ddb armv7 arm/arm/disassem.c optional ddb arm/arm/dump_machdep.c standard arm/arm/elf_machdep.c standard arm/arm/elf_note.S standard arm/arm/exception.S standard arm/arm/fiq.c standard arm/arm/fiq_subr.S standard arm/arm/fusu.S standard arm/arm/gdb_machdep.c optional gdb arm/arm/generic_timer.c optional generic_timer arm/arm/gic.c optional gic arm/arm/gic_fdt.c optional gic fdt arm/arm/identcpu-v6.c standard arm/arm/in_cksum.c optional inet | inet6 arm/arm/in_cksum_arm.S optional inet | inet6 kern/subr_intr.c standard arm/arm/locore.S standard no-obj arm/arm/hypervisor-stub.S standard arm/arm/machdep.c standard arm/arm/machdep_boot.c standard arm/arm/machdep_kdb.c standard arm/arm/machdep_intr.c standard arm/arm/machdep_ptrace.c standard arm/arm/mem.c optional mem arm/arm/minidump_machdep.c standard arm/arm/mp_machdep.c optional smp arm/arm/mpcore_timer.c optional mpcore_timer arm/arm/nexus.c standard arm/arm/ofw_machdep.c optional fdt arm/arm/pl190.c optional pl190 arm/arm/pl310.c optional pl310 arm/arm/platform.c optional platform arm/arm/platform_if.m optional platform arm/arm/platform_pl310_if.m optional platform pl310 arm/arm/pmap-v6.c standard arm/arm/pmu.c optional pmu | fdt hwpmc arm/arm/ptrace_machdep.c standard arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.s standard arm/arm/stack_machdep.c optional ddb | stack arm/arm/stdatomic.c standard \ compile-with "${NORMAL_C:N-Wmissing-prototypes}" arm/arm/support.S standard arm/arm/swtch.S standard arm/arm/swtch-v6.S standard arm/arm/sys_machdep.c standard arm/arm/syscall.c standard arm/arm/trap-v6.c standard arm/arm/uio_machdep.c standard arm/arm/undefined.c standard arm/arm/unwind.c optional ddb | kdtrace_hooks | stack arm/arm/vm_machdep.c standard arm/arm/vfp.c standard arm/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 cddl/compat/opensolaris/kern/opensolaris_atomic.c optional !armv7 !armv6 zfs | !armv7 !armv6 dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/arm/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/arm/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/arm/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" crypto/des/des_enc.c optional netsmb dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/dwc/if_dwc.c optional dwc dev/dwc/if_dwc_if.m optional dwc dev/fb/fb.c optional sc dev/fdt/fdt_arm_platform.c optional platform fdt dev/hdmi/hdmi_if.m optional hdmi dev/hwpmc/hwpmc_arm.c optional hwpmc dev/hwpmc/hwpmc_armv7.c optional hwpmc armv6 dev/hwpmc/hwpmc_armv7.c optional hwpmc armv7 dev/iicbus/twsi/twsi.c optional twsi dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci_host_generic pci dev/pci/pci_host_generic_fdt.c optional pci_host_generic pci fdt dev/psci/psci.c optional psci dev/psci/smccc_arm.S optional psci dev/syscons/scgfbrndr.c optional sc dev/uart/uart_cpu_fdt.c optional uart fdt kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_busdma_bufalloc.c standard kern/subr_devmap.c standard kern/subr_physmem.c standard kern/subr_sfbuf.c standard libkern/arm/aeabi_unwind.c standard libkern/arm/divsi3.S standard libkern/arm/ffs.S optional !armv7 !armv6 libkern/arm/ldivmod.S standard libkern/arm/ldivmod_helper.c standard libkern/arm/memclr.S standard libkern/arm/memcpy.S standard libkern/arm/memset.S standard libkern/arm/muldi3.c standard libkern/ashldi3.c standard libkern/ashrdi3.c standard libkern/divdi3.c standard libkern/ffsl.c optional !armv7 !armv6 libkern/ffsll.c optional !armv7 !armv6 libkern/fls.c optional !armv7 !armv6 libkern/flsl.c optional !armv7 !armv6 libkern/flsll.c optional !armv7 !armv6 libkern/lshrdi3.c standard libkern/memcmp.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard # CloudABI support cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf32-littlearm --binary-architecture arm cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # # Annapurna support arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}"