Index: head/sys/dev/cxgbe/common/common.h =================================================================== --- head/sys/dev/cxgbe/common/common.h (revision 367496) +++ head/sys/dev/cxgbe/common/common.h (revision 367497) @@ -1,930 +1,932 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __CHELSIO_COMMON_H #define __CHELSIO_COMMON_H #include "t4_hw.h" enum { MAX_NPORTS = 4, /* max # of ports */ SERNUM_LEN = 24, /* Serial # length */ EC_LEN = 16, /* E/C length */ ID_LEN = 16, /* ID length */ PN_LEN = 16, /* Part Number length */ MD_LEN = 16, /* MFG diags version length */ MACADDR_LEN = 12, /* MAC Address length */ }; enum { T4_REGMAP_SIZE = (160 * 1024), T5_REGMAP_SIZE = (332 * 1024), }; enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; enum { PAUSE_RX = 1 << 0, PAUSE_TX = 1 << 1, PAUSE_AUTONEG = 1 << 2 }; enum { /* * Real FECs. In the same order as the FEC portion of caps32 so that * the code can do (fec & M_FW_PORT_CAP32_FEC) to get all the real FECs. */ FEC_RS = 1 << 0, /* Reed-Solomon */ FEC_BASER_RS = 1 << 1, /* BASE-R, aka Firecode */ FEC_NONE = 1 << 2, /* no FEC */ /* * Pseudo FECs that translate to real FECs. The firmware knows nothing * about these and they start at M_FW_PORT_CAP32_FEC + 1. AUTO should * be set all by itself. */ FEC_AUTO = 1 << 5, FEC_MODULE = 1 << 6, /* FEC suggested by the cable/transceiver. */ }; enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; struct port_stats { u64 tx_octets; /* total # of octets in good frames */ u64 tx_frames; /* all good frames */ u64 tx_bcast_frames; /* all broadcast frames */ u64 tx_mcast_frames; /* all multicast frames */ u64 tx_ucast_frames; /* all unicast frames */ u64 tx_error_frames; /* all error frames */ u64 tx_frames_64; /* # of Tx frames in a particular range */ u64 tx_frames_65_127; u64 tx_frames_128_255; u64 tx_frames_256_511; u64 tx_frames_512_1023; u64 tx_frames_1024_1518; u64 tx_frames_1519_max; u64 tx_drop; /* # of dropped Tx frames */ u64 tx_pause; /* # of transmitted pause frames */ u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ u64 rx_octets; /* total # of octets in good frames */ u64 rx_frames; /* all good frames */ u64 rx_bcast_frames; /* all broadcast frames */ u64 rx_mcast_frames; /* all multicast frames */ u64 rx_ucast_frames; /* all unicast frames */ u64 rx_too_long; /* # of frames exceeding MTU */ u64 rx_jabber; /* # of jabber frames */ u64 rx_fcs_err; /* # of received frames with bad FCS */ u64 rx_len_err; /* # of received frames with length error */ u64 rx_symbol_err; /* symbol errors */ u64 rx_runt; /* # of short frames */ u64 rx_frames_64; /* # of Rx frames in a particular range */ u64 rx_frames_65_127; u64 rx_frames_128_255; u64 rx_frames_256_511; u64 rx_frames_512_1023; u64 rx_frames_1024_1518; u64 rx_frames_1519_max; u64 rx_pause; /* # of received pause frames */ u64 rx_ppp0; /* # of received PPP prio 0 frames */ u64 rx_ppp1; /* # of received PPP prio 1 frames */ u64 rx_ppp2; /* # of received PPP prio 2 frames */ u64 rx_ppp3; /* # of received PPP prio 3 frames */ u64 rx_ppp4; /* # of received PPP prio 4 frames */ u64 rx_ppp5; /* # of received PPP prio 5 frames */ u64 rx_ppp6; /* # of received PPP prio 6 frames */ u64 rx_ppp7; /* # of received PPP prio 7 frames */ u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ u64 rx_trunc0; /* buffer-group 0 truncated packets */ u64 rx_trunc1; /* buffer-group 1 truncated packets */ u64 rx_trunc2; /* buffer-group 2 truncated packets */ u64 rx_trunc3; /* buffer-group 3 truncated packets */ }; struct lb_port_stats { u64 octets; u64 frames; u64 bcast_frames; u64 mcast_frames; u64 ucast_frames; u64 error_frames; u64 frames_64; u64 frames_65_127; u64 frames_128_255; u64 frames_256_511; u64 frames_512_1023; u64 frames_1024_1518; u64 frames_1519_max; u64 drop; u64 ovflow0; u64 ovflow1; u64 ovflow2; u64 ovflow3; u64 trunc0; u64 trunc1; u64 trunc2; u64 trunc3; }; struct tp_tcp_stats { u32 tcp_out_rsts; u64 tcp_in_segs; u64 tcp_out_segs; u64 tcp_retrans_segs; }; struct tp_usm_stats { u32 frames; u32 drops; u64 octets; }; struct tp_fcoe_stats { u32 frames_ddp; u32 frames_drop; u64 octets_ddp; }; struct tp_err_stats { u32 mac_in_errs[MAX_NCHAN]; u32 hdr_in_errs[MAX_NCHAN]; u32 tcp_in_errs[MAX_NCHAN]; u32 tnl_cong_drops[MAX_NCHAN]; u32 ofld_chan_drops[MAX_NCHAN]; u32 tnl_tx_drops[MAX_NCHAN]; u32 ofld_vlan_drops[MAX_NCHAN]; u32 tcp6_in_errs[MAX_NCHAN]; u32 ofld_no_neigh; u32 ofld_cong_defer; }; struct tp_proxy_stats { u32 proxy[MAX_NCHAN]; }; struct tp_cpl_stats { u32 req[MAX_NCHAN]; u32 rsp[MAX_NCHAN]; }; struct tp_rdma_stats { u32 rqe_dfr_pkt; u32 rqe_dfr_mod; }; struct sge_params { int timer_val[SGE_NTIMERS]; /* final, scaled values */ int counter_val[SGE_NCOUNTERS]; int fl_starve_threshold; int fl_starve_threshold2; int page_shift; int eq_s_qpp; int iq_s_qpp; int spg_len; int pad_boundary; int pack_boundary; int fl_pktshift; u32 sge_control; u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; }; struct tp_params { unsigned int tre; /* log2 of core clocks per TP tick */ unsigned int dack_re; /* DACK timer resolution */ unsigned int la_mask; /* what events are recorded by TP LA */ unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ uint32_t vlan_pri_map; uint32_t ingress_config; uint32_t max_rx_pdu; uint32_t max_tx_pdu; uint64_t hash_filter_mask; bool rx_pkt_encap; int8_t fcoe_shift; int8_t port_shift; int8_t vnic_shift; int8_t vlan_shift; int8_t tos_shift; int8_t protocol_shift; int8_t ethertype_shift; int8_t macmatch_shift; int8_t matchtype_shift; int8_t frag_shift; }; struct vpd_params { unsigned int cclk; u8 ec[EC_LEN + 1]; u8 sn[SERNUM_LEN + 1]; u8 id[ID_LEN + 1]; u8 pn[PN_LEN + 1]; u8 na[MACADDR_LEN + 1]; u8 md[MD_LEN + 1]; }; struct pci_params { unsigned int vpd_cap_addr; unsigned int mps; unsigned short speed; unsigned short width; }; /* * Firmware device log. */ struct devlog_params { u32 memtype; /* which memory (FW_MEMTYPE_* ) */ u32 start; /* start of log in firmware memory */ u32 size; /* size of log */ u32 addr; /* start address in flat addr space */ }; /* Stores chip specific parameters */ struct chip_params { u8 nchan; u8 pm_stats_cnt; u8 cng_ch_bits_log; /* congestion channel map bits width */ u8 nsched_cls; u8 cim_num_obq; u16 mps_rplc_size; u16 vfcount; u32 sge_fl_db; u16 mps_tcam_size; u16 rss_nentries; }; /* VF-only parameters. */ /* * Global Receive Side Scaling (RSS) parameters in host-native format. */ struct rss_params { unsigned int mode; /* RSS mode */ union { struct { u_int synmapen:1; /* SYN Map Enable */ u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ u_int ofdmapen:1; /* Offload Map Enable */ u_int tnlmapen:1; /* Tunnel Map Enable */ u_int tnlalllookup:1; /* Tunnel All Lookup */ u_int hashtoeplitz:1; /* use Toeplitz hash */ } basicvirtual; } u; }; /* * Maximum resources provisioned for a PCI VF. */ struct vf_resources { unsigned int nvi; /* N virtual interfaces */ unsigned int neq; /* N egress Qs */ unsigned int nethctrl; /* N egress ETH or CTRL Qs */ unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ unsigned int niq; /* N ingress Qs */ unsigned int tc; /* PCI-E traffic class */ unsigned int pmask; /* port access rights mask */ unsigned int nexactf; /* N exact MPS filters */ unsigned int r_caps; /* read capabilities */ unsigned int wx_caps; /* write/execute capabilities */ }; struct adapter_params { struct sge_params sge; struct tp_params tp; /* PF-only */ struct vpd_params vpd; struct pci_params pci; struct devlog_params devlog; /* PF-only */ struct rss_params rss; /* VF-only */ struct vf_resources vfres; /* VF-only */ unsigned int core_vdd; unsigned int sf_size; /* serial flash size in bytes */ unsigned int sf_nsec; /* # of flash sectors */ unsigned int fw_vers; /* firmware version */ unsigned int bs_vers; /* bootstrap version */ unsigned int tp_vers; /* TP microcode version */ unsigned int er_vers; /* expansion ROM version */ unsigned int scfg_vers; /* Serial Configuration version */ unsigned int vpd_vers; /* VPD version */ unsigned short mtus[NMTUS]; unsigned short a_wnd[NCCTRL_WIN]; unsigned short b_wnd[NCCTRL_WIN]; unsigned int cim_la_size; uint8_t nports; /* # of ethernet ports */ uint8_t portvec; unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ unsigned int rev:4; /* chip revision */ unsigned int fpga:1; /* this is an FPGA */ unsigned int offload:1; /* hw is TOE capable, fw has divvied up card resources for TOE operation. */ unsigned int bypass:1; /* this is a bypass card */ unsigned int ethoffload:1; unsigned int hash_filter:1; unsigned int filter2_wr_support:1; unsigned int port_caps32:1; unsigned int smac_add_support:1; unsigned int ofldq_wr_cred; unsigned int eo_wr_cred; unsigned int max_ordird_qp; unsigned int max_ird_adapter; uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */ bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ bool viid_smt_extn_support; /* FW returns vin, vfvld & smt index? */ unsigned int max_pkts_per_eth_tx_pkts_wr; }; #define CHELSIO_T4 0x4 #define CHELSIO_T5 0x5 #define CHELSIO_T6 0x6 /* * State needed to monitor the forward progress of SGE Ingress DMA activities * and possible hangs. */ struct sge_idma_monitor_state { unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ unsigned int idma_state[2]; /* IDMA Hang detect state */ unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ unsigned int idma_warn[2]; /* time to warning in HZ */ }; struct trace_params { u32 data[TRACE_LEN / 4]; u32 mask[TRACE_LEN / 4]; unsigned short snap_len; unsigned short min_len; unsigned char skip_ofst; unsigned char skip_len; unsigned char invert; unsigned char port; }; struct link_config { /* OS-specific code owns all the requested_* fields. */ int8_t requested_aneg; /* link autonegotiation */ int8_t requested_fc; /* flow control */ int8_t requested_fec; /* FEC */ u_int requested_speed; /* speed (Mbps) */ uint32_t pcaps; /* link capabilities */ uint32_t acaps; /* advertised capabilities */ uint32_t lpacaps; /* peer advertised capabilities */ u_int speed; /* actual link speed (Mbps) */ int8_t fc; /* actual link flow control */ int8_t fec_hint; /* cable/transceiver recommended fec */ int8_t fec; /* actual FEC */ bool link_ok; /* link up? */ uint8_t link_down_rc; /* link down reason */ }; #include "adapter.h" #ifndef PCI_VENDOR_ID_CHELSIO # define PCI_VENDOR_ID_CHELSIO 0x1425 #endif #define for_each_port(adapter, iter) \ for (iter = 0; iter < (adapter)->params.nports; ++iter) static inline int is_ftid(const struct adapter *sc, u_int tid) { return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base && tid <= sc->tids.ftid_end); } static inline int is_hpftid(const struct adapter *sc, u_int tid) { return (sc->tids.nhpftids > 0 && tid >= sc->tids.hpftid_base && tid <= sc->tids.hpftid_end); } static inline int is_etid(const struct adapter *sc, u_int tid) { return (sc->tids.netids > 0 && tid >= sc->tids.etid_base && tid <= sc->tids.etid_end); } static inline int is_offload(const struct adapter *adap) { return adap->params.offload; } static inline int is_ethoffload(const struct adapter *adap) { return adap->params.ethoffload; } static inline int is_hashfilter(const struct adapter *adap) { return adap->params.hash_filter; } static inline int chip_id(struct adapter *adap) { return adap->params.chipid; } static inline int chip_rev(struct adapter *adap) { return adap->params.rev; } static inline int is_t4(struct adapter *adap) { return adap->params.chipid == CHELSIO_T4; } static inline int is_t5(struct adapter *adap) { return adap->params.chipid == CHELSIO_T5; } static inline int is_t6(struct adapter *adap) { return adap->params.chipid == CHELSIO_T6; } static inline int is_fpga(struct adapter *adap) { return adap->params.fpga; } static inline unsigned int core_ticks_per_usec(const struct adapter *adap) { return adap->params.vpd.cclk / 1000; } static inline unsigned int us_to_core_ticks(const struct adapter *adap, unsigned int us) { return (us * adap->params.vpd.cclk) / 1000; } static inline unsigned int core_ticks_to_us(const struct adapter *adapter, unsigned int ticks) { /* add Core Clock / 2 to round ticks to nearest uS */ return ((ticks * 1000 + adapter->params.vpd.cclk/2) / adapter->params.vpd.cclk); } static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, unsigned int ticks) { return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); } static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us) { return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre); } static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks) { return ((uint64_t)ticks << adap->params.tp.tre) / core_ticks_per_usec(adap); } void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, bool sleep_ok, int timeout); int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, bool sleep_ok); static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, int timeout) { return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, timeout); } static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl) { return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); } static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl) { return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); } void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, u32 *vals, unsigned int nregs, unsigned int start_idx); void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, const u32 *vals, unsigned int nregs, unsigned int start_idx); u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); struct fw_filter_wr; void t4_intr_enable(struct adapter *adapter); void t4_intr_disable(struct adapter *adapter); void t4_intr_clear(struct adapter *adapter); int t4_slow_intr_handler(struct adapter *adapter, bool verbose); int t4_hash_mac_addr(const u8 *addr); int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, struct link_config *lc); int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); int t4_seeprom_wp(struct adapter *adapter, int enable); int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented); int t4_write_flash(struct adapter *adapter, unsigned int addr, unsigned int n, const u8 *data, int byte_oriented); int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); int t5_fw_init_extern_mem(struct adapter *adap); int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); int t4_load_boot(struct adapter *adap, u8 *boot_data, unsigned int boot_addr, unsigned int size); int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); int t4_flash_cfg_addr(struct adapter *adapter); int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); int t4_get_fw_version(struct adapter *adapter, u32 *vers); int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr); int t4_get_bs_version(struct adapter *adapter, u32 *vers); int t4_get_tp_version(struct adapter *adapter, u32 *vers); int t4_get_exprom_version(struct adapter *adapter, u32 *vers); int t4_get_scfg_version(struct adapter *adapter, u32 *vers); int t4_get_vpd_version(struct adapter *adapter, u32 *vers); int t4_get_version_info(struct adapter *adapter); int t4_init_hw(struct adapter *adapter, u32 fw_params); const struct chip_params *t4_get_chip_params(int chipid); int t4_prep_adapter(struct adapter *adapter, u32 *buf); int t4_shutdown_adapter(struct adapter *adapter); int t4_init_devlog_params(struct adapter *adapter, int fw_attach); int t4_init_sge_params(struct adapter *adapter); int t4_init_tp_params(struct adapter *adap, bool sleep_ok); int t4_filter_field_shift(const struct adapter *adap, int filter_sel); int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); void t4_fatal_err(struct adapter *adapter, bool fw_error); int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, int filter_index, int enable); void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, int filter_index, int *enabled); int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, int start, int n, const u16 *rspq, unsigned int nrspq); int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, unsigned int flags); int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, unsigned int flags, unsigned int defq, unsigned int skeyidx, unsigned int skey); int t4_read_rss(struct adapter *adapter, u16 *entries); void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, bool sleep_ok); void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp, bool sleep_ok); void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val, bool sleep_ok); void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, u32 *vfl, u32 *vfh, bool sleep_ok); void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, u32 vfl, u32 vfh, bool sleep_ok); u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok); u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok); int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp); int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, const unsigned int *valp); int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp); int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); int t4_get_flash_params(struct adapter *adapter); u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, __be32 *data); void t4_idma_monitor_init(struct adapter *adapter, struct sge_idma_monitor_state *idma); void t4_idma_monitor(struct adapter *adapter, struct sge_idma_monitor_state *idma, int hz, int ticks); unsigned int t4_get_regs_len(struct adapter *adapter); void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); const char *t4_get_port_type_description(enum fw_port_type port_type); void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); void t4_get_port_stats_offset(struct adapter *adap, int idx, struct port_stats *stats, struct port_stats *offset); void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); void t4_clr_port_stats(struct adapter *adap, int idx); void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, unsigned int *ipg, bool sleep_ok); void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, unsigned int mask, unsigned int val); void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, bool sleep_ok); void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, bool sleep_ok); void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, bool sleep_ok); void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, bool sleep_ok); void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, bool sleep_ok); void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, struct tp_tcp_stats *v6, bool sleep_ok); void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, struct tp_fcoe_stats *st, bool sleep_ok); void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, const unsigned short *alpha, const unsigned short *beta); void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, unsigned int start, unsigned int n); void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, bool sleep_ok); void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, u64 mask0, u64 mask1, unsigned int crc, bool enable); int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, enum dev_master master, enum dev_state *state); int t4_fw_bye(struct adapter *adap, unsigned int mbox); int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); int t4_fw_restart(struct adapter *adap, unsigned int mbox); int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, const u8 *fw_data, unsigned int size, int force); int t4_fw_initialize(struct adapter *adap, unsigned int mbox); int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, u32 *val); int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, u32 *val, int rw); int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, const u32 *val, int timeout); int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, const u32 *val); int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, unsigned int rxqi, unsigned int rxq, unsigned int tc, unsigned int vi, unsigned int cmask, unsigned int pmask, unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, u16 *rss_size, uint8_t *vfvld, uint16_t *vin, unsigned int portfunc, unsigned int idstype); int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, u16 *rss_size, uint8_t *vfvld, uint16_t *vin); int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int viid); int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, int mtu, int promisc, int all_multi, int bcast, int vlanex, bool sleep_ok); int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, bool free, unsigned int naddr, const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, unsigned int naddr, const u8 **addr, bool sleep_ok); int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, bool sleep_ok); int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, const u8 *addr, const u8 *mask, unsigned int idx, u8 lookup_type, u8 port_id, bool sleep_ok); int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, const u8 *addr, const u8 *mask, unsigned int idx, u8 lookup_type, u8 port_id, bool sleep_ok); int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, const u8 *addr, const u8 *mask, unsigned int vni, unsigned int vni_mask, u8 dip_hit, u8 lookup_type, bool sleep_ok); int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, uint16_t *smt_idx); int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, const u8 *addr, bool smac); int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac); int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, bool ucast, u64 vec, bool sleep_ok); int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, bool rx_en, bool tx_en); int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, unsigned int nblinks); int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, unsigned int mmd, unsigned int reg, unsigned int *valp); int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, unsigned int mmd, unsigned int reg, unsigned int val); int t4_i2c_io(struct adapter *adap, unsigned int mbox, int port, unsigned int devid, unsigned int offset, unsigned int len, u8 *buf, bool write); int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, unsigned int devid, unsigned int offset, unsigned int len, u8 *buf); int t4_i2c_wr(struct adapter *adap, unsigned int mbox, int port, unsigned int devid, unsigned int offset, unsigned int len, u8 *buf); int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int iqtype, unsigned int iqid, unsigned int fl0id, unsigned int fl1id); int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int iqtype, unsigned int iqid, unsigned int fl0id, unsigned int fl1id); int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid); int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid); int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid); int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, enum ctxt_type ctype, u32 *data); int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, u32 *data); int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); const char *t4_link_down_rc_str(unsigned char link_down_rc); int t4_update_port_info(struct port_info *pi); int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); int t4_sched_config(struct adapter *adapter, int type, int minmaxen, int sleep_ok); int t4_sched_params(struct adapter *adapter, int type, int level, int mode, int rateunit, int ratemode, int channel, int cl, int minrate, int maxrate, int weight, int pktsize, int burstsize, int sleep_ok); int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, unsigned int maxrate, int sleep_ok); int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, int weight, int sleep_ok); int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, int mode, unsigned int maxrate, int pktsize, int sleep_ok); int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int timeout, unsigned int action); int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); int t4_set_devlog_level(struct adapter *adapter, unsigned int level); void t4_sge_decode_idma_state(struct adapter *adapter, int state); void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, bool sleep_ok); void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, u32 start_index, bool sleep_ok); void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, bool sleep_ok); void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, bool sleep_ok); int t4_configure_ringbb(struct adapter *adap); int t4_configure_add_smac(struct adapter *adap); int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, u16 vlan); static inline int t4vf_query_params(struct adapter *adapter, unsigned int nparams, const u32 *params, u32 *vals) { return t4_query_params(adapter, 0, 0, 0, nparams, params, vals); } static inline int t4vf_set_params(struct adapter *adapter, unsigned int nparams, const u32 *params, const u32 *vals) { return t4_set_params(adapter, 0, 0, 0, nparams, params, vals); } static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd, int size, void *rpl) { return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl); } int t4vf_wait_dev_ready(struct adapter *adapter); int t4vf_fw_reset(struct adapter *adapter); int t4vf_get_sge_params(struct adapter *adapter); int t4vf_get_rss_glb_config(struct adapter *adapter); int t4vf_get_vfres(struct adapter *adapter); int t4vf_prep_adapter(struct adapter *adapter); +int t4vf_get_vf_mac(struct adapter *adapter, unsigned int port, + unsigned int *naddr, u8 *addr); int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset, unsigned int *pbar2_qid); unsigned int fwcap_to_speed(uint32_t caps); uint32_t speed_to_fwcap(unsigned int speed); uint32_t fwcap_top_speed(uint32_t caps); static inline int port_top_speed(const struct port_info *pi) { /* Mbps -> Gbps */ return (fwcap_to_speed(pi->link_cfg.pcaps) / 1000); } #endif /* __CHELSIO_COMMON_H */ Index: head/sys/dev/cxgbe/common/t4vf_hw.c =================================================================== --- head/sys/dev/cxgbe/common/t4vf_hw.c (revision 367496) +++ head/sys/dev/cxgbe/common/t4vf_hw.c (revision 367497) @@ -1,384 +1,430 @@ /*- * Copyright (c) 2016 Chelsio Communications, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "common.h" #include "t4_regs.h" #include "t4_regs_values.h" #undef msleep #define msleep(x) do { \ if (cold) \ DELAY((x) * 1000); \ else \ pause("t4hw", (x) * hz / 1000); \ } while (0) /* * Wait for the device to become ready (signified by our "who am I" register * returning a value other than all 1's). Return an error if it doesn't * become ready ... */ int t4vf_wait_dev_ready(struct adapter *adapter) { const u32 whoami = VF_PL_REG(A_PL_VF_WHOAMI); const u32 notready1 = 0xffffffff; const u32 notready2 = 0xeeeeeeee; u32 val; val = t4_read_reg(adapter, whoami); if (val != notready1 && val != notready2) return 0; msleep(500); val = t4_read_reg(adapter, whoami); if (val != notready1 && val != notready2) return 0; else return -EIO; } /** * t4vf_fw_reset - issue a reset to FW * @adapter: the adapter * * Issues a reset command to FW. For a Physical Function this would * result in the Firmware reseting all of its state. For a Virtual * Function this just resets the state associated with the VF. */ int t4vf_fw_reset(struct adapter *adapter) { struct fw_reset_cmd cmd; memset(&cmd, 0, sizeof(cmd)); cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RESET_CMD) | F_FW_CMD_WRITE); cmd.retval_len16 = cpu_to_be32(V_FW_CMD_LEN16(FW_LEN16(cmd))); return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL); } /** * t4vf_get_sge_params - retrieve adapter Scatter gather Engine parameters * @adapter: the adapter * * Retrieves various core SGE parameters in the form of hardware SGE * register values. The caller is responsible for decoding these as * needed. The SGE parameters are stored in @adapter->params.sge. */ int t4vf_get_sge_params(struct adapter *adapter) { struct sge_params *sp = &adapter->params.sge; u32 params[7], vals[7]; u32 whoami; unsigned int pf, s_hps; int i, v; params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_CONTROL)); params[1] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_HOST_PAGE_SIZE)); params[2] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_TIMER_VALUE_0_AND_1)); params[3] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_TIMER_VALUE_2_AND_3)); params[4] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_TIMER_VALUE_4_AND_5)); params[5] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_CONM_CTRL)); params[6] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_INGRESS_RX_THRESHOLD)); v = t4vf_query_params(adapter, 7, params, vals); if (v != FW_SUCCESS) return v; sp->sge_control = vals[0]; sp->counter_val[0] = G_THRESHOLD_0(vals[6]); sp->counter_val[1] = G_THRESHOLD_1(vals[6]); sp->counter_val[2] = G_THRESHOLD_2(vals[6]); sp->counter_val[3] = G_THRESHOLD_3(vals[6]); sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(vals[2])); sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(vals[2])); sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(vals[3])); sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(vals[3])); sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(vals[4])); sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(vals[4])); sp->fl_starve_threshold = G_EGRTHRESHOLD(vals[5]) * 2 + 1; if (is_t4(adapter)) sp->fl_starve_threshold2 = sp->fl_starve_threshold; else if (is_t5(adapter)) sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(vals[5]) * 2 + 1; else sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(vals[5]) * 2 + 1; /* * We need the Queues/Page and Host Page Size for our VF. * This is based on the PF from which we're instantiated. */ whoami = t4_read_reg(adapter, VF_PL_REG(A_PL_VF_WHOAMI)); pf = G_SOURCEPF(whoami); s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * pf); sp->page_shift = ((vals[1] >> s_hps) & M_HOSTPAGESIZEPF0) + 10; for (i = 0; i < SGE_FLBUF_SIZES; i++) { params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_FL_BUFFER_SIZE0 + (4 * i))); v = t4vf_query_params(adapter, 1, params, vals); if (v != FW_SUCCESS) return v; sp->sge_fl_buffer_size[i] = vals[0]; } /* * T4 uses a single control field to specify both the PCIe Padding and * Packing Boundary. T5 introduced the ability to specify these * separately with the Padding Boundary in SGE_CONTROL and and Packing * Boundary in SGE_CONTROL2. So for T5 and later we need to grab * SGE_CONTROL in order to determine how ingress packet data will be * laid out in Packed Buffer Mode. Unfortunately, older versions of * the firmware won't let us retrieve SGE_CONTROL2 so if we get a * failure grabbing it we throw an error since we can't figure out the * right value. */ sp->spg_len = sp->sge_control & F_EGRSTATUSPAGESIZE ? 128 : 64; sp->fl_pktshift = G_PKTSHIFT(sp->sge_control); if (chip_id(adapter) <= CHELSIO_T5) { sp->pad_boundary = 1 << (G_INGPADBOUNDARY(sp->sge_control) + X_INGPADBOUNDARY_SHIFT); } else { sp->pad_boundary = 1 << (G_INGPADBOUNDARY(sp->sge_control) + X_T6_INGPADBOUNDARY_SHIFT); } if (is_t4(adapter)) sp->pack_boundary = sp->pad_boundary; else { params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_CONTROL2)); v = t4vf_query_params(adapter, 1, params, vals); if (v != FW_SUCCESS) { CH_ERR(adapter, "Unable to get SGE Control2; " "probably old firmware.\n"); return v; } if (G_INGPACKBOUNDARY(vals[0]) == 0) sp->pack_boundary = 16; else sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(vals[0]) + 5); } /* * For T5 and later we want to use the new BAR2 Doorbells. * Unfortunately, older firmware didn't allow the this register to be * read. */ if (!is_t4(adapter)) { unsigned int s_qpp; params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_EGRESS_QUEUES_PER_PAGE_VF)); params[1] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) | V_FW_PARAMS_PARAM_XYZ(A_SGE_INGRESS_QUEUES_PER_PAGE_VF)); v = t4vf_query_params(adapter, 2, params, vals); if (v != FW_SUCCESS) { CH_WARN(adapter, "Unable to get VF SGE Queues/Page; " "probably old firmware.\n"); return v; } s_qpp = (S_QUEUESPERPAGEPF0 + (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * pf); sp->eq_s_qpp = ((vals[0] >> s_qpp) & M_QUEUESPERPAGEPF0); sp->iq_s_qpp = ((vals[1] >> s_qpp) & M_QUEUESPERPAGEPF0); } return 0; } /** * t4vf_get_rss_glb_config - retrieve adapter RSS Global Configuration * @adapter: the adapter * * Retrieves global RSS mode and parameters with which we have to live * and stores them in the @adapter's RSS parameters. */ int t4vf_get_rss_glb_config(struct adapter *adapter) { struct rss_params *rss = &adapter->params.rss; struct fw_rss_glb_config_cmd cmd, rpl; int v; /* * Execute an RSS Global Configuration read command to retrieve * our RSS configuration. */ memset(&cmd, 0, sizeof(cmd)); cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_READ); cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl); if (v != FW_SUCCESS) return v; /* * Transate the big-endian RSS Global Configuration into our * cpu-endian format based on the RSS mode. We also do first level * filtering at this point to weed out modes which don't support * VF Drivers ... */ rss->mode = G_FW_RSS_GLB_CONFIG_CMD_MODE( be32_to_cpu(rpl.u.manual.mode_pkd)); switch (rss->mode) { case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: { u32 word = be32_to_cpu( rpl.u.basicvirtual.synmapen_to_hashtoeplitz); rss->u.basicvirtual.synmapen = ((word & F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) != 0); rss->u.basicvirtual.syn4tupenipv6 = ((word & F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) != 0); rss->u.basicvirtual.syn2tupenipv6 = ((word & F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) != 0); rss->u.basicvirtual.syn4tupenipv4 = ((word & F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) != 0); rss->u.basicvirtual.syn2tupenipv4 = ((word & F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) != 0); rss->u.basicvirtual.ofdmapen = ((word & F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) != 0); rss->u.basicvirtual.tnlmapen = ((word & F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) != 0); rss->u.basicvirtual.tnlalllookup = ((word & F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) != 0); rss->u.basicvirtual.hashtoeplitz = ((word & F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) != 0); /* we need at least Tunnel Map Enable to be set */ if (!rss->u.basicvirtual.tnlmapen) return -EINVAL; break; } default: /* all unknown/unsupported RSS modes result in an error */ return -EINVAL; } return 0; } /** * t4vf_get_vfres - retrieve VF resource limits * @adapter: the adapter * * Retrieves configured resource limits and capabilities for a virtual * function. The results are stored in @adapter->vfres. */ int t4vf_get_vfres(struct adapter *adapter) { struct vf_resources *vfres = &adapter->params.vfres; struct fw_pfvf_cmd cmd, rpl; int v; u32 word; /* * Execute PFVF Read command to get VF resource limits; bail out early * with error on command failure. */ memset(&cmd, 0, sizeof(cmd)); cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_READ); cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl); if (v != FW_SUCCESS) return v; /* * Extract VF resource limits and return success. */ word = be32_to_cpu(rpl.niqflint_niq); vfres->niqflint = G_FW_PFVF_CMD_NIQFLINT(word); vfres->niq = G_FW_PFVF_CMD_NIQ(word); word = be32_to_cpu(rpl.type_to_neq); vfres->neq = G_FW_PFVF_CMD_NEQ(word); vfres->pmask = G_FW_PFVF_CMD_PMASK(word); word = be32_to_cpu(rpl.tc_to_nexactf); vfres->tc = G_FW_PFVF_CMD_TC(word); vfres->nvi = G_FW_PFVF_CMD_NVI(word); vfres->nexactf = G_FW_PFVF_CMD_NEXACTF(word); word = be32_to_cpu(rpl.r_caps_to_nethctrl); vfres->r_caps = G_FW_PFVF_CMD_R_CAPS(word); vfres->wx_caps = G_FW_PFVF_CMD_WX_CAPS(word); vfres->nethctrl = G_FW_PFVF_CMD_NETHCTRL(word); return 0; } /** */ int t4vf_prep_adapter(struct adapter *adapter) { int err; /* * Wait for the device to become ready before proceeding ... */ err = t4vf_wait_dev_ready(adapter); if (err) return err; adapter->params.chipid = pci_get_device(adapter->dev) >> 12; if (adapter->params.chipid >= 0xa) { adapter->params.chipid -= (0xa - 0x4); adapter->params.fpga = 1; } /* * Default port and clock for debugging in case we can't reach * firmware. */ adapter->params.nports = 1; adapter->params.vfres.pmask = 1; adapter->params.vpd.cclk = 50000; adapter->chip_params = t4_get_chip_params(chip_id(adapter)); if (adapter->chip_params == NULL) return -EINVAL; return 0; } + +/* + * t4vf_get_vf_mac - Get the MAC address to be set to the VI of this VF. + * @adapter: The adapter + * @port: The port associated with vf + * @naddr: the number of ACL MAC addresses returned in addr + * @addr: Placeholder for MAC addresses + * + * Find the MAC address to be set to the VF's VI. The requested MAC address + * is from the host OS via callback in the PF driver. + */ +int t4vf_get_vf_mac(struct adapter *adapter, unsigned int port, + unsigned int *naddr, u8 *addr) +{ + struct fw_acl_mac_cmd cmd; + int ret; + + memset(&cmd, 0, sizeof(cmd)); + cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | + F_FW_CMD_REQUEST | + F_FW_CMD_READ); + cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); + ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &cmd); + if (ret) + return ret; + + if (cmd.nmac < *naddr) + *naddr = cmd.nmac; + + switch (port) { + case 3: + memcpy(addr, cmd.macaddr3, sizeof(cmd.macaddr3)); + break; + case 2: + memcpy(addr, cmd.macaddr2, sizeof(cmd.macaddr2)); + break; + case 1: + memcpy(addr, cmd.macaddr1, sizeof(cmd.macaddr1)); + break; + case 0: + memcpy(addr, cmd.macaddr0, sizeof(cmd.macaddr0)); + break; + } + + return ret; +} Index: head/sys/dev/cxgbe/t4_vf.c =================================================================== --- head/sys/dev/cxgbe/t4_vf.c (revision 367496) +++ head/sys/dev/cxgbe/t4_vf.c (revision 367497) @@ -1,983 +1,994 @@ /*- * Copyright (c) 2016 Chelsio Communications, Inc. * All rights reserved. * Written by: John Baldwin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include "opt_inet6.h" #include #include #include #include #include #include #include #if defined(__i386__) || defined(__amd64__) #include #include #endif #include "common/common.h" #include "common/t4_regs.h" #include "t4_ioctl.h" #include "t4_mp_ring.h" /* * Some notes: * * The Virtual Interfaces are connected to an internal switch on the chip * which allows VIs attached to the same port to talk to each other even when * the port link is down. As a result, we might want to always report a * VF's link as being "up". * * XXX: Add a TUNABLE and possible per-device sysctl for this? */ struct intrs_and_queues { uint16_t intr_type; /* MSI, or MSI-X */ uint16_t nirq; /* Total # of vectors */ uint16_t ntxq; /* # of NIC txq's for each port */ uint16_t nrxq; /* # of NIC rxq's for each port */ }; struct { uint16_t device; char *desc; } t4vf_pciids[] = { {0x4800, "Chelsio T440-dbg VF"}, {0x4801, "Chelsio T420-CR VF"}, {0x4802, "Chelsio T422-CR VF"}, {0x4803, "Chelsio T440-CR VF"}, {0x4804, "Chelsio T420-BCH VF"}, {0x4805, "Chelsio T440-BCH VF"}, {0x4806, "Chelsio T440-CH VF"}, {0x4807, "Chelsio T420-SO VF"}, {0x4808, "Chelsio T420-CX VF"}, {0x4809, "Chelsio T420-BT VF"}, {0x480a, "Chelsio T404-BT VF"}, {0x480e, "Chelsio T440-LP-CR VF"}, }, t5vf_pciids[] = { {0x5800, "Chelsio T580-dbg VF"}, {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */ {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */ {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */ {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */ {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */ {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */ {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */ {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */ {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */ {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */ {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */ {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */ {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */ {0x5818, "Chelsio T540-BT VF"}, /* 4 x 10GBaseT */ {0x5819, "Chelsio T540-LP-BT VF"}, /* 4 x 10GBaseT */ {0x581a, "Chelsio T540-SO-BT VF"}, /* 4 x 10GBaseT, nomem */ {0x581b, "Chelsio T540-SO-CR VF"}, /* 4 x 10G, nomem */ }, t6vf_pciids[] = { {0x6800, "Chelsio T6-DBG-25 VF"}, /* 2 x 10/25G, debug */ {0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */ {0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */ {0x6803, "Chelsio T6425-CR VF"}, /* 4 x 10/25G */ {0x6804, "Chelsio T6425-SO-CR VF"}, /* 4 x 10/25G, nomem */ {0x6805, "Chelsio T6225-OCP-SO VF"}, /* 2 x 10/25G, nomem */ {0x6806, "Chelsio T62100-OCP-SO VF"}, /* 2 x 40/50/100G, nomem */ {0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */ {0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */ {0x6809, "Chelsio T6210-BT VF"}, /* 2 x 10GBASE-T */ {0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */ {0x6810, "Chelsio T6-DBG-100 VF"}, /* 2 x 40/50/100G, debug */ {0x6811, "Chelsio T6225-LL-CR VF"}, /* 2 x 10/25G */ {0x6814, "Chelsio T61100-OCP-SO VF"}, /* 1 x 40/50/100G, nomem */ {0x6815, "Chelsio T6201-BT VF"}, /* 2 x 1000BASE-T */ /* Custom */ {0x6880, "Chelsio T6225 80 VF"}, {0x6881, "Chelsio T62100 81 VF"}, {0x6882, "Chelsio T6225-CR 82 VF"}, {0x6883, "Chelsio T62100-CR 83 VF"}, {0x6884, "Chelsio T64100-CR 84 VF"}, {0x6885, "Chelsio T6240-SO 85 VF"}, {0x6886, "Chelsio T6225-SO-CR 86 VF"}, {0x6887, "Chelsio T6225-CR 87 VF"}, }; static d_ioctl_t t4vf_ioctl; static struct cdevsw t4vf_cdevsw = { .d_version = D_VERSION, .d_ioctl = t4vf_ioctl, .d_name = "t4vf", }; static int t4vf_probe(device_t dev) { uint16_t d; size_t i; d = pci_get_device(dev); for (i = 0; i < nitems(t4vf_pciids); i++) { if (d == t4vf_pciids[i].device) { device_set_desc(dev, t4vf_pciids[i].desc); return (BUS_PROBE_DEFAULT); } } return (ENXIO); } static int t5vf_probe(device_t dev) { uint16_t d; size_t i; d = pci_get_device(dev); for (i = 0; i < nitems(t5vf_pciids); i++) { if (d == t5vf_pciids[i].device) { device_set_desc(dev, t5vf_pciids[i].desc); return (BUS_PROBE_DEFAULT); } } return (ENXIO); } static int t6vf_probe(device_t dev) { uint16_t d; size_t i; d = pci_get_device(dev); for (i = 0; i < nitems(t6vf_pciids); i++) { if (d == t6vf_pciids[i].device) { device_set_desc(dev, t6vf_pciids[i].desc); return (BUS_PROBE_DEFAULT); } } return (ENXIO); } #define FW_PARAM_DEV(param) \ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) #define FW_PARAM_PFVF(param) \ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) static int get_params__pre_init(struct adapter *sc) { int rc; uint32_t param[3], val[3]; param[0] = FW_PARAM_DEV(FWREV); param[1] = FW_PARAM_DEV(TPREV); param[2] = FW_PARAM_DEV(CCLK); rc = -t4vf_query_params(sc, nitems(param), param, val); if (rc != 0) { device_printf(sc->dev, "failed to query parameters (pre_init): %d.\n", rc); return (rc); } sc->params.fw_vers = val[0]; sc->params.tp_vers = val[1]; sc->params.vpd.cclk = val[2]; snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); return (0); } static int get_params__post_init(struct adapter *sc) { int rc; uint32_t param, val; rc = -t4vf_get_sge_params(sc); if (rc != 0) { device_printf(sc->dev, "unable to retrieve adapter SGE parameters: %d\n", rc); return (rc); } rc = -t4vf_get_rss_glb_config(sc); if (rc != 0) { device_printf(sc->dev, "unable to retrieve adapter RSS parameters: %d\n", rc); return (rc); } if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { device_printf(sc->dev, "unable to operate with global RSS mode %d\n", sc->params.rss.mode); return (EINVAL); } rc = t4_read_chip_settings(sc); if (rc != 0) return (rc); /* * Grab our Virtual Interface resource allocation, extract the * features that we're interested in and do a bit of sanity testing on * what we discover. */ rc = -t4vf_get_vfres(sc); if (rc != 0) { device_printf(sc->dev, "unable to get virtual interface resources: %d\n", rc); return (rc); } /* * Check for various parameter sanity issues. */ if (sc->params.vfres.pmask == 0) { device_printf(sc->dev, "no port access configured/usable!\n"); return (EINVAL); } if (sc->params.vfres.nvi == 0) { device_printf(sc->dev, "no virtual interfaces configured/usable!\n"); return (EINVAL); } sc->params.portvec = sc->params.vfres.pmask; param = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); rc = -t4vf_query_params(sc, 1, ¶m, &val); if (rc == 0) sc->params.max_pkts_per_eth_tx_pkts_wr = val; else sc->params.max_pkts_per_eth_tx_pkts_wr = 14; return (0); } static int set_params__post_init(struct adapter *sc) { uint32_t param, val; /* ask for encapsulated CPLs */ param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); val = 1; (void)t4vf_set_params(sc, 1, ¶m, &val); /* Enable 32b port caps if the firmware supports it. */ param = FW_PARAM_PFVF(PORT_CAPS32); val = 1; if (t4vf_set_params(sc, 1, ¶m, &val) == 0) sc->params.port_caps32 = 1; return (0); } #undef FW_PARAM_PFVF #undef FW_PARAM_DEV static int cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) { struct vf_resources *vfres; int nrxq, ntxq, nports; int itype, iq_avail, navail, rc; /* * Figure out the layout of queues across our VIs and ensure * we can allocate enough interrupts for our layout. */ vfres = &sc->params.vfres; nports = sc->params.nports; bzero(iaq, sizeof(*iaq)); for (itype = INTR_MSIX; itype != 0; itype >>= 1) { if (itype == INTR_INTX) continue; if (itype == INTR_MSIX) navail = pci_msix_count(sc->dev); else navail = pci_msi_count(sc->dev); if (navail == 0) continue; iaq->intr_type = itype; /* * XXX: The Linux driver reserves an Ingress Queue for * forwarded interrupts when using MSI (but not MSI-X). * It seems it just always asks for 2 interrupts and * forwards all rxqs to the forwarded interrupt. * * We must reserve one IRQ for the for the firmware * event queue. * * Every rxq requires an ingress queue with a free * list and interrupts and an egress queue. Every txq * requires an ETH egress queue. */ iaq->nirq = T4VF_EXTRA_INTR; /* * First, determine how many queues we can allocate. * Start by finding the upper bound on rxqs from the * limit on ingress queues. */ iq_avail = vfres->niqflint - iaq->nirq; if (iq_avail < nports) { device_printf(sc->dev, "Not enough ingress queues (%d) for %d ports\n", vfres->niqflint, nports); return (ENXIO); } /* * Try to honor the cap on interrupts. If there aren't * enough interrupts for at least one interrupt per * port, then don't bother, we will just forward all * interrupts to one interrupt in that case. */ if (iaq->nirq + nports <= navail) { if (iq_avail > navail - iaq->nirq) iq_avail = navail - iaq->nirq; } nrxq = nports * t4_nrxq; if (nrxq > iq_avail) { /* * Too many ingress queues. Use what we can. */ nrxq = (iq_avail / nports) * nports; } KASSERT(nrxq <= iq_avail, ("too many ingress queues")); /* * Next, determine the upper bound on txqs from the limit * on ETH queues. */ if (vfres->nethctrl < nports) { device_printf(sc->dev, "Not enough ETH queues (%d) for %d ports\n", vfres->nethctrl, nports); return (ENXIO); } ntxq = nports * t4_ntxq; if (ntxq > vfres->nethctrl) { /* * Too many ETH queues. Use what we can. */ ntxq = (vfres->nethctrl / nports) * nports; } KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues")); /* * Finally, ensure we have enough egress queues. */ if (vfres->neq < nports * 2) { device_printf(sc->dev, "Not enough egress queues (%d) for %d ports\n", vfres->neq, nports); return (ENXIO); } if (nrxq + ntxq > vfres->neq) { /* Just punt and use 1 for everything. */ nrxq = ntxq = nports; } KASSERT(nrxq <= iq_avail, ("too many ingress queues")); KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues")); KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues")); /* * Do we have enough interrupts? For MSI the interrupts * have to be a power of 2 as well. */ iaq->nirq += nrxq; iaq->ntxq = ntxq; iaq->nrxq = nrxq; if (iaq->nirq <= navail && (itype != INTR_MSI || powerof2(iaq->nirq))) { navail = iaq->nirq; if (itype == INTR_MSIX) rc = pci_alloc_msix(sc->dev, &navail); else rc = pci_alloc_msi(sc->dev, &navail); if (rc != 0) { device_printf(sc->dev, "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", itype, rc, iaq->nirq, navail); return (rc); } if (navail == iaq->nirq) { return (0); } pci_release_msi(sc->dev); } /* Fall back to a single interrupt. */ iaq->nirq = 1; navail = iaq->nirq; if (itype == INTR_MSIX) rc = pci_alloc_msix(sc->dev, &navail); else rc = pci_alloc_msi(sc->dev, &navail); if (rc != 0) device_printf(sc->dev, "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", itype, rc, iaq->nirq, navail); return (rc); } device_printf(sc->dev, "failed to find a usable interrupt type. " "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, pci_msix_count(sc->dev), pci_msi_count(sc->dev)); return (ENXIO); } static int t4vf_attach(device_t dev) { struct adapter *sc; - int rc = 0, i, j, rqidx, tqidx; + int rc = 0, i, j, rqidx, tqidx, n, p, pmask; struct make_dev_args mda; struct intrs_and_queues iaq; struct sge *s; sc = device_get_softc(dev); sc->dev = dev; pci_enable_busmaster(dev); pci_set_max_read_req(dev, 4096); sc->params.pci.mps = pci_get_max_payload(dev); sc->flags |= IS_VF; TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS); sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL); snprintf(sc->lockname, sizeof(sc->lockname), "%s", device_get_nameunit(dev)); mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); t4_add_adapter(sc); mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); TAILQ_INIT(&sc->sfl); callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); rc = t4_map_bars_0_and_4(sc); if (rc != 0) goto done; /* error message displayed already */ rc = -t4vf_prep_adapter(sc); if (rc != 0) goto done; t4_init_devnames(sc); if (sc->names == NULL) { rc = ENOTSUP; goto done; /* error message displayed already */ } /* * Leave the 'pf' and 'mbox' values as zero. This ensures * that various firmware messages do not set the fields which * is the correct thing to do for a VF. */ memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); make_dev_args_init(&mda); mda.mda_devsw = &t4vf_cdevsw; mda.mda_uid = UID_ROOT; mda.mda_gid = GID_WHEEL; mda.mda_mode = 0600; mda.mda_si_drv1 = sc; rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); if (rc != 0) device_printf(dev, "failed to create nexus char device: %d.\n", rc); #if defined(__i386__) if ((cpu_feature & CPUID_CX8) == 0) { device_printf(dev, "64 bit atomics not available.\n"); rc = ENOTSUP; goto done; } #endif /* * Some environments do not properly handle PCIE FLRs -- e.g. in Linux * 2.6.31 and later we can't call pci_reset_function() in order to * issue an FLR because of a self- deadlock on the device semaphore. * Meanwhile, the OS infrastructure doesn't issue FLRs in all the * cases where they're needed -- for instance, some versions of KVM * fail to reset "Assigned Devices" when the VM reboots. Therefore we * use the firmware based reset in order to reset any per function * state. */ rc = -t4vf_fw_reset(sc); if (rc != 0) { device_printf(dev, "FW reset failed: %d\n", rc); goto done; } sc->flags |= FW_OK; /* * Grab basic operational parameters. These will predominantly have * been set up by the Physical Function Driver or will be hard coded * into the adapter. We just have to live with them ... Note that * we _must_ get our VPD parameters before our SGE parameters because * we need to know the adapter's core clock from the VPD in order to * properly decode the SGE Timer Values. */ rc = get_params__pre_init(sc); if (rc != 0) goto done; /* error message displayed already */ rc = get_params__post_init(sc); if (rc != 0) goto done; /* error message displayed already */ rc = set_params__post_init(sc); if (rc != 0) goto done; /* error message displayed already */ rc = t4_map_bar_2(sc); if (rc != 0) goto done; /* error message displayed already */ rc = t4_create_dma_tag(sc); if (rc != 0) goto done; /* error message displayed already */ /* * The number of "ports" which we support is equal to the number of * Virtual Interfaces with which we've been provisioned. */ sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS); /* * We may have been provisioned with more VIs than the number of * ports we're allowed to access (our Port Access Rights Mask). * Just use a single VI for each port. */ sc->params.nports = imin(sc->params.nports, bitcount32(sc->params.vfres.pmask)); #ifdef notyet /* * XXX: The Linux VF driver will lower nports if it thinks there * are too few resources in vfres (niqflint, nethctrl, neq). */ #endif /* * First pass over all the ports - allocate VIs and initialize some * basic parameters like mac address, port type, etc. */ + pmask = sc->params.vfres.pmask; for_each_port(sc, i) { struct port_info *pi; + uint8_t mac[ETHER_ADDR_LEN]; pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); sc->port[i] = pi; /* These must be set before t4_port_init */ pi->adapter = sc; pi->port_id = i; pi->nvi = 1; pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE, M_ZERO | M_WAITOK); /* * Allocate the "main" VI and initialize parameters * like mac addr. */ rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); if (rc != 0) { device_printf(dev, "unable to initialize port %d: %d\n", i, rc); free(pi->vi, M_CXGBE); free(pi, M_CXGBE); sc->port[i] = NULL; goto done; } + + /* Prefer the MAC address set by the PF, if there is one. */ + n = 1; + p = ffs(pmask) - 1; + MPASS(p >= 0); + rc = t4vf_get_vf_mac(sc, p, &n, mac); + if (rc == 0 && n == 1) + t4_os_set_hw_addr(pi, mac); + pmask &= ~(1 << p); /* No t4_link_start. */ snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", device_get_nameunit(dev), i); mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); sc->chan_map[pi->tx_chan] = i; /* All VIs on this port share this media. */ ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, cxgbe_media_status); pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, -1); if (pi->dev == NULL) { device_printf(dev, "failed to add device for port %d.\n", i); rc = ENXIO; goto done; } pi->vi[0].dev = pi->dev; device_set_softc(pi->dev, pi); } /* * Interrupt type, # of interrupts, # of rx/tx queues, etc. */ rc = cfg_itype_and_nqueues(sc, &iaq); if (rc != 0) goto done; /* error message displayed already */ sc->intr_type = iaq.intr_type; sc->intr_count = iaq.nirq; s = &sc->sge; s->nrxq = sc->params.nports * iaq.nrxq; s->ntxq = sc->params.nports * iaq.ntxq; s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ s->neq += sc->params.nports; /* ctrl queues: 1 per port */ s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, M_ZERO | M_WAITOK); s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, M_ZERO | M_WAITOK); s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, M_ZERO | M_WAITOK); s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, M_ZERO | M_WAITOK); sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, M_ZERO | M_WAITOK); /* * Second pass over the ports. This time we know the number of rx and * tx queues that each port should get. */ rqidx = tqidx = 0; for_each_port(sc, i) { struct port_info *pi = sc->port[i]; struct vi_info *vi; if (pi == NULL) continue; for_each_vi(pi, j, vi) { vi->pi = pi; vi->adapter = sc; vi->qsize_rxq = t4_qsize_rxq; vi->qsize_txq = t4_qsize_txq; vi->first_rxq = rqidx; vi->first_txq = tqidx; vi->tmr_idx = t4_tmr_idx; vi->pktc_idx = t4_pktc_idx; vi->nrxq = j == 0 ? iaq.nrxq: 1; vi->ntxq = j == 0 ? iaq.ntxq: 1; rqidx += vi->nrxq; tqidx += vi->ntxq; vi->rsrv_noflowq = 0; } } rc = t4_setup_intr_handlers(sc); if (rc != 0) { device_printf(dev, "failed to setup interrupt handlers: %d\n", rc); goto done; } rc = bus_generic_attach(dev); if (rc != 0) { device_printf(dev, "failed to attach all child ports: %d\n", rc); goto done; } device_printf(dev, "%d ports, %d %s interrupt%s, %d eq, %d iq\n", sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); done: if (rc != 0) t4_detach_common(dev); else t4_sysctls(sc); return (rc); } static void get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) { /* 0x3f is used as the revision for VFs. */ regs->version = chip_id(sc) | (0x3f << 10); t4_get_regs(sc, buf, regs->len); } static void t4_clr_vi_stats(struct adapter *sc) { int reg; for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) t4_write_reg(sc, VF_MPS_REG(reg), 0); } static int t4vf_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, struct thread *td) { int rc; struct adapter *sc = dev->si_drv1; rc = priv_check(td, PRIV_DRIVER); if (rc != 0) return (rc); switch (cmd) { case CHELSIO_T4_GETREG: { struct t4_reg *edata = (struct t4_reg *)data; if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) return (EFAULT); if (edata->size == 4) edata->val = t4_read_reg(sc, edata->addr); else if (edata->size == 8) edata->val = t4_read_reg64(sc, edata->addr); else return (EINVAL); break; } case CHELSIO_T4_SETREG: { struct t4_reg *edata = (struct t4_reg *)data; if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) return (EFAULT); if (edata->size == 4) { if (edata->val & 0xffffffff00000000) return (EINVAL); t4_write_reg(sc, edata->addr, (uint32_t) edata->val); } else if (edata->size == 8) t4_write_reg64(sc, edata->addr, edata->val); else return (EINVAL); break; } case CHELSIO_T4_REGDUMP: { struct t4_regdump *regs = (struct t4_regdump *)data; int reglen = t4_get_regs_len(sc); uint8_t *buf; if (regs->len < reglen) { regs->len = reglen; /* hint to the caller */ return (ENOBUFS); } regs->len = reglen; buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); get_regs(sc, regs, buf); rc = copyout(buf, regs->data, reglen); free(buf, M_CXGBE); break; } case CHELSIO_T4_CLEAR_STATS: { int i, v; u_int port_id = *(uint32_t *)data; struct port_info *pi; struct vi_info *vi; if (port_id >= sc->params.nports) return (EINVAL); pi = sc->port[port_id]; /* MAC stats */ pi->tx_parse_error = 0; t4_clr_vi_stats(sc); /* * Since this command accepts a port, clear stats for * all VIs on this port. */ for_each_vi(pi, v, vi) { if (vi->flags & VI_INIT_DONE) { struct sge_rxq *rxq; struct sge_txq *txq; for_each_rxq(vi, i, rxq) { #if defined(INET) || defined(INET6) rxq->lro.lro_queued = 0; rxq->lro.lro_flushed = 0; #endif rxq->rxcsum = 0; rxq->vlan_extraction = 0; } for_each_txq(vi, i, txq) { txq->txcsum = 0; txq->tso_wrs = 0; txq->vlan_insertion = 0; txq->imm_wrs = 0; txq->sgl_wrs = 0; txq->txpkt_wrs = 0; txq->txpkts0_wrs = 0; txq->txpkts1_wrs = 0; txq->txpkts0_pkts = 0; txq->txpkts1_pkts = 0; mp_ring_reset_stats(txq->r); } } } break; } case CHELSIO_T4_SCHED_CLASS: rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); break; case CHELSIO_T4_SCHED_QUEUE: rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); break; default: rc = ENOTTY; } return (rc); } static device_method_t t4vf_methods[] = { DEVMETHOD(device_probe, t4vf_probe), DEVMETHOD(device_attach, t4vf_attach), DEVMETHOD(device_detach, t4_detach_common), DEVMETHOD_END }; static driver_t t4vf_driver = { "t4vf", t4vf_methods, sizeof(struct adapter) }; static device_method_t t5vf_methods[] = { DEVMETHOD(device_probe, t5vf_probe), DEVMETHOD(device_attach, t4vf_attach), DEVMETHOD(device_detach, t4_detach_common), DEVMETHOD_END }; static driver_t t5vf_driver = { "t5vf", t5vf_methods, sizeof(struct adapter) }; static device_method_t t6vf_methods[] = { DEVMETHOD(device_probe, t6vf_probe), DEVMETHOD(device_attach, t4vf_attach), DEVMETHOD(device_detach, t4_detach_common), DEVMETHOD_END }; static driver_t t6vf_driver = { "t6vf", t6vf_methods, sizeof(struct adapter) }; static driver_t cxgbev_driver = { "cxgbev", cxgbe_methods, sizeof(struct port_info) }; static driver_t cxlv_driver = { "cxlv", cxgbe_methods, sizeof(struct port_info) }; static driver_t ccv_driver = { "ccv", cxgbe_methods, sizeof(struct port_info) }; static devclass_t t4vf_devclass, t5vf_devclass, t6vf_devclass; static devclass_t cxgbev_devclass, cxlv_devclass, ccv_devclass; DRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0); MODULE_VERSION(t4vf, 1); MODULE_DEPEND(t4vf, t4nex, 1, 1, 1); DRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0); MODULE_VERSION(t5vf, 1); MODULE_DEPEND(t5vf, t5nex, 1, 1, 1); DRIVER_MODULE(t6vf, pci, t6vf_driver, t6vf_devclass, 0, 0); MODULE_VERSION(t6vf, 1); MODULE_DEPEND(t6vf, t6nex, 1, 1, 1); DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0); MODULE_VERSION(cxgbev, 1); DRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0); MODULE_VERSION(cxlv, 1); DRIVER_MODULE(ccv, t6vf, ccv_driver, ccv_devclass, 0, 0); MODULE_VERSION(ccv, 1);