Index: stable/12/sys/arm/mv/mv_ap806_clock.c =================================================================== --- stable/12/sys/arm/mv/mv_ap806_clock.c (revision 367204) +++ stable/12/sys/arm/mv/mv_ap806_clock.c (revision 367205) @@ -1,210 +1,210 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include -#include +#include +#include #include #include -#include +#include "syscon_if.h" + static struct clk_fixed_def ap806_clk_cluster_0 = { .clkdef.id = 0, .clkdef.name = "ap806-cpu-cluster-0", .freq = 0, }; static struct clk_fixed_def ap806_clk_cluster_1 = { .clkdef.id = 1, .clkdef.name = "ap806-cpu-cluster-1", .freq = 0, }; static struct clk_fixed_def ap806_clk_fixed = { .clkdef.id = 2, .clkdef.name = "ap806-fixed", .freq = 1200000000, }; /* Thoses are the only exported clocks AFAICT */ static const char *mss_parents[] = {"ap806-fixed"}; static struct clk_fixed_def ap806_clk_mss = { .clkdef.id = 3, .clkdef.name = "ap806-mss", .clkdef.parent_names = mss_parents, .clkdef.parent_cnt = 1, .mult = 1, .div = 6, }; static const char *sdio_parents[] = {"ap806-fixed"}; static struct clk_fixed_def ap806_clk_sdio = { .clkdef.id = 4, .clkdef.name = "ap806-sdio", .clkdef.parent_names = sdio_parents, .clkdef.parent_cnt = 1, .mult = 1, .div = 3, }; struct mv_ap806_clock_softc { - struct simplebus_softc simplebus_sc; device_t dev; - struct resource *res; + struct syscon *syscon; }; -static struct resource_spec mv_ap806_clock_res_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, - { -1, 0 } -}; + static struct ofw_compat_data compat_data[] = { - {"marvell,ap806-clock", 1}, - {NULL, 0} + {"marvell,ap806-clock", 1}, + {NULL, 0} }; -#define RD4(sc, reg) bus_read_4((sc)->res, (reg)) -#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) +#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) +#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) static int mv_ap806_clock_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell AP806 Clock Controller"); return (BUS_PROBE_DEFAULT); } static int mv_ap806_clock_attach(device_t dev) { struct mv_ap806_clock_softc *sc; struct clkdom *clkdom; uint64_t clock_freq; uint32_t reg; sc = device_get_softc(dev); sc->dev = dev; - if (bus_alloc_resources(dev, mv_ap806_clock_res_spec, &sc->res) != 0) { - device_printf(dev, "cannot allocate resources for device\n"); + if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || + sc->syscon == NULL) { + device_printf(dev, "cannot get syscon for device\n"); return (ENXIO); } /* * We might miss some combinations * Those are the only possible ones on the mcbin */ reg = RD4(sc, 0x400); switch (reg & 0x1f) { case 0x0: case 0x1: clock_freq = 2000000000; break; case 0x6: clock_freq = 1800000000; break; case 0xd: clock_freq = 1600000000; break; case 0x14: clock_freq = 1333000000; break; default: - device_printf(dev, "Cannot guess clock freq with reg %x\n", reg & 0x1f); + device_printf(dev, "Cannot guess clock freq with reg %x\n", + reg & 0x1f); return (ENXIO); break; }; ap806_clk_cluster_0.freq = clock_freq; ap806_clk_cluster_1.freq = clock_freq; clkdom = clkdom_create(dev); clknode_fixed_register(clkdom, &ap806_clk_cluster_0); clknode_fixed_register(clkdom, &ap806_clk_cluster_1); clknode_fixed_register(clkdom, &ap806_clk_fixed); clknode_fixed_register(clkdom, &ap806_clk_mss); clknode_fixed_register(clkdom, &ap806_clk_sdio); clkdom_finit(clkdom); if (bootverbose) clkdom_dump(clkdom); return (0); } static int mv_ap806_clock_detach(device_t dev) { return (EBUSY); } static device_method_t mv_ap806_clock_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mv_ap806_clock_probe), DEVMETHOD(device_attach, mv_ap806_clock_attach), DEVMETHOD(device_detach, mv_ap806_clock_detach), DEVMETHOD_END }; static devclass_t mv_ap806_clock_devclass; static driver_t mv_ap806_clock_driver = { "mv_ap806_clock", mv_ap806_clock_methods, sizeof(struct mv_ap806_clock_softc), }; EARLY_DRIVER_MODULE(mv_ap806_clock, simplebus, mv_ap806_clock_driver, mv_ap806_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); Index: stable/12/sys/arm/mv/mv_ap806_gicp.c =================================================================== --- stable/12/sys/arm/mv/mv_ap806_gicp.c (revision 367204) +++ stable/12/sys/arm/mv/mv_ap806_gicp.c (revision 367205) @@ -1,289 +1,331 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" #define MV_AP806_GICP_MAX_NIRQS 207 struct mv_ap806_gicp_softc { device_t dev; device_t parent; struct resource *res; ssize_t spi_ranges_cnt; uint32_t *spi_ranges; + struct intr_map_data_fdt *parent_map_data; }; static struct ofw_compat_data compat_data[] = { {"marvell,ap806-gicp", 1}, {NULL, 0} }; #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static int mv_ap806_gicp_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell GICP"); return (BUS_PROBE_DEFAULT); } static int mv_ap806_gicp_attach(device_t dev) { struct mv_ap806_gicp_softc *sc; phandle_t node, xref, intr_parent; sc = device_get_softc(dev); sc->dev = dev; node = ofw_bus_get_node(dev); /* Look for our parent */ if ((intr_parent = ofw_bus_find_iparent(node)) == 0) { - device_printf(dev, "Cannot find our parent interrupt controller\n"); + device_printf(dev, + "Cannot find our parent interrupt controller\n"); return (ENXIO); } if ((sc->parent = OF_device_from_xref(intr_parent)) == NULL) { - device_printf(dev, "cannot find parent interrupt controller device\n"); + device_printf(dev, + "cannot find parent interrupt controller device\n"); return (ENXIO); } sc->spi_ranges_cnt = OF_getencprop_alloc(node, "marvell,spi-ranges", (void **)&sc->spi_ranges); xref = OF_xref_from_node(node); if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "Cannot register GICP\n"); return (ENXIO); } - + /* Allocate GIC compatible mapping entry (3 cells) */ + sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data( + INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) + + + 3 * sizeof(phandle_t), M_WAITOK | M_ZERO); OF_device_register_xref(xref, dev); return (0); } static int mv_ap806_gicp_detach(device_t dev) { return (EBUSY); } +static struct intr_map_data * +mv_ap806_gicp_convert_map_data(struct mv_ap806_gicp_softc *sc, + struct intr_map_data *data) +{ + struct intr_map_data_fdt *daf; + uint32_t i, irq_num, irq_type; + + daf = (struct intr_map_data_fdt *)data; + if (daf->ncells != 2) + return (NULL); + + irq_num = daf->cells[0]; + irq_type = daf->cells[1]; + if (irq_num >= MV_AP806_GICP_MAX_NIRQS) + return (NULL); + + /* Construct GIC compatible mapping. */ + sc->parent_map_data->ncells = 3; + sc->parent_map_data->cells[0] = 0; /* SPI */ + sc->parent_map_data->cells[2] = irq_type; + + /* Map the interrupt number to SPI number */ + for (i = 0; i < sc->spi_ranges_cnt / 2; i += 2) { + if (irq_num < sc->spi_ranges[i + 1]) { + irq_num += sc->spi_ranges[i]; + break; + } + + irq_num -= sc->spi_ranges[i]; + } + + sc->parent_map_data->cells[1] = irq_num - 32; + + return ((struct intr_map_data *)sc->parent_map_data); +} + + + + static int mv_ap806_gicp_activate_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); + data = mv_ap806_gicp_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data)); } static void mv_ap806_gicp_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); PIC_ENABLE_INTR(sc->parent, isrc); } static void mv_ap806_gicp_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); PIC_DISABLE_INTR(sc->parent, isrc); } static int mv_ap806_gicp_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { struct mv_ap806_gicp_softc *sc; - struct intr_map_data_fdt *daf; - uint32_t group, irq_num, irq_type; - int i; + int ret; sc = device_get_softc(dev); if (data->type != INTR_MAP_DATA_FDT) return (ENOTSUP); - daf = (struct intr_map_data_fdt *)data; - if (daf->ncells != 3 || daf->cells[0] >= MV_AP806_GICP_MAX_NIRQS) + data = mv_ap806_gicp_convert_map_data(sc, data); + if (data == NULL) return (EINVAL); - group = daf->cells[0]; - irq_num = daf->cells[1]; - irq_type = daf->cells[2]; - - /* Map the interrupt number to spi number */ - for (i = 0; i < sc->spi_ranges_cnt / 2; i += 2) { - if (irq_num < sc->spi_ranges[i + 1]) { - irq_num += sc->spi_ranges[i]; - break; - } - - irq_num -= sc->spi_ranges[i]; - } - - daf->cells[1] = irq_num - 32; - - return (PIC_MAP_INTR(sc->parent, data, isrcp)); + ret = PIC_MAP_INTR(sc->parent, data, isrcp); + (*isrcp)->isrc_dev = sc->dev; + return(ret); } static int mv_ap806_gicp_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); + data = mv_ap806_gicp_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); + return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data)); } static int mv_ap806_gicp_setup_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); + data = mv_ap806_gicp_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_SETUP_INTR(sc->parent, isrc, res, data)); } static int mv_ap806_gicp_teardown_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); + data = mv_ap806_gicp_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data)); } static void mv_ap806_gicp_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); PIC_PRE_ITHREAD(sc->parent, isrc); } static void mv_ap806_gicp_post_ithread(device_t dev, struct intr_irqsrc *isrc) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); PIC_POST_ITHREAD(sc->parent, isrc); } static void mv_ap806_gicp_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct mv_ap806_gicp_softc *sc; sc = device_get_softc(dev); PIC_POST_FILTER(sc->parent, isrc); } static device_method_t mv_ap806_gicp_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mv_ap806_gicp_probe), DEVMETHOD(device_attach, mv_ap806_gicp_attach), DEVMETHOD(device_detach, mv_ap806_gicp_detach), /* Interrupt controller interface */ DEVMETHOD(pic_activate_intr, mv_ap806_gicp_activate_intr), DEVMETHOD(pic_disable_intr, mv_ap806_gicp_disable_intr), DEVMETHOD(pic_enable_intr, mv_ap806_gicp_enable_intr), DEVMETHOD(pic_map_intr, mv_ap806_gicp_map_intr), DEVMETHOD(pic_deactivate_intr, mv_ap806_gicp_deactivate_intr), DEVMETHOD(pic_setup_intr, mv_ap806_gicp_setup_intr), DEVMETHOD(pic_teardown_intr, mv_ap806_gicp_teardown_intr), DEVMETHOD(pic_post_filter, mv_ap806_gicp_post_filter), DEVMETHOD(pic_post_ithread, mv_ap806_gicp_post_ithread), DEVMETHOD(pic_pre_ithread, mv_ap806_gicp_pre_ithread), DEVMETHOD_END }; static devclass_t mv_ap806_gicp_devclass; static driver_t mv_ap806_gicp_driver = { "mv_ap806_gicp", mv_ap806_gicp_methods, sizeof(struct mv_ap806_gicp_softc), }; EARLY_DRIVER_MODULE(mv_ap806_gicp, simplebus, mv_ap806_gicp_driver, mv_ap806_gicp_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Index: stable/12/sys/arm/mv/mv_ap806_sei.c =================================================================== --- stable/12/sys/arm/mv/mv_ap806_sei.c (nonexistent) +++ stable/12/sys/arm/mv/mv_ap806_sei.c (revision 367205) @@ -0,0 +1,419 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Michal Meloun + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include "pic_if.h" + +#define MV_AP806_SEI_LOCK(_sc) mtx_lock(&(_sc)->mtx) +#define MV_AP806_SEI_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) +#define MV_AP806_SEI_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \ + device_get_nameunit(_sc->dev), "mv_ap806_sei", MTX_DEF) +#define MV_AP806_SEI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); +#define MV_AP806_SEI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); +#define MV_AP806_SEI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED); + +#define MV_AP806_SEI_MAX_NIRQS 64 +#define GICP_SECR0 0x00 +#define GICP_SECR1 0x04 +#define GICP_SECR(i) (0x00 + (((i)/32) * 0x4)) +#define GICP_SECR_BIT(i) ((i) % 32) +#define GICP_SEMR0 0x20 +#define GICP_SEMR1 0x24 +#define GICP_SEMR(i) (0x20 + (((i)/32) * 0x4)) +#define GICP_SEMR_BIT(i) ((i) % 32) + + + +struct mv_ap806_sei_irqsrc { + struct intr_irqsrc isrc; + u_int irq; +}; + +struct mv_ap806_sei_softc { + device_t dev; + struct resource *mem_res; + struct resource *irq_res; + void *irq_ih; + struct mtx mtx; + + struct mv_ap806_sei_irqsrc *isrcs; +}; + +static struct ofw_compat_data compat_data[] = { + {"marvell,ap806-sei", 1}, + {NULL, 0} +}; + +#define RD4(sc, reg) bus_read_4((sc)->mem_res, (reg)) +#define WR4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val)) + +static inline void +mv_ap806_sei_isrc_mask(struct mv_ap806_sei_softc *sc, + struct mv_ap806_sei_irqsrc *sisrc, uint32_t val) +{ + uint32_t tmp; + int bit; + + bit = GICP_SEMR_BIT(sisrc->irq); + MV_AP806_SEI_LOCK(sc); + tmp = RD4(sc, GICP_SEMR(sisrc->irq)); + if (val != 0) + tmp |= 1 << bit; + else + tmp &= ~(1 << bit); + WR4(sc, GICP_SEMR(sisrc->irq), tmp); + MV_AP806_SEI_UNLOCK(sc); +} + +static inline void +mv_ap806_sei_isrc_eoi(struct mv_ap806_sei_softc *sc, + struct mv_ap806_sei_irqsrc *sisrc) +{ + + WR4(sc, GICP_SECR(sisrc->irq), GICP_SECR_BIT(sisrc->irq)); +} + +static void +mv_ap806_sei_enable_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + mv_ap806_sei_isrc_mask(sc, sisrc, 0); +} + +static void +mv_ap806_sei_disable_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + mv_ap806_sei_isrc_mask(sc, sisrc, 1); +} + +static int +mv_ap806_sei_map(device_t dev, struct intr_map_data *data, u_int *irqp) +{ + struct mv_ap806_sei_softc *sc; + struct intr_map_data_fdt *daf; + u_int irq; + + sc = device_get_softc(dev); + + if (data->type != INTR_MAP_DATA_FDT) + return (ENOTSUP); + + daf = (struct intr_map_data_fdt *)data; + if (daf->ncells != 1 || daf->cells[0] >= MV_AP806_SEI_MAX_NIRQS) + return (EINVAL); + irq = daf->cells[0]; + if (irqp != NULL) + *irqp = irq; + + return(0); +} + +static int +mv_ap806_sei_map_intr(device_t dev, struct intr_map_data *data, + struct intr_irqsrc **isrcp) +{ + struct mv_ap806_sei_softc *sc; + u_int irq; + int rv; + + sc = device_get_softc(dev); + rv = mv_ap806_sei_map(dev, data, &irq); + if (rv == 0) + *isrcp = &sc->isrcs[irq].isrc; + + return (rv); +} + + + +static int +mv_ap806_sei_setup_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + u_int irq; + int rv; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + if (data == NULL) + return (ENOTSUP); + rv = mv_ap806_sei_map(dev, data, &irq); + if (rv != 0) + return (rv); + if (irq != sisrc->irq) + return (EINVAL); + mv_ap806_sei_isrc_mask(sc, sisrc, 0); + return (0); +} + +static int +mv_ap806_sei_teardown_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + + mv_ap806_sei_isrc_mask(sc, sisrc, 1); + return (0); +} + +static void +mv_ap806_sei_pre_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + + mv_ap806_sei_isrc_mask(sc, sisrc, 1); + mv_ap806_sei_isrc_eoi(sc, sisrc); +} + +static void +mv_ap806_sei_post_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + + mv_ap806_sei_isrc_mask(sc, sisrc, 1); +} + +static void +mv_ap806_sei_post_filter(device_t dev, struct intr_irqsrc *isrc) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sisrc; + + sc = device_get_softc(dev); + sisrc = (struct mv_ap806_sei_irqsrc *)isrc; + + mv_ap806_sei_isrc_mask(sc, sisrc, 1); + mv_ap806_sei_isrc_eoi(sc, sisrc); +} + +/* ---------------------------------------------------------------------------- + * + * B u s i n t e r f a c e + */ +static int +mv_ap806_sei_intr(void *arg) +{ + struct mv_ap806_sei_softc *sc; + struct mv_ap806_sei_irqsrc *sirq; + struct trapframe *tf; + uint64_t cause; + u_int irq; + + sc = (struct mv_ap806_sei_softc *)arg; + tf = curthread->td_intr_frame; + while (1) { + cause = RD4(sc, GICP_SECR1); + cause <<= 32; + cause |= RD4(sc, GICP_SECR0); + + irq = ffsll(cause); + if (irq == 0) break; + irq--; + sirq = &sc->isrcs[irq]; + if (intr_isrc_dispatch(&sirq->isrc, tf) != 0) { + mv_ap806_sei_isrc_mask(sc, sirq, 0); + mv_ap806_sei_isrc_eoi(sc, sirq); + device_printf(sc->dev, + "Stray irq %u disabled\n", irq); + } + } + + return (FILTER_HANDLED); +} + + +static int +mv_ap806_sei_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Marvell SEI"); + return (BUS_PROBE_DEFAULT); +} + +static int +mv_ap806_sei_attach(device_t dev) +{ + struct mv_ap806_sei_softc *sc; + phandle_t xref, node; + uint32_t irq; + const char *name; + int rv, rid; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + MV_AP806_SEI_LOCK_INIT(sc); + + /* Allocate resources. */ + rid = 0; + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "Cannot allocate memory resources\n"); + rv = ENXIO; + goto fail; + } + + rid = 0; + sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); + if (sc->irq_res == NULL) { + device_printf(dev, "Cannot allocate IRQ resources\n"); + rv = ENXIO; + goto fail; + } + + /* Mask all interrupts) */ + WR4(sc, GICP_SEMR0, 0xFFFFFFFF); + WR4(sc, GICP_SEMR1, 0xFFFFFFFF); + + /* Create all interrupt sources */ + sc->isrcs = malloc(sizeof(*sc->isrcs) * MV_AP806_SEI_MAX_NIRQS, + M_DEVBUF, M_WAITOK | M_ZERO); + name = device_get_nameunit(sc->dev); + for (irq = 0; irq < MV_AP806_SEI_MAX_NIRQS; irq++) { + sc->isrcs[irq].irq = irq; + rv = intr_isrc_register(&sc->isrcs[irq].isrc, + sc->dev, 0, "%s,%u", name, irq); + if (rv != 0) + goto fail; /* XXX deregister ISRCs */ + } + xref = OF_xref_from_node(node);; + if (intr_pic_register(dev, xref) == NULL) { + device_printf(dev, "Cannot register SEI\n"); + rv = ENXIO; + goto fail; + } + if (bus_setup_intr(dev, sc->irq_res,INTR_TYPE_MISC | INTR_MPSAFE, + mv_ap806_sei_intr, NULL, sc, &sc->irq_ih)) { + device_printf(dev, + "Unable to register interrupt handler\n"); + rv = ENXIO; + goto fail; + } + + OF_device_register_xref(xref, dev); + return (0); + +fail: + if (sc->irq_ih != NULL) + bus_teardown_intr(dev, sc->irq_res, sc->irq_ih); + if (sc->irq_res != NULL) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); + if (sc->mem_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); + MV_AP806_SEI_LOCK_DESTROY(sc); + return (ENXIO); +} + +static int +mv_ap806_sei_detach(device_t dev) +{ + + return (EBUSY); +} + + +static device_method_t mv_ap806_sei_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, mv_ap806_sei_probe), + DEVMETHOD(device_attach, mv_ap806_sei_attach), + DEVMETHOD(device_detach, mv_ap806_sei_detach), + + /* Interrupt controller interface */ + DEVMETHOD(pic_disable_intr, mv_ap806_sei_disable_intr), + DEVMETHOD(pic_enable_intr, mv_ap806_sei_enable_intr), + DEVMETHOD(pic_map_intr, mv_ap806_sei_map_intr), + DEVMETHOD(pic_setup_intr, mv_ap806_sei_setup_intr), + DEVMETHOD(pic_teardown_intr, mv_ap806_sei_teardown_intr), + DEVMETHOD(pic_post_filter, mv_ap806_sei_post_filter), + DEVMETHOD(pic_post_ithread, mv_ap806_sei_post_ithread), + DEVMETHOD(pic_pre_ithread, mv_ap806_sei_pre_ithread), + + DEVMETHOD_END +}; + +static devclass_t mv_ap806_sei_devclass; + +static driver_t mv_ap806_sei_driver = { + "mv_ap806_sei", + mv_ap806_sei_methods, + sizeof(struct mv_ap806_sei_softc), +}; + +EARLY_DRIVER_MODULE(mv_ap806_sei, simplebus, mv_ap806_sei_driver, + mv_ap806_sei_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Property changes on: stable/12/sys/arm/mv/mv_ap806_sei.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/arm/mv/mv_cp110_clock.c =================================================================== --- stable/12/sys/arm/mv/mv_cp110_clock.c (revision 367204) +++ stable/12/sys/arm/mv/mv_cp110_clock.c (revision 367205) @@ -1,375 +1,371 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include -#include +#include +#include +#include #include #include -#include -#include - #include #include "clkdev_if.h" +#include "syscon_if.h" /* Clocks */ static struct clk_fixed_def cp110_clk_pll_0 = { .clkdef.id = CP110_PLL_0, .freq = 1000000000, }; static const char *clk_parents_0[] = {"cp110-pll0-0"}; static const char *clk_parents_1[] = {"cp110-pll0-1"}; static struct clk_fixed_def cp110_clk_ppv2_core = { .clkdef.id = CP110_PPV2_CORE, .clkdef.parent_cnt = 1, .mult = 1, .div = 3, }; static struct clk_fixed_def cp110_clk_x2core = { .clkdef.id = CP110_X2CORE, .clkdef.parent_cnt = 1, .mult = 1, .div = 2, }; static const char *core_parents_0[] = {"cp110-x2core-0"}; static const char *core_parents_1[] = {"cp110-x2core-1"}; static struct clk_fixed_def cp110_clk_core = { .clkdef.id = CP110_CORE, .clkdef.parent_cnt = 1, .mult = 1, .div = 2, }; static struct clk_fixed_def cp110_clk_sdio = { .clkdef.id = CP110_SDIO, .clkdef.parent_cnt = 1, .mult = 2, .div = 5, }; /* Gates */ static struct cp110_gate cp110_gates[] = { CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0) CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1) /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */ CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3) CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4) CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5) CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6) CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7) CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8) CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9) CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11) CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12) CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13) CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14) CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15) CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16) CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17) CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18) CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21) CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22) CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23) CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24) CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25) CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26) }; struct mv_cp110_clock_softc { - struct simplebus_softc simplebus_sc; device_t dev; - struct resource *res; + struct syscon *syscon; struct mtx mtx; }; -static struct resource_spec mv_cp110_clock_res_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, - { -1, 0 } -}; static struct ofw_compat_data compat_data[] = { {"marvell,cp110-clock", 1}, {NULL, 0} }; -#define RD4(sc, reg) bus_read_4((sc)->res, (reg)) -#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) +#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) +#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) static char * mv_cp110_clock_name(device_t dev, const char *name) { char *clkname = NULL; int unit; unit = device_get_unit(dev); if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0) panic("Cannot generate unique clock name for %s\n", name); return (clkname); } static int mv_cp110_clock_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell CP110 Clock Controller"); return (BUS_PROBE_DEFAULT); } static int cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells, phandle_t *cells, struct clknode **clk) { int id = 0; if (ncells != 2) return (ENXIO); id = cells[1]; if (cells[0] == 1) id += CP110_MAX_CLOCK; *clk = clknode_find_by_id(clkdom, id); return (0); } static int mv_cp110_clock_attach(device_t dev) { struct mv_cp110_clock_softc *sc; struct clkdom *clkdom; struct clk_gate_def def; char *pll0_name; int unit, i; sc = device_get_softc(dev); sc->dev = dev; - if (bus_alloc_resources(dev, mv_cp110_clock_res_spec, &sc->res) != 0) { - device_printf(dev, "cannot allocate resources for device\n"); + if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || + sc->syscon == NULL) { + device_printf(dev, "cannot get syscon for device\n"); return (ENXIO); } unit = device_get_unit(dev); if (unit > 1) { device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit); return (ENXIO); } mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); clkdom = clkdom_create(dev); clkdom_set_ofw_mapper(clkdom, cp110_ofw_map); pll0_name = mv_cp110_clock_name(dev, "cp110-pll0"); cp110_clk_pll_0.clkdef.name = pll0_name; clknode_fixed_register(clkdom, &cp110_clk_pll_0); cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2"); cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; clknode_fixed_register(clkdom, &cp110_clk_ppv2_core); cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core"); cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; clknode_fixed_register(clkdom, &cp110_clk_x2core); cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core"); cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1; clknode_fixed_register(clkdom, &cp110_clk_core); /* NAND missing */ cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio"); cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; clknode_fixed_register(clkdom, &cp110_clk_sdio); for (i = 0; i < nitems(cp110_gates); i++) { if (cp110_gates[i].name == NULL) continue; memset(&def, 0, sizeof(def)); def.clkdef.id = CP110_MAX_CLOCK + i; def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name); def.clkdef.parent_cnt = 1; def.offset = CP110_CLOCK_GATING_OFFSET; def.shift = cp110_gates[i].shift; def.mask = 1; def.on_value = 1; def.off_value = 0; switch (i) { case CP110_GATE_MG: case CP110_GATE_GOP_DP: case CP110_GATE_PPV2: def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name; break; case CP110_GATE_SDIO: def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name; break; case CP110_GATE_MAIN: case CP110_GATE_PCIE_XOR: case CP110_GATE_PCIE_X4: case CP110_GATE_EIP150: case CP110_GATE_EIP197: def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name; break; default: def.clkdef.parent_names = &cp110_clk_core.clkdef.name; break; } clknode_gate_register(clkdom, &def); } clkdom_finit(clkdom); if (bootverbose) clkdom_dump(clkdom); return (0); } static int mv_cp110_clock_detach(device_t dev) { return (EBUSY); } static int mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val) { struct mv_cp110_clock_softc *sc; sc = device_get_softc(dev); WR4(sc, addr, val); return (0); } static int mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val) { struct mv_cp110_clock_softc *sc; sc = device_get_softc(dev); *val = RD4(sc, addr); return (0); } static int mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) { struct mv_cp110_clock_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = RD4(sc, addr); reg &= ~clr; reg |= set; WR4(sc, addr, reg); return (0); } static void mv_cp110_clock_device_lock(device_t dev) { struct mv_cp110_clock_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->mtx); } static void mv_cp110_clock_device_unlock(device_t dev) { struct mv_cp110_clock_softc *sc; sc = device_get_softc(dev); mtx_unlock(&sc->mtx); } static device_method_t mv_cp110_clock_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mv_cp110_clock_probe), DEVMETHOD(device_attach, mv_cp110_clock_attach), DEVMETHOD(device_detach, mv_cp110_clock_detach), /* clkdev interface */ DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4), DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4), DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4), DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock), DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock), DEVMETHOD_END }; static devclass_t mv_cp110_clock_devclass; static driver_t mv_cp110_clock_driver = { "mv_cp110_clock", mv_cp110_clock_methods, sizeof(struct mv_cp110_clock_softc), }; EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver, mv_cp110_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); Index: stable/12/sys/arm/mv/mv_cp110_icu.c =================================================================== --- stable/12/sys/arm/mv/mv_cp110_icu.c (revision 367204) +++ stable/12/sys/arm/mv/mv_cp110_icu.c (revision 367205) @@ -1,299 +1,357 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include "pic_if.h" #define ICU_GRP_NSR 0x0 #define ICU_GRP_SR 0x1 #define ICU_GRP_SEI 0x4 #define ICU_GRP_REI 0x5 #define ICU_SETSPI_NSR_AL 0x10 #define ICU_SETSPI_NSR_AH 0x14 #define ICU_CLRSPI_NSR_AL 0x18 #define ICU_CLRSPI_NSR_AH 0x1c #define ICU_INT_CFG(x) (0x100 + (x) * 4) #define ICU_INT_ENABLE (1 << 24) #define ICU_INT_EDGE (1 << 28) #define ICU_INT_GROUP_SHIFT 29 #define ICU_INT_MASK 0x3ff #define MV_CP110_ICU_MAX_NIRQS 207 struct mv_cp110_icu_softc { device_t dev; device_t parent; struct resource *res; + struct intr_map_data_fdt *parent_map_data; }; static struct resource_spec mv_cp110_icu_res_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static struct ofw_compat_data compat_data[] = { - {"marvell,cp110-icu", 1}, - {NULL, 0} + {"marvell,cp110-icu-nsr", 1}, + {"marvell,cp110-icu-sei", 2}, + {NULL, 0} }; #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static int mv_cp110_icu_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell Interrupt Consolidation Unit"); return (BUS_PROBE_DEFAULT); } static int mv_cp110_icu_attach(device_t dev) { struct mv_cp110_icu_softc *sc; phandle_t node, msi_parent; sc = device_get_softc(dev); sc->dev = dev; node = ofw_bus_get_node(dev); if (OF_getencprop(node, "msi-parent", &msi_parent, sizeof(phandle_t)) <= 0) { device_printf(dev, "cannot find msi-parent property\n"); return (ENXIO); } if ((sc->parent = OF_device_from_xref(msi_parent)) == NULL) { device_printf(dev, "cannot find msi-parent device\n"); return (ENXIO); } if (bus_alloc_resources(dev, mv_cp110_icu_res_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "Cannot register ICU\n"); goto fail; } + + /* Allocate GICP compatible mapping entry (2 cells) */ + sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data( + INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) + + + 3 * sizeof(phandle_t), M_WAITOK | M_ZERO); return (0); fail: bus_release_resources(dev, mv_cp110_icu_res_spec, &sc->res); return (ENXIO); } +static struct intr_map_data * +mv_cp110_icu_convert_map_data(struct mv_cp110_icu_softc *sc, struct intr_map_data *data) +{ + struct intr_map_data_fdt *daf; + uint32_t reg, irq_no, irq_type; + + daf = (struct intr_map_data_fdt *)data; + if (daf->ncells != 2) + return (NULL); + irq_no = daf->cells[0]; + irq_type = daf->cells[1]; + if (irq_no >= MV_CP110_ICU_MAX_NIRQS) + return (NULL); + if (irq_type != IRQ_TYPE_LEVEL_HIGH && + irq_type != IRQ_TYPE_EDGE_RISING) + return (NULL); + + /* We rely on fact that ICU->GIC mapping is preset by bootstrap. */ + reg = RD4(sc, ICU_INT_CFG(irq_no)); + + /* Construct GICP compatible mapping. */ + sc->parent_map_data->ncells = 2; + sc->parent_map_data->cells[0] = reg & ICU_INT_MASK; + sc->parent_map_data->cells[1] = irq_type; + + return ((struct intr_map_data *)sc->parent_map_data); +} + + static int mv_cp110_icu_detach(device_t dev) { return (EBUSY); } static int mv_cp110_icu_activate_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); - + data = mv_cp110_icu_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data)); } static void mv_cp110_icu_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mv_cp110_icu_softc *sc; - sc = device_get_softc(dev); PIC_ENABLE_INTR(sc->parent, isrc); } static void mv_cp110_icu_disable_intr(device_t dev, struct intr_irqsrc *isrc) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); PIC_DISABLE_INTR(sc->parent, isrc); } + + static int mv_cp110_icu_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { struct mv_cp110_icu_softc *sc; struct intr_map_data_fdt *daf; - uint32_t reg; + uint32_t reg, irq_no, irq_type; + int ret; sc = device_get_softc(dev); if (data->type != INTR_MAP_DATA_FDT) return (ENOTSUP); + /* Parse original */ daf = (struct intr_map_data_fdt *)data; - if (daf->ncells != 3 || daf->cells[0] >= MV_CP110_ICU_MAX_NIRQS) + if (daf->ncells != 2) return (EINVAL); + irq_no = daf->cells[0]; + irq_type = daf->cells[1]; + data = mv_cp110_icu_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); - reg = RD4(sc, ICU_INT_CFG(daf->cells[1])); + reg = RD4(sc, ICU_INT_CFG(irq_no)); + reg |= ICU_INT_ENABLE; + if (irq_type == IRQ_TYPE_LEVEL_HIGH) + reg &= ~ICU_INT_EDGE; + else + reg |= ICU_INT_EDGE; + WR4(sc, ICU_INT_CFG(irq_no), reg); - if ((reg & ICU_INT_ENABLE) == 0) { - reg |= ICU_INT_ENABLE; - WR4(sc, ICU_INT_CFG(daf->cells[1]), reg); - } - - daf->cells[1] = reg & ICU_INT_MASK; - return (PIC_MAP_INTR(sc->parent, data, isrcp)); + ret = PIC_MAP_INTR(sc->parent, data, isrcp); + (*isrcp)->isrc_dev = sc->dev; + return (ret); } static int mv_cp110_icu_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); + data = mv_cp110_icu_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data)); } static int mv_cp110_icu_setup_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); + data = mv_cp110_icu_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_SETUP_INTR(sc->parent, isrc, res, data)); } static int mv_cp110_icu_teardown_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res, struct intr_map_data *data) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); + data = mv_cp110_icu_convert_map_data(sc, data); + if (data == NULL) + return (EINVAL); return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data)); } static void mv_cp110_icu_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); PIC_PRE_ITHREAD(sc->parent, isrc); } static void mv_cp110_icu_post_ithread(device_t dev, struct intr_irqsrc *isrc) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); PIC_POST_ITHREAD(sc->parent, isrc); } static void mv_cp110_icu_post_filter(device_t dev, struct intr_irqsrc *isrc) { struct mv_cp110_icu_softc *sc; sc = device_get_softc(dev); PIC_POST_FILTER(sc->parent, isrc); } static device_method_t mv_cp110_icu_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mv_cp110_icu_probe), DEVMETHOD(device_attach, mv_cp110_icu_attach), DEVMETHOD(device_detach, mv_cp110_icu_detach), /* Interrupt controller interface */ DEVMETHOD(pic_activate_intr, mv_cp110_icu_activate_intr), DEVMETHOD(pic_disable_intr, mv_cp110_icu_disable_intr), DEVMETHOD(pic_enable_intr, mv_cp110_icu_enable_intr), DEVMETHOD(pic_map_intr, mv_cp110_icu_map_intr), DEVMETHOD(pic_deactivate_intr, mv_cp110_icu_deactivate_intr), DEVMETHOD(pic_setup_intr, mv_cp110_icu_setup_intr), DEVMETHOD(pic_teardown_intr, mv_cp110_icu_teardown_intr), DEVMETHOD(pic_post_filter, mv_cp110_icu_post_filter), DEVMETHOD(pic_post_ithread, mv_cp110_icu_post_ithread), DEVMETHOD(pic_pre_ithread, mv_cp110_icu_pre_ithread), DEVMETHOD_END }; static devclass_t mv_cp110_icu_devclass; static driver_t mv_cp110_icu_driver = { "mv_cp110_icu", mv_cp110_icu_methods, sizeof(struct mv_cp110_icu_softc), }; -EARLY_DRIVER_MODULE(mv_cp110_icu, simplebus, mv_cp110_icu_driver, +EARLY_DRIVER_MODULE(mv_cp110_icu, mv_cp110_icu_bus, mv_cp110_icu_driver, mv_cp110_icu_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); Index: stable/12/sys/arm/mv/mv_cp110_icu_bus.c =================================================================== --- stable/12/sys/arm/mv/mv_cp110_icu_bus.c (nonexistent) +++ stable/12/sys/arm/mv/mv_cp110_icu_bus.c (revision 367205) @@ -0,0 +1,78 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Michal Meloun + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +static struct ofw_compat_data compat_data[] = { + {"marvell,cp110-icu", 1}, + {NULL, 0} +}; + +static int +mv_cp110_icu_bus_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Marvell Interrupt Consolidation Unit Bus"); + return (BUS_PROBE_DEFAULT); +} + +static device_method_t mv_cp110_icu_bus_methods[] = { + DEVMETHOD(device_probe, mv_cp110_icu_bus_probe), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(mv_cp110_icu_bus, mv_cp110_icu_bus_driver, + mv_cp110_icu_bus_methods, sizeof(struct simple_mfd_softc), + simple_mfd_driver); + +static devclass_t mv_cp110_icu_bus_devclass; +EARLY_DRIVER_MODULE(mv_cp110_icu_bus, simplebus, mv_cp110_icu_bus_driver, + mv_cp110_icu_bus_devclass, 0, 0, BUS_PASS_INTERRUPT); +MODULE_VERSION(mv_cp110_icu_bus, 1); Property changes on: stable/12/sys/arm/mv/mv_cp110_icu_bus.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/arm/mv/mv_thermal.c =================================================================== --- stable/12/sys/arm/mv/mv_thermal.c (revision 367204) +++ stable/12/sys/arm/mv/mv_thermal.c (revision 367205) @@ -1,381 +1,382 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include +#include -#include - #include #include -#define CONTROL0 0x00 +#include "syscon_if.h" + +#define CONTROL0 0 /* Offset in config->regs[] array */ #define CONTROL0_TSEN_START (1 << 0) #define CONTROL0_TSEN_RESET (1 << 1) #define CONTROL0_TSEN_EN (1 << 2) #define CONTROL0_CHANNEL_SHIFT 13 #define CONTROL0_CHANNEL_MASK 0xF #define CONTROL0_OSR_SHIFT 24 #define CONTROL0_OSR_MAX 3 /* OSR = 512 * 4uS = ~2mS */ #define CONTROL0_MODE_SHIFT 30 #define CONTROL0_MODE_EXTERNAL 0x2 #define CONTROL0_MODE_MASK 0x3 -#define CONTROL1 0x04 +#define CONTROL1 1 /* Offset in config->regs[] array */ /* This doesn't seems to work */ #define CONTROL1_TSEN_SENS_SHIFT 21 #define CONTROL1_TSEN_SENS_MASK 0x7 -#define STATUS 0x00 +#define STATUS 2 /* Offset in config->regs[] array */ #define STATUS_TEMP_MASK 0x3FF enum mv_thermal_type { MV_AP806 = 1, MV_CP110, }; struct mv_thermal_config { enum mv_thermal_type type; + int regs[3]; int ncpus; int64_t calib_mul; int64_t calib_add; int64_t calib_div; uint32_t valid_mask; bool signed_value; }; struct mv_thermal_softc { device_t dev; - struct resource *res[2]; + struct syscon *syscon; struct mtx mtx; - struct mv_thermal_config *config; - int cur_sensor; + struct mv_thermal_config *config; + int cur_sensor; }; static struct mv_thermal_config mv_ap806_config = { .type = MV_AP806, + .regs = {0x84, 0x88, 0x8C}, .ncpus = 4, .calib_mul = 423, .calib_add = -150000, .calib_div = 100, .valid_mask = (1 << 16), .signed_value = true, }; static struct mv_thermal_config mv_cp110_config = { .type = MV_CP110, + .regs = {0x70, 0x74, 0x78}, .calib_mul = 2000096, .calib_add = 1172499100, .calib_div = 420100, .valid_mask = (1 << 10), .signed_value = false, }; -static struct resource_spec mv_thermal_res_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { SYS_RES_MEMORY, 1, RF_ACTIVE }, - { -1, 0 } -}; - static struct ofw_compat_data compat_data[] = { {"marvell,armada-ap806-thermal", (uintptr_t) &mv_ap806_config}, {"marvell,armada-cp110-thermal", (uintptr_t) &mv_cp110_config}, {NULL, 0} }; -#define RD_STA(sc, reg) bus_read_4((sc)->res[0], (reg)) -#define WR_STA(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) -#define RD_CON(sc, reg) bus_read_4((sc)->res[1], (reg)) -#define WR_CON(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val)) +#define RD4(sc, reg) \ + SYSCON_READ_4((sc)->syscon, sc->config->regs[reg]) +#define WR4(sc, reg, val) \ + SYSCON_WRITE_4((sc)->syscon, sc->config->regs[reg], (val)) static inline int32_t sign_extend(uint32_t value, int index) { uint8_t shift; shift = 31 - index; return ((int32_t)(value << shift) >> shift); } static int mv_thermal_wait_sensor(struct mv_thermal_softc *sc) { uint32_t reg; uint32_t timeout; timeout = 100000; while (--timeout > 0) { - reg = RD_STA(sc, STATUS); + reg = RD4(sc, STATUS); if ((reg & sc->config->valid_mask) == sc->config->valid_mask) break; DELAY(100); } if (timeout == 0) { return (ETIMEDOUT); } return (0); } static int mv_thermal_select_sensor(struct mv_thermal_softc *sc, int sensor) { uint32_t reg; if (sc->cur_sensor == sensor) return (0); /* Stop the current reading and reset the module */ - reg = RD_CON(sc, CONTROL0); + reg = RD4(sc, CONTROL0); reg &= ~(CONTROL0_TSEN_START | CONTROL0_TSEN_EN); - WR_CON(sc, CONTROL0, reg); + WR4(sc, CONTROL0, reg); /* Switch to the selected sensor */ - /* + /* * NOTE : Datasheet says to use CONTROL1 for selecting * but when doing so the sensors >0 are never ready * Do what Linux does using undocumented bits in CONTROL0 */ /* This reset automatically to the sensor 0 */ reg &= ~(CONTROL0_MODE_MASK << CONTROL0_MODE_SHIFT); if (sensor) { /* Select external sensor */ reg |= CONTROL0_MODE_EXTERNAL << CONTROL0_MODE_SHIFT; reg &= ~(CONTROL0_CHANNEL_MASK << CONTROL0_CHANNEL_SHIFT); reg |= (sensor - 1) << CONTROL0_CHANNEL_SHIFT; } - WR_CON(sc, CONTROL0, reg); + WR4(sc, CONTROL0, reg); sc->cur_sensor = sensor; /* Start the reading */ - reg = RD_CON(sc, CONTROL0); + reg = RD4(sc, CONTROL0); reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_EN; - WR_CON(sc, CONTROL0, reg); + WR4(sc, CONTROL0, reg); return (mv_thermal_wait_sensor(sc)); } static int mv_thermal_read_sensor(struct mv_thermal_softc *sc, int sensor, int *temp) { uint32_t reg; int64_t sample, rv; rv = mv_thermal_select_sensor(sc, sensor); if (rv != 0) return (rv); - reg = RD_STA(sc, STATUS) & STATUS_TEMP_MASK; + reg = RD4(sc, STATUS) & STATUS_TEMP_MASK; if (sc->config->signed_value) sample = sign_extend(reg, fls(STATUS_TEMP_MASK) - 1); else sample = reg; *temp = ((sample * sc->config->calib_mul) - sc->config->calib_add) / sc->config->calib_div; return (0); } static int ap806_init(struct mv_thermal_softc *sc) { uint32_t reg; /* Start the temp capture/conversion */ - reg = RD_CON(sc, CONTROL0); + reg = RD4(sc, CONTROL0); reg &= ~CONTROL0_TSEN_RESET; reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_EN; /* Sample every ~2ms */ reg |= CONTROL0_OSR_MAX << CONTROL0_OSR_SHIFT; - WR_CON(sc, CONTROL0, reg); + WR4(sc, CONTROL0, reg); /* Since we just started the module wait for the sensor to be ready */ mv_thermal_wait_sensor(sc); return (0); } static int cp110_init(struct mv_thermal_softc *sc) { uint32_t reg; - reg = RD_CON(sc, CONTROL1); + reg = RD4(sc, CONTROL1); reg &= (1 << 7); reg |= (1 << 8); - WR_CON(sc, CONTROL1, reg); + WR4(sc, CONTROL1, reg); /* Sample every ~2ms */ - reg = RD_CON(sc, CONTROL0); + reg = RD4(sc, CONTROL0); reg |= CONTROL0_OSR_MAX << CONTROL0_OSR_SHIFT; - WR_CON(sc, CONTROL0, reg); + WR4(sc, CONTROL0, reg); return (0); } static int mv_thermal_sysctl(SYSCTL_HANDLER_ARGS) { struct mv_thermal_softc *sc; device_t dev = arg1; int sensor = arg2; int val = 0; sc = device_get_softc(dev); mtx_lock(&(sc)->mtx); if (mv_thermal_read_sensor(sc, sensor, &val) == 0) { /* Convert to Kelvin */ val = val + 2732; } else { device_printf(dev, "Timeout waiting for sensor\n"); } mtx_unlock(&(sc)->mtx); return sysctl_handle_opaque(oidp, &val, sizeof(val), req); } static int mv_thermal_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell Thermal Sensor Controller"); return (BUS_PROBE_DEFAULT); } static int mv_thermal_attach(device_t dev) { struct mv_thermal_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid_list *oid; + phandle_t node; char name[255]; char desc[255]; int i; sc = device_get_softc(dev); sc->dev = dev; + node = ofw_bus_get_node(dev); - sc->config = (struct mv_thermal_config *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; + sc->config = (struct mv_thermal_config *) + ofw_bus_search_compatible(dev, compat_data)->ocd_data; mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); - if (bus_alloc_resources(dev, mv_thermal_res_spec, sc->res) != 0) { - device_printf(dev, "cannot allocate resources for device\n"); + + if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || + sc->syscon == NULL) { + device_printf(dev, "cannot get syscon for device\n"); return (ENXIO); } sc->cur_sensor = -1; switch (sc->config->type) { case MV_AP806: ap806_init(sc); break; case MV_CP110: cp110_init(sc); break; } ctx = device_get_sysctl_ctx(dev); oid = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); /* There is always at least one sensor */ SYSCTL_ADD_PROC(ctx, oid, OID_AUTO, "internal", CTLTYPE_INT | CTLFLAG_RD, dev, 0, mv_thermal_sysctl, "IK", "Internal Temperature"); for (i = 0; i < sc->config->ncpus; i++) { snprintf(name, sizeof(name), "cpu%d", i); snprintf(desc, sizeof(desc), "CPU%d Temperature", i); SYSCTL_ADD_PROC(ctx, oid, OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RD, dev, i + 1, mv_thermal_sysctl, "IK", desc); } return (0); } static int mv_thermal_detach(device_t dev) { struct mv_thermal_softc *sc; sc = device_get_softc(dev); - - bus_release_resources(dev, mv_thermal_res_spec, sc->res); return (0); } static device_method_t mv_thermal_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mv_thermal_probe), DEVMETHOD(device_attach, mv_thermal_attach), DEVMETHOD(device_detach, mv_thermal_detach), DEVMETHOD_END }; static devclass_t mv_thermal_devclass; static driver_t mv_thermal_driver = { "mv_thermal", mv_thermal_methods, sizeof(struct mv_thermal_softc), }; DRIVER_MODULE(mv_thermal, simplebus, mv_thermal_driver, mv_thermal_devclass, 0, 0); Index: stable/12/sys/arm/mv/mvebu_pinctrl.c =================================================================== --- stable/12/sys/arm/mv/mvebu_pinctrl.c (revision 367204) +++ stable/12/sys/arm/mv/mvebu_pinctrl.c (revision 367205) @@ -1,246 +1,240 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include -#include +#include +#include + #include #include -#include +#include "syscon_if.h" -#include "opt_soc.h" - #define PINS_PER_REG 8 #define BITS_PER_PIN 4 #define PINS_MASK 0xf #define MAX_PIN_FUNC 5 struct mv_pins { const char *name; const char *functions[MAX_PIN_FUNC]; }; struct mv_padconf { const struct mv_pins *pins; size_t npins; }; -#ifdef SOC_MARVELL_8K const static struct mv_pins ap806_pins[] = { {"mpp0", {"gpio", "sdio", NULL, "spi0"}}, {"mpp1", {"gpio", "sdio", NULL, "spi0"}}, {"mpp2", {"gpio", "sdio", NULL, "spi0"}}, {"mpp3", {"gpio", "sdio", NULL, "spi0"}}, {"mpp4", {"gpio", "sdio", NULL, "i2c0"}}, {"mpp5", {"gpio", "sdio", NULL, "i2c0"}}, {"mpp6", {"gpio", "sdio", NULL, NULL}}, {"mpp7", {"gpio", "sdio", NULL, "uart1"}}, {"mpp8", {"gpio", "sdio", NULL, "uart1"}}, {"mpp9", {"gpio", "sdio", NULL, "spi0"}}, {"mpp10", {"gpio", "sdio", NULL, NULL}}, {"mpp11", {"gpio", NULL, NULL, "uart0"}}, {"mpp12", {"gpio", "sdio", "sdio", NULL}}, {"mpp13", {"gpio", NULL, NULL}}, {"mpp14", {"gpio", NULL, NULL}}, {"mpp15", {"gpio", NULL, NULL}}, {"mpp16", {"gpio", NULL, NULL}}, {"mpp17", {"gpio", NULL, NULL}}, {"mpp18", {"gpio", NULL, NULL}}, {"mpp19", {"gpio", NULL, NULL, "uart0", "sdio"}}, }; const struct mv_padconf ap806_padconf = { .npins = nitems(ap806_pins), .pins = ap806_pins, }; -#endif struct mv_pinctrl_softc { device_t dev; - struct resource *res; + struct syscon *syscon; struct mv_padconf *padconf; }; -static struct resource_spec mv_pinctrl_res_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, - { -1, 0 } -}; static struct ofw_compat_data compat_data[] = { -#ifdef SOC_MARVELL_8K {"marvell,ap806-pinctrl", (uintptr_t)&ap806_padconf}, -#endif {NULL, 0} }; -#define RD4(sc, reg) bus_read_4((sc)->res, (reg)) -#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) +#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) +#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) static void mv_pinctrl_configure_pin(struct mv_pinctrl_softc *sc, uint32_t pin, uint32_t function) { uint32_t offset, shift, reg; offset = (pin / PINS_PER_REG) * BITS_PER_PIN; shift = (pin % PINS_PER_REG) * BITS_PER_PIN; reg = RD4(sc, offset); reg &= ~(PINS_MASK << shift); reg |= function << shift; WR4(sc, offset, reg); } static int mv_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) { struct mv_pinctrl_softc *sc; phandle_t node; char *function; const char **pins; int i, pin_num, pin_func, npins; sc = device_get_softc(dev); node = OF_node_from_xref(cfgxref); if (OF_getprop_alloc(node, "marvell,function", (void **)&function) == -1) return (ENOMEM); npins = ofw_bus_string_list_to_array(node, "marvell,pins", &pins); if (npins == -1) return (ENOMEM); for (i = 0; i < npins; i++) { for (pin_num = 0; pin_num < sc->padconf->npins; pin_num++) { if (strcmp(pins[i], sc->padconf->pins[pin_num].name) == 0) break; } if (pin_num == sc->padconf->npins) continue; for (pin_func = 0; pin_func < MAX_PIN_FUNC; pin_func++) if (sc->padconf->pins[pin_num].functions[pin_func] && strcmp(function, sc->padconf->pins[pin_num].functions[pin_func]) == 0) break; if (pin_func == MAX_PIN_FUNC) continue; mv_pinctrl_configure_pin(sc, pin_num, pin_func); } OF_prop_free(pins); return (0); } static int mv_pinctrl_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell Pinctrl controller"); return (BUS_PROBE_DEFAULT); } static int mv_pinctrl_attach(device_t dev) { struct mv_pinctrl_softc *sc; phandle_t node; sc = device_get_softc(dev); sc->dev = dev; - sc->padconf = (struct mv_padconf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; + sc->padconf = (struct mv_padconf *) + ofw_bus_search_compatible(dev,compat_data)->ocd_data; - if (bus_alloc_resources(dev, mv_pinctrl_res_spec, &sc->res) != 0) { - device_printf(dev, "cannot allocate resources for device\n"); + if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || + sc->syscon == NULL) { + device_printf(dev, "cannot get syscon for device\n"); return (ENXIO); } node = ofw_bus_get_node(dev); fdt_pinctrl_register(dev, "marvell,pins"); fdt_pinctrl_configure_tree(dev); return (0); } static int mv_pinctrl_detach(device_t dev) { return (EBUSY); } static device_method_t mv_pinctrl_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mv_pinctrl_probe), DEVMETHOD(device_attach, mv_pinctrl_attach), DEVMETHOD(device_detach, mv_pinctrl_detach), /* fdt_pinctrl interface */ DEVMETHOD(fdt_pinctrl_configure,mv_pinctrl_configure_pins), DEVMETHOD_END }; static devclass_t mv_pinctrl_devclass; static driver_t mv_pinctrl_driver = { "mv_pinctrl", mv_pinctrl_methods, sizeof(struct mv_pinctrl_softc), }; EARLY_DRIVER_MODULE(mv_pinctrl, simplebus, mv_pinctrl_driver, mv_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); Index: stable/12/sys/arm64/conf/GENERIC =================================================================== --- stable/12/sys/arm64/conf/GENERIC (revision 367204) +++ stable/12/sys/arm64/conf/GENERIC (revision 367205) @@ -1,319 +1,320 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC # IP (v4/v6) security options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options TCP_RFC7413 # TCP Fast Open options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options COMPAT_FREEBSD32 # Incomplete, but used by cloudabi32.ko. options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options NETDUMP # netdump(4) client support # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_ALLWINNER_H6 options SOC_CAVM_THUNDERX options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 options SOC_BRCM_BCM2838 options SOC_MARVELL_8K options SOC_ROCKCHIP_RK3328 options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure device iflib device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family # Ethernet NICs device mdio device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet device axgbe # AMD Opteron A1100 integrated NIC device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC device dwc_rk # Rockchip Designware device dwc_socfpga # Altera SOCFPGA Ethernet MAC # Block devices device ahci device scbus device da # ATA/SCSI peripherals device cd # CD device pass # Passthrough device (direct ATA/SCSI access) # NVM Express (NVMe) support device nvme # base NVMe driver options NVME_USE_NVD=0 # prefer the cam(4) based nda(4) driver device nvd # expose NVMe namespaces as disks, depends on nvme # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc device dwmmc_altera device rk_emmcphy # Serial (COM) ports device uart # Generic UART driver device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support device aw_usbphy # Allwinner USB PHY device rk_usb2phy # Rockchip USB2PHY device rk_typec_phy # Rockchip TypeC PHY device dwcotg # DWC OTG controller device musb # Mentor Graphics USB OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI PCI->USB interface (USB 3.0) device rk_dwc3 # Rockchip DWC3 controller device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device muge device smcphy device smsc # Sound support device sound device a10_codec # DMA controller device a31_dmac # GPIO / PINCTRL device a37x0_gpio # Marvell Armada 37x0 GPIO controller device aw_gpio # Allwinner GPIO controller device gpio device gpioled device fdt_pinctrl device gpioregulator device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller device rk_gpio # RockChip GPIO Controller device rk_pinctrl # RockChip Pinmux Controller # I2C device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iic device twsi # Allwinner I2C controller device syr827 # Silergy SYR827 PMIC device rk_i2c # RockChip I2C controller # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support device mv_cp110_icu # Marvell CP110 ICU device mv_ap806_gicp # Marvell AP806 GICP +device mv_ap806_sei # Marvell AP806 SEI # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock # Crypto accelerators device safexcel # Inside Secure EIP-97 # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller device mv_thermal # Marvell Thermal Sensor Controller # SPI device spibus device bcm2835_spi # Broadcom BCM283x SPI bus device rk_spi # RockChip SPI controller # PWM device pwm device aw_pwm device rk_pwm # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev # Pseudo devices. device crypto # core crypto support device loop # Network loopback device random # Entropy device device ether # Ethernet support device vlan # 802.1Q VLAN support device tuntap # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module options EFIRT # EFI Runtime Services # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # IO Domains device rk_iodomain # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner dtb/mv dtb/rockchip dtb/rpi" Index: stable/12/sys/conf/files.arm64 =================================================================== --- stable/12/sys/conf/files.arm64 (revision 367204) +++ stable/12/sys/conf/files.arm64 (revision 367205) @@ -1,364 +1,367 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt | random soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt +arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt -arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt -arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt +arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt +arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt +arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt +arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_generic.c optional ahci dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sriov.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01031000 -mice_ddp -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.16.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.16.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc fdt dwmmc_altera dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard dev/psci/smccc.c standard dev/safexcel/safexcel.c optional safexcel fdt dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/musb_otg_allwinner.c optional musb fdt soc_allwinner_a64 dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memcmp.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 Index: stable/12 =================================================================== --- stable/12 (revision 367204) +++ stable/12 (revision 367205) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r353773