Index: head/sys/arm/broadcom/bcm2835/bcm2835_mbox.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_mbox.c (revision 363794) +++ head/sys/arm/broadcom/bcm2835/bcm2835_mbox.c (revision 363795) @@ -1,574 +1,595 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mbox_if.h" #define REG_READ 0x00 #define REG_POL 0x10 #define REG_SENDER 0x14 #define REG_STATUS 0x18 #define STATUS_FULL 0x80000000 #define STATUS_EMPTY 0x40000000 #define REG_CONFIG 0x1C #define CONFIG_DATA_IRQ 0x00000001 #define REG_WRITE 0x20 /* This is Mailbox 1 address */ #define MBOX_MSG(chan, data) (((data) & ~0xf) | ((chan) & 0xf)) #define MBOX_CHAN(msg) ((msg) & 0xf) #define MBOX_DATA(msg) ((msg) & ~0xf) #define MBOX_LOCK(sc) do { \ mtx_lock(&(sc)->lock); \ } while(0) #define MBOX_UNLOCK(sc) do { \ mtx_unlock(&(sc)->lock); \ } while(0) #ifdef DEBUG #define dprintf(fmt, args...) printf(fmt, ##args) #else #define dprintf(fmt, args...) #endif struct bcm_mbox_softc { struct mtx lock; struct resource * mem_res; struct resource * irq_res; void* intr_hl; bus_space_tag_t bst; bus_space_handle_t bsh; int msg[BCM2835_MBOX_CHANS]; int have_message[BCM2835_MBOX_CHANS]; struct sx property_chan_lock; }; #define mbox_read_4(sc, reg) \ bus_space_read_4((sc)->bst, (sc)->bsh, reg) #define mbox_write_4(sc, reg, val) \ bus_space_write_4((sc)->bst, (sc)->bsh, reg, val) static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-mbox", 1}, {"brcm,bcm2835-mbox", 1}, {NULL, 0} }; static int bcm_mbox_read_msg(struct bcm_mbox_softc *sc, int *ochan) { #ifdef DEBUG uint32_t data; #endif uint32_t msg; int chan; msg = mbox_read_4(sc, REG_READ); dprintf("bcm_mbox_intr: raw data %08x\n", msg); chan = MBOX_CHAN(msg); #ifdef DEBUG data = MBOX_DATA(msg); #endif if (sc->msg[chan]) { printf("bcm_mbox_intr: channel %d oveflow\n", chan); return (1); } dprintf("bcm_mbox_intr: chan %d, data %08x\n", chan, data); sc->msg[chan] = msg; if (ochan != NULL) *ochan = chan; return (0); } static void bcm_mbox_intr(void *arg) { struct bcm_mbox_softc *sc = arg; int chan; MBOX_LOCK(sc); while (!(mbox_read_4(sc, REG_STATUS) & STATUS_EMPTY)) if (bcm_mbox_read_msg(sc, &chan) == 0) { sc->have_message[chan] = 1; wakeup(&sc->have_message[chan]); } MBOX_UNLOCK(sc); } static int bcm_mbox_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2835 VideoCore Mailbox"); return (BUS_PROBE_DEFAULT); } static int bcm_mbox_attach(device_t dev) { struct bcm_mbox_softc *sc = device_get_softc(dev); int i; int rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "could not allocate memory resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->mem_res); sc->bsh = rman_get_bushandle(sc->mem_res); rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "could not allocate interrupt resource\n"); return (ENXIO); } /* Setup and enable the timer */ if (bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE | INTR_TYPE_MISC, NULL, bcm_mbox_intr, sc, &sc->intr_hl) != 0) { bus_release_resource(dev, SYS_RES_IRQ, rid, sc->irq_res); device_printf(dev, "Unable to setup the clock irq handler.\n"); return (ENXIO); } mtx_init(&sc->lock, "vcio mbox", NULL, MTX_DEF); for (i = 0; i < BCM2835_MBOX_CHANS; i++) { sc->msg[i] = 0; sc->have_message[i] = 0; } sx_init(&sc->property_chan_lock, "mboxprop"); /* Read all pending messages */ while ((mbox_read_4(sc, REG_STATUS) & STATUS_EMPTY) == 0) (void)mbox_read_4(sc, REG_READ); mbox_write_4(sc, REG_CONFIG, CONFIG_DATA_IRQ); return (0); } /* * Mailbox API */ static int bcm_mbox_write(device_t dev, int chan, uint32_t data) { int limit = 1000; struct bcm_mbox_softc *sc = device_get_softc(dev); dprintf("bcm_mbox_write: chan %d, data %08x\n", chan, data); MBOX_LOCK(sc); sc->have_message[chan] = 0; while ((mbox_read_4(sc, REG_STATUS) & STATUS_FULL) && --limit) DELAY(5); if (limit == 0) { printf("bcm_mbox_write: STATUS_FULL stuck"); MBOX_UNLOCK(sc); return (EAGAIN); } mbox_write_4(sc, REG_WRITE, MBOX_MSG(chan, data)); MBOX_UNLOCK(sc); return (0); } static int bcm_mbox_read(device_t dev, int chan, uint32_t *data) { struct bcm_mbox_softc *sc = device_get_softc(dev); int err, read_chan; dprintf("bcm_mbox_read: chan %d\n", chan); err = 0; MBOX_LOCK(sc); if (!cold) { if (sc->have_message[chan] == 0) { if (mtx_sleep(&sc->have_message[chan], &sc->lock, 0, "mbox", 10*hz) != 0) { device_printf(dev, "timeout waiting for message on chan %d\n", chan); err = ETIMEDOUT; } } } else { do { /* Wait for a message */ while ((mbox_read_4(sc, REG_STATUS) & STATUS_EMPTY)) ; /* Read the message */ if (bcm_mbox_read_msg(sc, &read_chan) != 0) { err = EINVAL; goto out; } } while (read_chan != chan); } /* * get data from intr handler, the same channel is never coming * because of holding sc lock. */ *data = MBOX_DATA(sc->msg[chan]); sc->msg[chan] = 0; sc->have_message[chan] = 0; out: MBOX_UNLOCK(sc); dprintf("bcm_mbox_read: chan %d, data %08x\n", chan, *data); return (err); } static device_method_t bcm_mbox_methods[] = { DEVMETHOD(device_probe, bcm_mbox_probe), DEVMETHOD(device_attach, bcm_mbox_attach), DEVMETHOD(mbox_read, bcm_mbox_read), DEVMETHOD(mbox_write, bcm_mbox_write), DEVMETHOD_END }; static driver_t bcm_mbox_driver = { "mbox", bcm_mbox_methods, sizeof(struct bcm_mbox_softc), }; static devclass_t bcm_mbox_devclass; EARLY_DRIVER_MODULE(mbox, simplebus, bcm_mbox_driver, bcm_mbox_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); static void bcm2835_mbox_dma_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) { bus_addr_t *addr; if (err) return; addr = (bus_addr_t *)arg; *addr = ARMC_TO_VCBUS(segs[0].ds_addr); } static void * bcm2835_mbox_init_dma(device_t dev, size_t len, bus_dma_tag_t *tag, bus_dmamap_t *map, bus_addr_t *phys) { void *buf; int err; err = bus_dma_tag_create(bus_get_dma_tag(dev), 16, 0, bcm283x_dmabus_peripheral_lowaddr(), BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); if (err != 0) { device_printf(dev, "can't create DMA tag\n"); return (NULL); } err = bus_dmamem_alloc(*tag, &buf, 0, map); if (err != 0) { bus_dma_tag_destroy(*tag); device_printf(dev, "can't allocate dmamem\n"); return (NULL); } err = bus_dmamap_load(*tag, *map, buf, len, bcm2835_mbox_dma_cb, phys, 0); if (err != 0) { bus_dmamem_free(*tag, buf, *map); bus_dma_tag_destroy(*tag); device_printf(dev, "can't load DMA map\n"); return (NULL); } return (buf); } static int bcm2835_mbox_err(device_t dev, bus_addr_t msg_phys, uint32_t resp_phys, struct bcm2835_mbox_hdr *msg, size_t len) { int idx; struct bcm2835_mbox_tag_hdr *tag; uint8_t *last; if ((uint32_t)msg_phys != resp_phys) { device_printf(dev, "response channel mismatch\n"); return (EIO); } if (msg->code != BCM2835_MBOX_CODE_RESP_SUCCESS) { device_printf(dev, "mbox response error\n"); return (EIO); } /* Loop until the end tag. */ tag = (struct bcm2835_mbox_tag_hdr *)(msg + 1); last = (uint8_t *)msg + len; for (idx = 0; tag->tag != 0; idx++) { /* * When setting the GPIO config or state the firmware doesn't * set tag->val_len correctly. */ if ((tag->tag == BCM2835_FIRMWARE_TAG_SET_GPIO_CONFIG || tag->tag == BCM2835_FIRMWARE_TAG_SET_GPIO_STATE) && tag->val_len == 0) { tag->val_len = BCM2835_MBOX_TAG_VAL_LEN_RESPONSE | tag->val_buf_size; } if ((tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE) == 0) { device_printf(dev, "tag %d response error\n", idx); return (EIO); } /* Clear the response bit. */ tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE; /* Next tag. */ tag = (struct bcm2835_mbox_tag_hdr *)((uint8_t *)tag + sizeof(*tag) + tag->val_buf_size); if ((uint8_t *)tag > last) { device_printf(dev, "mbox buffer size error\n"); return (EIO); } } return (0); } int bcm2835_mbox_property(void *msg, size_t msg_size) { struct bcm_mbox_softc *sc; - struct msg_set_power_state *buf; bus_dma_tag_t msg_tag; bus_dmamap_t msg_map; bus_addr_t msg_phys; + char *buf; uint32_t reg; device_t mbox; int err; /* get mbox device */ mbox = devclass_get_device(devclass_find("mbox"), 0); if (mbox == NULL) return (ENXIO); sc = device_get_softc(mbox); sx_xlock(&sc->property_chan_lock); /* Allocate memory for the message */ buf = bcm2835_mbox_init_dma(mbox, msg_size, &msg_tag, &msg_map, &msg_phys); if (buf == NULL) { err = ENOMEM; goto out; } memcpy(buf, msg, msg_size); bus_dmamap_sync(msg_tag, msg_map, BUS_DMASYNC_PREWRITE); MBOX_WRITE(mbox, BCM2835_MBOX_CHAN_PROP, (uint32_t)msg_phys); MBOX_READ(mbox, BCM2835_MBOX_CHAN_PROP, ®); bus_dmamap_sync(msg_tag, msg_map, BUS_DMASYNC_PREREAD); memcpy(msg, buf, msg_size); err = bcm2835_mbox_err(mbox, msg_phys, reg, (struct bcm2835_mbox_hdr *)msg, msg_size); bus_dmamap_unload(msg_tag, msg_map); bus_dmamem_free(msg_tag, buf, msg_map); bus_dma_tag_destroy(msg_tag); out: sx_xunlock(&sc->property_chan_lock); return (err); } int bcm2835_mbox_set_power_state(uint32_t device_id, boolean_t on) { struct msg_set_power_state msg; int err; memset(&msg, 0, sizeof(msg)); msg.hdr.buf_size = sizeof(msg); msg.hdr.code = BCM2835_MBOX_CODE_REQ; msg.tag_hdr.tag = BCM2835_MBOX_TAG_SET_POWER_STATE; msg.tag_hdr.val_buf_size = sizeof(msg.body); msg.tag_hdr.val_len = sizeof(msg.body.req); msg.body.req.device_id = device_id; msg.body.req.state = (on ? BCM2835_MBOX_POWER_ON : 0) | BCM2835_MBOX_POWER_WAIT; msg.end_tag = 0; err = bcm2835_mbox_property(&msg, sizeof(msg)); return (err); } int +bcm2835_mbox_notify_xhci_reset(uint32_t pci_dev_addr) +{ + struct msg_notify_xhci_reset msg; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.hdr.buf_size = sizeof(msg); + msg.hdr.code = BCM2835_MBOX_CODE_REQ; + msg.tag_hdr.tag = BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET; + msg.tag_hdr.val_buf_size = sizeof(msg.body); + msg.tag_hdr.val_len = sizeof(msg.body.req); + msg.body.req.pci_device_addr = pci_dev_addr; + msg.end_tag = 0; + + err = bcm2835_mbox_property(&msg, sizeof(msg)); + + return (err); +} + +int bcm2835_mbox_get_clock_rate(uint32_t clock_id, uint32_t *hz) { struct msg_get_clock_rate msg; int err; memset(&msg, 0, sizeof(msg)); msg.hdr.buf_size = sizeof(msg); msg.hdr.code = BCM2835_MBOX_CODE_REQ; msg.tag_hdr.tag = BCM2835_MBOX_TAG_GET_CLOCK_RATE; msg.tag_hdr.val_buf_size = sizeof(msg.body); msg.tag_hdr.val_len = sizeof(msg.body.req); msg.body.req.clock_id = clock_id; msg.end_tag = 0; err = bcm2835_mbox_property(&msg, sizeof(msg)); *hz = msg.body.resp.rate_hz; return (err); } int bcm2835_mbox_fb_get_w_h(struct bcm2835_fb_config *fb) { int err; struct msg_fb_get_w_h msg; memset(&msg, 0, sizeof(msg)); msg.hdr.buf_size = sizeof(msg); msg.hdr.code = BCM2835_MBOX_CODE_REQ; BCM2835_MBOX_INIT_TAG(&msg.physical_w_h, GET_PHYSICAL_W_H); msg.physical_w_h.tag_hdr.val_len = 0; msg.end_tag = 0; err = bcm2835_mbox_property(&msg, sizeof(msg)); if (err == 0) { fb->xres = msg.physical_w_h.body.resp.width; fb->yres = msg.physical_w_h.body.resp.height; } return (err); } int bcm2835_mbox_fb_get_bpp(struct bcm2835_fb_config *fb) { int err; struct msg_fb_get_bpp msg; memset(&msg, 0, sizeof(msg)); msg.hdr.buf_size = sizeof(msg); msg.hdr.code = BCM2835_MBOX_CODE_REQ; BCM2835_MBOX_INIT_TAG(&msg.bpp, GET_DEPTH); msg.bpp.tag_hdr.val_len = 0; msg.end_tag = 0; err = bcm2835_mbox_property(&msg, sizeof(msg)); if (err == 0) fb->bpp = msg.bpp.body.resp.bpp; return (err); } int bcm2835_mbox_fb_init(struct bcm2835_fb_config *fb) { int err; struct msg_fb_setup msg; memset(&msg, 0, sizeof(msg)); msg.hdr.buf_size = sizeof(msg); msg.hdr.code = BCM2835_MBOX_CODE_REQ; BCM2835_MBOX_INIT_TAG(&msg.physical_w_h, SET_PHYSICAL_W_H); msg.physical_w_h.body.req.width = fb->xres; msg.physical_w_h.body.req.height = fb->yres; BCM2835_MBOX_INIT_TAG(&msg.virtual_w_h, SET_VIRTUAL_W_H); msg.virtual_w_h.body.req.width = fb->vxres; msg.virtual_w_h.body.req.height = fb->vyres; BCM2835_MBOX_INIT_TAG(&msg.offset, SET_VIRTUAL_OFFSET); msg.offset.body.req.x = fb->xoffset; msg.offset.body.req.y = fb->yoffset; BCM2835_MBOX_INIT_TAG(&msg.depth, SET_DEPTH); msg.depth.body.req.bpp = fb->bpp; BCM2835_MBOX_INIT_TAG(&msg.alpha, SET_ALPHA_MODE); msg.alpha.body.req.alpha = BCM2835_MBOX_ALPHA_MODE_IGNORED; BCM2835_MBOX_INIT_TAG(&msg.buffer, ALLOCATE_BUFFER); msg.buffer.body.req.alignment = PAGE_SIZE; BCM2835_MBOX_INIT_TAG(&msg.pitch, GET_PITCH); msg.end_tag = 0; err = bcm2835_mbox_property(&msg, sizeof(msg)); if (err == 0) { fb->xres = msg.physical_w_h.body.resp.width; fb->yres = msg.physical_w_h.body.resp.height; fb->vxres = msg.virtual_w_h.body.resp.width; fb->vyres = msg.virtual_w_h.body.resp.height; fb->xoffset = msg.offset.body.resp.x; fb->yoffset = msg.offset.body.resp.y; fb->pitch = msg.pitch.body.resp.pitch; fb->base = VCBUS_TO_ARMC(msg.buffer.body.resp.fb_address); fb->size = msg.buffer.body.resp.fb_size; } return (err); } + Index: head/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h (revision 363794) +++ head/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h (revision 363795) @@ -1,448 +1,466 @@ /*- * Copyright (C) 2013-2014 Daisuke Aoyama * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _BCM2835_MBOX_PROP_H_ #define _BCM2835_MBOX_PROP_H_ #include #include /* * Mailbox property interface: * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */ #define BCM2835_MBOX_CODE_REQ 0 #define BCM2835_MBOX_CODE_RESP_SUCCESS 0x80000000 #define BCM2835_MBOX_CODE_RESP_ERROR 0x80000001 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 struct bcm2835_mbox_hdr { uint32_t buf_size; uint32_t code; }; struct bcm2835_mbox_tag_hdr { uint32_t tag; uint32_t val_buf_size; uint32_t val_len; }; #define BCM2835_MBOX_INIT_TAG(tag_, tagid_) do { \ (tag_)->tag_hdr.tag = BCM2835_MBOX_TAG_##tagid_; \ (tag_)->tag_hdr.val_buf_size = sizeof((tag_)->body); \ (tag_)->tag_hdr.val_len = sizeof((tag_)->body.req); \ } while (0) #define BCM2835_MBOX_TAG_FIRMWARE_REVISION 0x00000001 #define BCM2835_MBOX_POWER_ID_EMMC 0x00000000 #define BCM2835_MBOX_POWER_ID_UART0 0x00000001 #define BCM2835_MBOX_POWER_ID_UART1 0x00000002 #define BCM2835_MBOX_POWER_ID_USB_HCD 0x00000003 #define BCM2835_MBOX_POWER_ID_I2C0 0x00000004 #define BCM2835_MBOX_POWER_ID_I2C1 0x00000005 #define BCM2835_MBOX_POWER_ID_I2C2 0x00000006 #define BCM2835_MBOX_POWER_ID_SPI 0x00000007 #define BCM2835_MBOX_POWER_ID_CCP2TX 0x00000008 #define BCM2835_MBOX_POWER_ON (1 << 0) #define BCM2835_MBOX_POWER_WAIT (1 << 1) #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 struct msg_get_power_state { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t device_id; } req; struct { uint32_t device_id; uint32_t state; } resp; } body; uint32_t end_tag; }; struct msg_set_power_state { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t device_id; uint32_t state; } req; struct { uint32_t device_id; uint32_t state; } resp; } body; uint32_t end_tag; }; /* Sets the power state for a given device */ int bcm2835_mbox_set_power_state(uint32_t, boolean_t); +#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 + +struct msg_notify_xhci_reset { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + uint32_t pci_device_addr; + } req; + struct { + } resp; + } body; + uint32_t end_tag; +}; + +/* Prompts the VideoCore processor to reload the xhci firmware. */ +int bcm2835_mbox_notify_xhci_reset(uint32_t); + #define BCM2835_MBOX_CLOCK_ID_EMMC 0x00000001 #define BCM2838_MBOX_CLOCK_ID_EMMC2 0x0000000c #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 struct msg_get_clock_rate { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t clock_id; } req; struct { uint32_t clock_id; uint32_t rate_hz; } resp; } body; uint32_t end_tag; }; int bcm2835_mbox_get_clock_rate(uint32_t, uint32_t *); #define BCM2835_MBOX_TURBO_ON 1 #define BCM2835_MBOX_TURBO_OFF 0 #define BCM2835_MBOX_TAG_GET_TURBO 0x00030009 #define BCM2835_MBOX_TAG_SET_TURBO 0x00038009 struct msg_get_turbo { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t id; } req; struct { uint32_t id; uint32_t level; } resp; } body; uint32_t end_tag; }; struct msg_set_turbo { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t id; uint32_t level; } req; struct { uint32_t id; uint32_t level; } resp; } body; uint32_t end_tag; }; #define BCM2835_MBOX_VOLTAGE_ID_CORE 0x00000001 #define BCM2835_MBOX_VOLTAGE_ID_SDRAM_C 0x00000002 #define BCM2835_MBOX_VOLTAGE_ID_SDRAM_P 0x00000003 #define BCM2835_MBOX_VOLTAGE_ID_SDRAM_I 0x00000004 #define BCM2835_MBOX_TAG_GET_VOLTAGE 0x00030003 #define BCM2835_MBOX_TAG_SET_VOLTAGE 0x00038003 #define BCM2835_MBOX_TAG_GET_MAX_VOLTAGE 0x00030005 #define BCM2835_MBOX_TAG_GET_MIN_VOLTAGE 0x00030008 struct msg_get_voltage { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t voltage_id; } req; struct { uint32_t voltage_id; uint32_t value; } resp; } body; uint32_t end_tag; }; struct msg_set_voltage { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t voltage_id; uint32_t value; } req; struct { uint32_t voltage_id; uint32_t value; } resp; } body; uint32_t end_tag; }; struct msg_get_max_voltage { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t voltage_id; } req; struct { uint32_t voltage_id; uint32_t value; } resp; } body; uint32_t end_tag; }; struct msg_get_min_voltage { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t voltage_id; } req; struct { uint32_t voltage_id; uint32_t value; } resp; } body; uint32_t end_tag; }; #define BCM2835_MBOX_TAG_GET_TEMPERATURE 0x00030006 #define BCM2835_MBOX_TAG_GET_MAX_TEMPERATURE 0x0003000a struct msg_get_temperature { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t temperature_id; } req; struct { uint32_t temperature_id; uint32_t value; } resp; } body; uint32_t end_tag; }; struct msg_get_max_temperature { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t temperature_id; } req; struct { uint32_t temperature_id; uint32_t value; } resp; } body; uint32_t end_tag; }; #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 struct bcm2835_mbox_tag_fb_w_h { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t width; uint32_t height; } req; struct { uint32_t width; uint32_t height; } resp; } body; }; #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 struct bcm2835_mbox_tag_depth { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t bpp; } req; struct { uint32_t bpp; } resp; } body; }; #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 struct bcm2835_mbox_tag_alpha_mode { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t alpha; } req; struct { uint32_t alpha; } resp; } body; }; #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 struct bcm2835_mbox_tag_virtual_offset { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t x; uint32_t y; } req; struct { uint32_t x; uint32_t y; } resp; } body; }; #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 struct bcm2835_mbox_tag_pitch { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { } req; struct { uint32_t pitch; } resp; } body; }; #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 struct bcm2835_mbox_tag_allocate_buffer { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { uint32_t alignment; } req; struct { uint32_t fb_address; uint32_t fb_size; } resp; } body; }; #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 struct bcm2835_mbox_tag_release_buffer { struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { } req; struct { } resp; } body; }; #define BCM2835_MBOX_TAG_GET_TOUCHBUF 0x0004000f struct bcm2835_mbox_tag_touchbuf { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_hdr tag_hdr; union { struct { } req; struct { uint32_t address; } resp; } body; uint32_t end_tag; }; struct bcm2835_fb_config { uint32_t xres; uint32_t yres; uint32_t vxres; uint32_t vyres; uint32_t xoffset; uint32_t yoffset; uint32_t bpp; uint32_t pitch; uint32_t base; uint32_t size; }; struct msg_fb_get_w_h { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_fb_w_h physical_w_h; uint32_t end_tag; }; int bcm2835_mbox_fb_get_w_h(struct bcm2835_fb_config *); struct msg_fb_get_bpp { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_depth bpp; uint32_t end_tag; }; int bcm2835_mbox_fb_get_bpp(struct bcm2835_fb_config *); struct msg_fb_setup { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_fb_w_h physical_w_h; struct bcm2835_mbox_tag_fb_w_h virtual_w_h; struct bcm2835_mbox_tag_virtual_offset offset; struct bcm2835_mbox_tag_depth depth; struct bcm2835_mbox_tag_alpha_mode alpha; struct bcm2835_mbox_tag_allocate_buffer buffer; struct bcm2835_mbox_tag_pitch pitch; uint32_t end_tag; }; int bcm2835_mbox_fb_init(struct bcm2835_fb_config *); int bcm2835_mbox_property(void *, size_t); #endif /* _BCM2835_MBOX_PROP_H_ */ Index: head/sys/arm/broadcom/bcm2835/bcm2838_xhci.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2838_xhci.c (nonexistent) +++ head/sys/arm/broadcom/bcm2835/bcm2838_xhci.c (revision 363795) @@ -0,0 +1,217 @@ +/*- + * SPDX-License-Identifier: ISC + * + * Copyright (c) 2020 Dr Robert Harvey Crowston + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * + * $FreeBSD$ + * + */ + +/* + * VIA VL805 controller on the Raspberry Pi 4. + * The VL805 is a generic xhci controller. However, in the newer hardware + * revisions of the Raspberry Pi 4, it is incapable of loading its own firmware. + * Instead, the VideoCore GPU must load the firmware into the controller at the + * appropriate time. This driver is a shim that pre-loads the firmware before + * handing control to the xhci generic driver. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define VL805_FIRMWARE_REG 0x50 +#define PCIE_BUS_SHIFT 20 +#define PCIE_SLOT_SHIFT 15 +#define PCIE_FUNC_SHIFT 12 + +static int +bcm_xhci_probe(device_t dev) +{ + phandle_t root; + uint32_t device_id; + + device_id = pci_get_devid(dev); + if (device_id != 0x34831106) /* VIA VL805 USB 3.0 controller. */ + return (ENXIO); + + /* + * The VIA chip is not unique to the Pi, but we only want to use this + * driver if the SoC is a Raspberry Pi 4. Walk the device tree to + * discover if the system is a Pi 4. + */ + root = OF_finddevice("/"); + if (root == -1) + return (ENXIO); + if (!ofw_bus_node_is_compatible(root, "raspberrypi,4-model-b")) + return (ENXIO); + + /* + * On the Pi 4, the VIA chip with the firmware-loading limitation is + * soldered-on to a particular bus/slot/function. But, it's possible a + * user could desolder the VIA chip, replace it with a pci-pci bridge, + * then plug in a commodity VIA PCI-e card on the new bridge. In that + * case we don't want to try to load the firmware to a commodity + * expansion card. + */ + if (pci_get_bus(dev) != 1 || pci_get_slot(dev) != 0 || + pci_get_function(dev) != 0 ) + return (ENXIO); + + device_set_desc(dev, + "VL805 USB 3.0 controller (on the Raspberry Pi 4b)"); + + return (BUS_PROBE_SPECIFIC); +} + +static uint32_t +bcm_xhci_check_firmware(device_t dev, bool expect_loaded) +{ + uint32_t revision; + bool loaded; + + revision = pci_read_config(dev, VL805_FIRMWARE_REG, 4); + loaded = !(revision == 0 || revision == 0xffffffff); + + if (expect_loaded && !loaded) + device_printf(dev, "warning: xhci firmware not found.\n"); + else if (bootverbose && !loaded) + device_printf(dev, "note: xhci firmware not found.\n"); + else if (bootverbose) + device_printf(dev, + "note: xhci firmware detected; firmware is revision %x.\n", + revision); + + if (!loaded) + return 0; + + return (revision); +} + +static void +bcm_xhci_install_xhci_firmware(device_t dev) +{ + uint32_t revision, dev_addr; + int error; + + revision = bcm_xhci_check_firmware(dev, false); + if (revision > 0) { + /* + * With the pre-June 2020 boot firmware, it does not seem + * possible to reload already-installed xhci firmware. + */ + return; + } + + /* + * Notify the VideoCore gpu processor that it needs to reload the xhci + * firmware into the xhci controller. This needs to happen after the pci + * bridge topology is registered with the controller. + */ + if (bootverbose) + device_printf(dev, "note: installing xhci firmware.\n"); + + dev_addr = + pci_get_bus(dev) << PCIE_BUS_SHIFT | + pci_get_slot(dev) << PCIE_SLOT_SHIFT | + pci_get_function(dev) << PCIE_FUNC_SHIFT; + + error = bcm2835_mbox_notify_xhci_reset(dev_addr); + if (error) + device_printf(dev, + "warning: xhci firmware install failed (error %d).\n", + error); + + DELAY(1000); + bcm_xhci_check_firmware(dev, true); + + return; +} + +static int +bcm_xhci_attach(device_t dev) +{ + struct xhci_softc *sc; + int error; + + sc = device_get_softc(dev); + + bcm_xhci_install_xhci_firmware(dev); + + error = xhci_pci_attach(dev); + if (error) + return (error); + + /* 32 bit DMA is a limitation of the PCI-e controller, not the VL805. */ + sc->sc_bus.dma_bits = 32; + if (bootverbose) + device_printf(dev, "note: switched to 32-bit DMA.\n"); + + return (0); +} + +/* + * Device method table. + */ +static device_method_t bcm_xhci_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, bcm_xhci_probe), + DEVMETHOD(device_attach, bcm_xhci_attach), +}; + +DEFINE_CLASS_1(bcm_xhci, bcm_xhci_driver, bcm_xhci_methods, + sizeof(struct xhci_softc), xhci_pci_driver); + +static devclass_t xhci_devclass; +DRIVER_MODULE(bcm_xhci, pci, bcm_xhci_driver, xhci_devclass, 0, 0); MODULE_DEPEND(bcm_xhci, usb, 1, 1, 1); + Property changes on: head/sys/arm/broadcom/bcm2835/bcm2838_xhci.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/broadcom/bcm2835/files.bcm283x =================================================================== --- head/sys/arm/broadcom/bcm2835/files.bcm283x (revision 363794) +++ head/sys/arm/broadcom/bcm2835/files.bcm283x (revision 363795) @@ -1,47 +1,48 @@ # $FreeBSD$ arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc arm/broadcom/bcm2835/bcm2835_cpufreq.c standard arm/broadcom/bcm2835/bcm2835_dma.c standard arm/broadcom/bcm2835/bcm2835_fb.c optional sc arm/broadcom/bcm2835/bcm2835_fbd.c optional vt arm/broadcom/bcm2835/bcm2835_firmware.c standard arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio arm/broadcom/bcm2835/bcm2835_intr.c standard arm/broadcom/bcm2835/bcm2835_machdep.c optional platform arm/broadcom/bcm2835/bcm2835_mbox.c standard arm/broadcom/bcm2835/bcm2835_rng.c optional random arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi arm/broadcom/bcm2835/bcm2835_vcbus.c standard arm/broadcom/bcm2835/bcm2835_vcio.c standard arm/broadcom/bcm2835/bcm2835_wdog.c standard arm/broadcom/bcm2835/bcm2838_pci.c optional pci +arm/broadcom/bcm2835/bcm2838_xhci.c optional xhci arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt dev/mbox/mbox_if.m standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" # VideoCore driver contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 363794) +++ head/sys/conf/files.arm64 (revision 363795) @@ -1,415 +1,416 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_firmware.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci +arm/broadcom/bcm2835/bcm2838_xhci.c optional soc_brcm_bcm2838 fdt pci xhci arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional fdt pci arm64/broadcom/genet/if_genet.c optional SOC_BRCM_BCM2838 fdt genet arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_acpi.c optional acpi arm64/coresight/coresight_fdt.c optional fdt arm64/coresight/coresight_if.m standard arm64/coresight/coresight_cmd.c standard arm64/coresight/coresight_cpu_debug.c standard arm64/coresight/coresight_etm4x.c standard arm64/coresight/coresight_etm4x_acpi.c optional acpi arm64/coresight/coresight_etm4x_fdt.c optional fdt arm64/coresight/coresight_funnel.c standard arm64/coresight/coresight_funnel_acpi.c optional acpi arm64/coresight/coresight_funnel_fdt.c optional fdt arm64/coresight/coresight_replicator.c standard arm64/coresight/coresight_replicator_acpi.c optional acpi arm64/coresight/coresight_replicator_fdt.c optional fdt arm64/coresight/coresight_tmc.c standard arm64/coresight/coresight_tmc_acpi.c optional acpi arm64/coresight/coresight_tmc_fdt.c optional fdt arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10 arm64/qoriq/ls1046_gpio.c optional ls1046_gpio gpio fdt SOC_NXP_LS arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clkgen.c optional clk SOC_NXP_LS arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/des/des_enc.c optional netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_fsl_fdt.c optional SOC_NXP_LS ahci fdt dev/ahci/ahci_generic.c optional ahci dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sriov.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01030900 -mice_ddp -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.9.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.9.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard dev/safexcel/safexcel.c optional safexcel fdt dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/bcmp.c standard libkern/memcmp.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/memset.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 # i.MX8 Clock support arm64/freescale/imx/imx8mq_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_gate.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_mux.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_composite.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_sscg_pll.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_frac_pll.c optional fdt soc_freescale_imx8 # iMX drivers arm/freescale/imx/imx_gpio.c optional gpio soc_freescale_imx8 arm/freescale/imx/imx_i2c.c optional fsliic arm/freescale/imx/imx_machdep.c optional fdt soc_freescale_imx8 arm64/freescale/imx/imx7gpc.c optional fdt soc_freescale_imx8 dev/ffec/if_ffec.c optional ffec Index: head/sys/dev/usb/controller/xhci.h =================================================================== --- head/sys/dev/usb/controller/xhci.h (revision 363794) +++ head/sys/dev/usb/controller/xhci.h (revision 363795) @@ -1,548 +1,551 @@ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _XHCI_H_ #define _XHCI_H_ #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ #define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */ #define XHCI_MAX_EVENTS (16 * 13) #define XHCI_MAX_COMMANDS (16 * 1) #define XHCI_MAX_RSEG 1 #define XHCI_MAX_TRANSFERS 4 #if USB_MAX_EP_STREAMS == 8 #define XHCI_MAX_STREAMS 8 #define XHCI_MAX_STREAMS_LOG 3 #elif USB_MAX_EP_STREAMS == 1 #define XHCI_MAX_STREAMS 1 #define XHCI_MAX_STREAMS_LOG 0 #else #error "The USB_MAX_EP_STREAMS value is not supported." #endif #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE #define XHCI_TRB_ALIGN 16 /* bytes */ #define XHCI_TD_ALIGN 64 /* bytes */ #define XHCI_PAGE_SIZE 4096 /* bytes */ struct xhci_dev_ctx_addr { volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; struct { volatile uint64_t dummy; } __aligned(64) padding; volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; }; #define XHCI_EPNO2EPID(x) \ ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) struct xhci_slot_ctx { volatile uint32_t dwSctx0; #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) volatile uint32_t dwSctx1; #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) volatile uint32_t dwSctx2; #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) volatile uint32_t dwSctx3; #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) volatile uint32_t dwSctx4; volatile uint32_t dwSctx5; volatile uint32_t dwSctx6; volatile uint32_t dwSctx7; }; struct xhci_endp_ctx { volatile uint32_t dwEpCtx0; #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) #define XHCI_EPCTX_0_EPSTATE_DISABLED 0 #define XHCI_EPCTX_0_EPSTATE_RUNNING 1 #define XHCI_EPCTX_0_EPSTATE_HALTED 2 #define XHCI_EPCTX_0_EPSTATE_STOPPED 3 #define XHCI_EPCTX_0_EPSTATE_ERROR 4 #define XHCI_EPCTX_0_EPSTATE_RESERVED_5 5 #define XHCI_EPCTX_0_EPSTATE_RESERVED_6 6 #define XHCI_EPCTX_0_EPSTATE_RESERVED_7 7 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) volatile uint32_t dwEpCtx1; #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) volatile uint64_t qwEpCtx2; #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U volatile uint32_t dwEpCtx4; #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) volatile uint32_t dwEpCtx5; volatile uint32_t dwEpCtx6; volatile uint32_t dwEpCtx7; }; struct xhci_input_ctx { #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU volatile uint32_t dwInCtx0; #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) volatile uint32_t dwInCtx1; #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) volatile uint32_t dwInCtx2; volatile uint32_t dwInCtx3; volatile uint32_t dwInCtx4; volatile uint32_t dwInCtx5; volatile uint32_t dwInCtx6; volatile uint32_t dwInCtx7; }; struct xhci_input_dev_ctx { struct xhci_input_ctx ctx_input; struct xhci_slot_ctx ctx_slot; struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; }; struct xhci_dev_ctx { struct xhci_slot_ctx ctx_slot; struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; } __aligned(XHCI_DEV_CTX_ALIGN); struct xhci_stream_ctx { volatile uint64_t qwSctx0; #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U volatile uint32_t dwSctx2; volatile uint32_t dwSctx3; }; struct xhci_trb { volatile uint64_t qwTrb0; #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) volatile uint32_t dwTrb2; #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) volatile uint32_t dwTrb3; #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) #define XHCI_TRB_3_CYCLE_BIT (1U << 0) #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ #define XHCI_TRB_3_ISP_BIT (1U << 2) #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) #define XHCI_TRB_3_CHAIN_BIT (1U << 4) #define XHCI_TRB_3_IOC_BIT (1U << 5) #define XHCI_TRB_3_IDT_BIT (1U << 6) #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) #define XHCI_TRB_3_BEI_BIT (1U << 9) #define XHCI_TRB_3_DCEP_BIT (1U << 9) #define XHCI_TRB_3_PRSV_BIT (1U << 9) #define XHCI_TRB_3_BSR_BIT (1U << 9) #define XHCI_TRB_3_TRT_MASK (3U << 16) #define XHCI_TRB_3_TRT_NONE (0U << 16) #define XHCI_TRB_3_TRT_OUT (2U << 16) #define XHCI_TRB_3_TRT_IN (3U << 16) #define XHCI_TRB_3_DIR_IN (1U << 16) #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) /* Commands */ #define XHCI_TRB_TYPE_RESERVED 0x00 #define XHCI_TRB_TYPE_NORMAL 0x01 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 #define XHCI_TRB_TYPE_ISOCH 0x05 #define XHCI_TRB_TYPE_LINK 0x06 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 #define XHCI_TRB_TYPE_NOOP 0x08 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D #define XHCI_TRB_TYPE_RESET_EP 0x0E #define XHCI_TRB_TYPE_STOP_EP 0x0F #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 /* Events */ #define XHCI_TRB_EVENT_TRANSFER 0x20 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 #define XHCI_TRB_EVENT_DOORBELL 0x24 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 /* Error codes */ #define XHCI_TRB_ERROR_INVALID 0x00 #define XHCI_TRB_ERROR_SUCCESS 0x01 #define XHCI_TRB_ERROR_DATA_BUF 0x02 #define XHCI_TRB_ERROR_BABBLE 0x03 #define XHCI_TRB_ERROR_XACT 0x04 #define XHCI_TRB_ERROR_TRB 0x05 #define XHCI_TRB_ERROR_STALL 0x06 #define XHCI_TRB_ERROR_RESOURCE 0x07 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C #define XHCI_TRB_ERROR_SHORT_PKT 0x0D #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 #define XHCI_TRB_ERROR_PARAMETER 0x11 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 #define XHCI_TRB_ERROR_STOPPED 0x1A #define XHCI_TRB_ERROR_LENGTH 0x1B #define XHCI_TRB_ERROR_BAD_MELAT 0x1D #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F #define XHCI_TRB_ERROR_EVENT_LOST 0x20 #define XHCI_TRB_ERROR_UNDEFINED 0x21 #define XHCI_TRB_ERROR_INVALID_SID 0x22 #define XHCI_TRB_ERROR_SEC_BW 0x23 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 } __aligned(4); struct xhci_dev_endpoint_trbs { struct xhci_trb trb[(XHCI_MAX_STREAMS * XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; }; #if (USB_PAGE_SIZE < 4096) #error "The XHCI driver needs a pagesize above or equal to 4K" #endif /* Define the maximum payload which we will handle in a single TRB */ #define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */ /* Define the maximum payload of a single scatter-gather list element */ #define XHCI_TD_PAGE_SIZE \ ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX) /* Define the maximum length of the scatter-gather list */ #define XHCI_TD_PAGE_NBUF \ (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1) struct xhci_td { /* one LINK TRB has been added to the TRB array */ struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; /* * Extra information needed: */ uint64_t td_self; struct xhci_td *next; struct xhci_td *alt_next; struct xhci_td *obj_next; struct usb_page_cache *page_cache; uint32_t len; uint32_t remainder; uint8_t ntrb; uint8_t status; } __aligned(XHCI_TRB_ALIGN); struct xhci_command { struct xhci_trb trb; TAILQ_ENTRY(xhci_command) entry; }; struct xhci_event_ring_seg { volatile uint64_t qwEvrsTablePtr; volatile uint32_t dwEvrsTableSize; volatile uint32_t dwEvrsReserved; }; struct xhci_hw_root { struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; struct { volatile uint64_t dummy; } __aligned(64) padding; struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; }; struct xhci_endpoint_ext { struct xhci_trb *trb; struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; struct usb_page_cache *page_cache; uint64_t physaddr; uint8_t trb_used[XHCI_MAX_STREAMS]; uint8_t trb_index[XHCI_MAX_STREAMS]; uint8_t trb_halted; uint8_t trb_running; uint8_t trb_ep_mode; uint8_t trb_ep_maxp; }; enum { XHCI_ST_DISABLED, XHCI_ST_ENABLED, XHCI_ST_DEFAULT, XHCI_ST_ADDRESSED, XHCI_ST_CONFIGURED, XHCI_ST_MAX }; struct xhci_hw_dev { struct usb_page_cache device_pc; struct usb_page_cache input_pc; struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; struct usb_page device_pg; struct usb_page input_pg; struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; uint32_t ep_configured; uint8_t state; uint8_t nports; uint8_t tt; uint8_t context_num; }; struct xhci_hw_softc { struct usb_page_cache root_pc; struct usb_page_cache ctx_pc; struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; struct usb_page root_pg; struct usb_page ctx_pg; struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; }; struct xhci_config_desc { struct usb_config_descriptor confd; struct usb_interface_descriptor ifcd; struct usb_endpoint_descriptor endpd; struct usb_endpoint_ss_comp_descriptor endpcd; } __packed; struct xhci_bos_desc { struct usb_bos_descriptor bosd; struct usb_devcap_usb2ext_descriptor usb2extd; struct usb_devcap_ss_descriptor usbdcd; struct usb_devcap_container_id_descriptor cidd; } __packed; union xhci_hub_desc { struct usb_status stat; struct usb_port_status ps; struct usb_hub_ss_descriptor hubd; uint8_t temp[128]; }; typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); struct xhci_softc { struct xhci_hw_softc sc_hw; /* base device */ struct usb_bus sc_bus; /* configure message */ struct usb_bus_msg sc_config_msg[2]; struct usb_callout sc_callout; xhci_port_route_t *sc_port_route; union xhci_hub_desc sc_hub_desc; struct cv sc_cmd_cv; struct sx sc_cmd_sx; struct usb_device *sc_devices[XHCI_MAX_DEVICES]; struct resource *sc_io_res; struct resource *sc_irq_res; struct resource *sc_msix_res; void *sc_intr_hdl; bus_size_t sc_io_size; bus_space_tag_t sc_io_tag; bus_space_handle_t sc_io_hdl; /* last pending command address */ uint64_t sc_cmd_addr; /* result of command */ uint32_t sc_cmd_result[2]; /* copy of cmd register */ uint32_t sc_cmd; /* worst case exit latency */ uint32_t sc_exit_lat_max; /* offset to operational registers */ uint32_t sc_oper_off; /* offset to capability registers */ uint32_t sc_capa_off; /* offset to runtime registers */ uint32_t sc_runt_off; /* offset to doorbell registers */ uint32_t sc_door_off; /* chip specific */ uint16_t sc_erst_max; uint16_t sc_event_idx; uint16_t sc_command_idx; uint16_t sc_imod_default; /* number of scratch pages */ uint16_t sc_noscratch; uint8_t sc_event_ccs; uint8_t sc_command_ccs; /* number of XHCI device slots */ uint8_t sc_noslot; /* number of ports on root HUB */ uint8_t sc_noport; /* root HUB device configuration */ uint8_t sc_conf; /* step status stage of all control transfers */ uint8_t sc_ctlstep; /* root HUB port event bitmap, max 256 ports */ uint8_t sc_hub_idata[32]; /* size of context */ uint8_t sc_ctx_is_64_byte; /* vendor string for root HUB */ char sc_vendor[16]; }; #define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx) #define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx) #define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED) /* prototypes */ uint8_t xhci_use_polling(void); usb_error_t xhci_halt_controller(struct xhci_softc *); usb_error_t xhci_reset_controller(struct xhci_softc *); usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); usb_error_t xhci_start_controller(struct xhci_softc *); void xhci_interrupt(struct xhci_softc *); void xhci_uninit(struct xhci_softc *); +int xhci_pci_attach(device_t); + +DECLARE_CLASS(xhci_pci_driver); #endif /* _XHCI_H_ */ Index: head/sys/dev/usb/controller/xhci_pci.c =================================================================== --- head/sys/dev/usb/controller/xhci_pci.c (revision 363794) +++ head/sys/dev/usb/controller/xhci_pci.c (revision 363795) @@ -1,455 +1,451 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "usb_if.h" static device_probe_t xhci_pci_probe; -static device_attach_t xhci_pci_attach; static device_detach_t xhci_pci_detach; static usb_take_controller_t xhci_pci_take_controller; static device_method_t xhci_device_methods[] = { /* device interface */ DEVMETHOD(device_probe, xhci_pci_probe), DEVMETHOD(device_attach, xhci_pci_attach), DEVMETHOD(device_detach, xhci_pci_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(usb_take_controller, xhci_pci_take_controller), DEVMETHOD_END }; -static driver_t xhci_driver = { - .name = "xhci", - .methods = xhci_device_methods, - .size = sizeof(struct xhci_softc), -}; +DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, + sizeof(struct xhci_softc)); static devclass_t xhci_devclass; -DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); +DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL); MODULE_DEPEND(xhci, usb, 1, 1, 1); static const char * xhci_pci_match(device_t self) { uint32_t device_id = pci_get_devid(self); switch (device_id) { case 0x145c1022: return ("AMD KERNCZ USB 3.0 controller"); case 0x43ba1022: return ("AMD X399 USB 3.0 controller"); case 0x43b91022: /* X370 */ case 0x43bb1022: /* B350 */ return ("AMD 300 Series USB 3.0 controller"); case 0x78141022: return ("AMD FCH USB 3.0 controller"); case 0x145f1d94: return ("Hygon USB 3.0 controller"); case 0x01941033: return ("NEC uPD720200 USB 3.0 controller"); case 0x00151912: return ("NEC uPD720202 USB 3.0 controller"); case 0x10001b73: return ("Fresco Logic FL1000G USB 3.0 controller"); case 0x11001b73: return ("Fresco Logic FL1100 USB 3.0 controller"); case 0x10421b21: return ("ASMedia ASM1042 USB 3.0 controller"); case 0x11421b21: return ("ASMedia ASM1042A USB 3.0 controller"); case 0x0f358086: return ("Intel BayTrail USB 3.0 controller"); case 0x19d08086: return ("Intel Denverton USB 3.0 controller"); case 0x9c318086: case 0x1e318086: return ("Intel Panther Point USB 3.0 controller"); case 0x22b58086: return ("Intel Braswell USB 3.0 controller"); case 0x5aa88086: return ("Intel Apollo Lake USB 3.0 controller"); case 0x8c318086: return ("Intel Lynx Point USB 3.0 controller"); case 0x8cb18086: return ("Intel Wildcat Point USB 3.0 controller"); case 0x8d318086: return ("Intel Wellsburg USB 3.0 controller"); case 0x9cb18086: return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); case 0x9d2f8086: return ("Intel Sunrise Point-LP USB 3.0 controller"); case 0xa12f8086: return ("Intel Sunrise Point USB 3.0 controller"); case 0xa1af8086: return ("Intel Lewisburg USB 3.0 controller"); case 0xa2af8086: return ("Intel Union Point USB 3.0 controller"); case 0xa36d8086: return ("Intel Cannon Lake USB 3.1 controller"); case 0xa01b177d: return ("Cavium ThunderX USB 3.0 controller"); default: break; } if ((pci_get_class(self) == PCIC_SERIALBUS) && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { return ("XHCI (generic) USB 3.0 controller"); } return (NULL); /* dunno */ } static int xhci_pci_probe(device_t self) { const char *desc = xhci_pci_match(self); if (desc) { device_set_desc(self, desc); return (BUS_PROBE_DEFAULT); } else { return (ENXIO); } } static int xhci_use_msi = 1; TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); static int xhci_use_msix = 1; TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); static void xhci_interrupt_poll(void *_sc) { struct xhci_softc *sc = _sc; USB_BUS_UNLOCK(&sc->sc_bus); xhci_interrupt(sc); USB_BUS_LOCK(&sc->sc_bus); usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); } static int xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) { uint32_t temp; uint32_t usb3_mask; uint32_t usb2_mask; temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); temp |= set; temp &= ~clear; /* Don't set bits which the hardware doesn't support */ usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); device_printf(self, "Port routing mask set to 0x%08x\n", temp); return (0); } -static int +int xhci_pci_attach(device_t self) { struct xhci_softc *sc = device_get_softc(self); int count, err, msix_table, rid; uint8_t usemsi = 1; uint8_t usedma32 = 0; rid = PCI_XHCI_CBMEM; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); return (ENOMEM); } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); switch (pci_get_devid(self)) { case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ /* Don't use 64-bit DMA on these controllers. */ usedma32 = 1; break; case 0x10001b73: /* FL1000G */ /* Fresco Logic host doesn't support MSI. */ usemsi = 0; break; case 0x0f358086: /* BayTrail */ case 0x9c318086: /* Panther Point */ case 0x1e318086: /* Panther Point */ case 0x8c318086: /* Lynx Point */ case 0x8cb18086: /* Wildcat Point */ case 0x9cb18086: /* Broadwell Mobile Integrated */ /* * On Intel chipsets, reroute ports from EHCI to XHCI * controller and use a different IMOD value. */ sc->sc_port_route = &xhci_pci_port_route; sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; sc->sc_ctlstep = 1; break; } if (xhci_init(sc, self, usedma32)) { device_printf(self, "Could not initialize softc\n"); bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, sc->sc_io_res); return (ENXIO); } pci_enable_busmaster(self); usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); rid = 0; if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { sc->sc_msix_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &msix_table, RF_ACTIVE); if (sc->sc_msix_res == NULL) { /* May not be enabled */ device_printf(self, "Unable to map MSI-X table \n"); } else { count = 1; if (pci_alloc_msix(self, &count) == 0) { if (bootverbose) device_printf(self, "MSI-X enabled\n"); rid = 1; } else { bus_release_resource(self, SYS_RES_MEMORY, msix_table, sc->sc_msix_res); sc->sc_msix_res = NULL; } } } if (rid == 0 && xhci_use_msi && usemsi) { count = 1; if (pci_alloc_msi(self, &count) == 0) { if (bootverbose) device_printf(self, "MSI enabled\n"); rid = 1; } } sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); if (sc->sc_irq_res == NULL) { pci_release_msi(self); device_printf(self, "Could not allocate IRQ\n"); /* goto error; FALLTHROUGH - use polling */ } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (sc->sc_bus.bdev == NULL) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); if (sc->sc_irq_res != NULL) { err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); if (err != 0) { bus_release_resource(self, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); sc->sc_irq_res = NULL; pci_release_msi(self); device_printf(self, "Could not setup IRQ, err=%d\n", err); sc->sc_intr_hdl = NULL; } } if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { if (xhci_use_polling() != 0) { device_printf(self, "Interrupt polling at %dHz\n", hz); USB_BUS_LOCK(&sc->sc_bus); xhci_interrupt_poll(sc); USB_BUS_UNLOCK(&sc->sc_bus); } else goto error; } xhci_pci_take_controller(self); err = xhci_halt_controller(sc); if (err == 0) err = xhci_start_controller(sc); if (err == 0) err = device_probe_and_attach(sc->sc_bus.bdev); if (err) { device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); goto error; } return (0); error: xhci_pci_detach(self); return (ENXIO); } static int xhci_pci_detach(device_t self) { struct xhci_softc *sc = device_get_softc(self); /* during module unload there are lots of children leftover */ device_delete_children(self); usb_callout_drain(&sc->sc_callout); xhci_halt_controller(sc); xhci_reset_controller(sc); pci_disable_busmaster(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); sc->sc_irq_res = NULL; pci_release_msi(self); } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, sc->sc_io_res); sc->sc_io_res = NULL; } if (sc->sc_msix_res) { bus_release_resource(self, SYS_RES_MEMORY, rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); sc->sc_msix_res = NULL; } xhci_uninit(sc); return (0); } static int xhci_pci_take_controller(device_t self) { struct xhci_softc *sc = device_get_softc(self); uint32_t cparams; uint32_t eecp; uint32_t eec; uint16_t to; uint8_t bios_sem; cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); eec = -1; /* Synchronise with the BIOS if it owns the controller. */ for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); eecp += XHCI_XECP_NEXT(eec) << 2) { eec = XREAD4(sc, capa, eecp); if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) continue; bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); if (bios_sem == 0) continue; device_printf(sc->sc_bus.bdev, "waiting for BIOS " "to give up control\n"); XWRITE1(sc, capa, eecp + XHCI_XECP_OS_SEM, 1); to = 500; while (1) { bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); if (bios_sem == 0) break; if (--to == 0) { device_printf(sc->sc_bus.bdev, "timed out waiting for BIOS\n"); break; } usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ } } return (0); }